Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	384882479	0	0	0
ctrl_en_input_filter_rd_A	384882479	554686	0	0
intr_ctrl_en_falling_rd_A	384882479	593594	0	0
intr_ctrl_en_lvlhigh_rd_A	384882479	554516	0	0
intr_ctrl_en_lvllow_rd_A	384882479	596486	0	0
intr_ctrl_en_rising_rd_A	384882479	557859	0	0
intr_enable_rd_A	384882479	554323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	554686	0	0
T1	2400	55	0	0
T2	0	20	0	0
T3	0	67	0	0
T4	0	669	0	0
T5	0	35	0	0
T6	0	74	0	0
T7	0	8	0	0
T8	0	14	0	0
T9	0	129	0	0
T10	0	4	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	593594	0	0
T1	2400	26	0	0
T2	0	5	0	0
T3	0	65	0	0
T4	0	620	0	0
T5	0	29	0	0
T6	0	88	0	0
T8	0	14	0	0
T9	0	91	0	0
T10	0	1	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	0	0	0
T20	0	91	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	554516	0	0
T1	2400	19	0	0
T2	0	9	0	0
T3	0	84	0	0
T4	0	722	0	0
T5	0	33	0	0
T6	0	71	0	0
T7	0	3	0	0
T8	0	10	0	0
T9	0	93	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	0	0	0
T20	0	56	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	596486	0	0
T1	2400	70	0	0
T2	0	12	0	0
T3	0	80	0	0
T4	0	708	0	0
T5	0	28	0	0
T6	0	49	0	0
T7	0	1	0	0
T8	0	25	0	0
T9	0	113	0	0
T10	0	4	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	557859	0	0
T1	2400	35	0	0
T2	0	12	0	0
T3	0	91	0	0
T4	0	678	0	0
T5	0	30	0	0
T6	0	79	0	0
T7	0	9	0	0
T8	0	16	0	0
T9	0	72	0	0
T10	0	8	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384882479	554323	0	0
T1	2400	41	0	0
T2	0	7	0	0
T3	0	103	0	0
T4	0	678	0	0
T5	0	21	0	0
T6	0	73	0	0
T7	0	5	0	0
T8	0	58	0	0
T11	3681	0	0	0
T12	8334	0	0	0
T13	17396	0	0	0
T14	1023	0	0	0
T15	984	0	0	0
T16	1270	0	0	0
T17	1187	0	0	0
T18	2800	0	0	0
T19	1112	24	0	0
T21	0	17	0	0