Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4559005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21454535

1

T25

40

T26

216

T27

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10105137	1			T25	29		T26	103		T27	11
values[0x0]	7801372	1			T25	9		T26	61		T27	6
values[0x1]	8107031	1			T25	20		T26	52		T27	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3476351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22537189

1

T25

44

T26

216

T27

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96261	1			T29	6		T34	1		T11	3
valid_sources[0x01]	92707	1			T26	1		T31	1		T34	1
valid_sources[0x02]	100616	1			T26	2		T31	1		T34	6
valid_sources[0x03]	100132	1			T31	1		T34	3		T11	1
valid_sources[0x04]	105329	1			T26	3		T31	2		T33	22
valid_sources[0x05]	103251	1			T26	2		T1	1		T11	7
valid_sources[0x06]	103669	1			T26	2		T34	1		T1	2
valid_sources[0x07]	97778	1			T26	1		T31	1		T33	14
valid_sources[0x08]	101403	1			T34	3		T1	1		T11	2
valid_sources[0x09]	98338	1			T26	1		T31	1		T33	4
valid_sources[0x0a]	109435	1			T31	1		T33	2		T34	1
valid_sources[0x0b]	95880	1			T31	2		T11	5		T15	13
valid_sources[0x0c]	93190	1			T30	1		T31	2		T34	3
valid_sources[0x0d]	104958	1			T31	2		T34	1		T11	3
valid_sources[0x0e]	87439	1			T26	1		T1	3		T11	3
valid_sources[0x0f]	91939	1			T30	1		T34	2		T11	4
valid_sources[0x10]	90902	1			T26	4		T34	3		T11	4
valid_sources[0x11]	96029	1			T30	1		T34	4		T11	2
valid_sources[0x12]	95935	1			T26	4		T31	2		T33	3
valid_sources[0x13]	188194	1			T31	3		T34	2		T11	5
valid_sources[0x14]	142818	1			T26	1		T31	1		T34	1
valid_sources[0x15]	97706	1			T26	4		T30	1		T34	1
valid_sources[0x16]	116503	1			T31	1		T1	2		T11	1
valid_sources[0x17]	110418	1			T31	2		T11	2		T15	13
valid_sources[0x18]	90740	1			T34	2		T1	1		T11	1
valid_sources[0x19]	97463	1			T26	8		T31	2		T34	1
valid_sources[0x1a]	101917	1			T31	4		T34	4		T11	2
valid_sources[0x1b]	92952	1			T31	2		T33	6		T34	1
valid_sources[0x1c]	91304	1			T26	1		T31	2		T34	1
valid_sources[0x1d]	104781	1			T34	2		T11	1		T15	16
valid_sources[0x1e]	95256	1			T31	1		T34	1		T11	4
valid_sources[0x1f]	102143	1			T34	2		T1	2		T11	5
valid_sources[0x20]	92790	1			T31	1		T33	7		T34	1
valid_sources[0x21]	98266	1			T26	6		T33	2		T11	2
valid_sources[0x22]	94378	1			T26	2		T31	2		T34	4
valid_sources[0x23]	104555	1			T26	1		T31	2		T11	2
valid_sources[0x24]	100391	1			T31	2		T34	1		T11	6
valid_sources[0x25]	96806	1			T34	5		T11	4		T15	15
valid_sources[0x26]	99422	1			T31	1		T1	1		T11	2
valid_sources[0x27]	108771	1			T26	4		T31	4		T11	6
valid_sources[0x28]	97640	1			T26	5		T34	1		T1	1
valid_sources[0x29]	117861	1			T26	1		T34	7		T11	2
valid_sources[0x2a]	101981	1			T31	5		T34	1		T1	1
valid_sources[0x2b]	98163	1			T11	6		T15	13		T24	1
valid_sources[0x2c]	99958	1			T26	1		T34	1		T11	4
valid_sources[0x2d]	90828	1			T34	4		T1	1		T11	3
valid_sources[0x2e]	93795	1			T34	4		T11	6		T15	13
valid_sources[0x2f]	96976	1			T34	1		T11	4		T15	24
valid_sources[0x30]	241448	1			T26	1		T33	1		T34	2
valid_sources[0x31]	93482	1			T31	3		T33	6		T34	2
valid_sources[0x32]	91307	1			T31	1		T34	1		T1	1
valid_sources[0x33]	105586	1			T30	1		T31	1		T34	1
valid_sources[0x34]	94381	1			T26	7		T31	2		T34	1
valid_sources[0x35]	94885	1			T1	1		T11	4		T15	9
valid_sources[0x36]	98561	1			T31	3		T34	1		T1	1
valid_sources[0x37]	90201	1			T28	5		T30	2		T31	2
valid_sources[0x38]	99073	1			T34	1		T1	2		T11	4
valid_sources[0x39]	93296	1			T31	2		T34	3		T1	1
valid_sources[0x3a]	91886	1			T26	2		T33	1		T34	2
valid_sources[0x3b]	90808	1			T31	1		T34	2		T11	3
valid_sources[0x3c]	95468	1			T28	3		T31	1		T34	3
valid_sources[0x3d]	91907	1			T26	2		T30	1		T31	3
valid_sources[0x3e]	92939	1			T26	1		T30	1		T11	4
valid_sources[0x3f]	98054	1			T1	1		T11	6		T12	2
valid_sources[0x40]	100556	1			T26	1		T31	1		T34	1
valid_sources[0x41]	92756	1			T33	1		T34	3		T1	2
valid_sources[0x42]	94208	1			T34	1		T11	3		T15	17
valid_sources[0x43]	99577	1			T28	1		T34	2		T11	7
valid_sources[0x44]	94594	1			T31	2		T34	8		T35	65
valid_sources[0x45]	104537	1			T33	3		T34	2		T11	4
valid_sources[0x46]	102955	1			T30	1		T34	2		T1	2
valid_sources[0x47]	91873	1			T34	2		T11	6		T13	2
valid_sources[0x48]	102306	1			T31	4		T34	2		T11	4
valid_sources[0x49]	96032	1			T31	3		T34	1		T1	1
valid_sources[0x4a]	95708	1			T31	1		T11	3		T15	12
valid_sources[0x4b]	105957	1			T31	1		T11	5		T14	12
valid_sources[0x4c]	99761	1			T34	1		T1	3		T11	2
valid_sources[0x4d]	102265	1			T26	8		T31	2		T1	1
valid_sources[0x4e]	96381	1			T26	1		T31	2		T1	1
valid_sources[0x4f]	106870	1			T26	3		T34	2		T11	4
valid_sources[0x50]	95807	1			T26	1		T31	4		T34	1
valid_sources[0x51]	98948	1			T1	5		T11	3		T15	16
valid_sources[0x52]	100473	1			T1	1		T11	3		T15	13
valid_sources[0x53]	96767	1			T26	1		T11	3		T15	14
valid_sources[0x54]	96163	1			T31	2		T11	3		T15	14
valid_sources[0x55]	107724	1			T31	1		T33	8		T34	1
valid_sources[0x56]	98814	1			T26	2		T31	1		T1	1
valid_sources[0x57]	100314	1			T34	1		T11	5		T15	24
valid_sources[0x58]	100488	1			T26	4		T33	2		T34	3
valid_sources[0x59]	106037	1			T1	1		T11	4		T15	17
valid_sources[0x5a]	99098	1			T34	1		T1	1		T11	1
valid_sources[0x5b]	102150	1			T31	1		T34	1		T35	137
valid_sources[0x5c]	98383	1			T31	1		T33	6		T34	1
valid_sources[0x5d]	101143	1			T26	6		T29	15		T1	1
valid_sources[0x5e]	96922	1			T34	2		T11	2		T15	21
valid_sources[0x5f]	100490	1			T26	1		T31	1		T34	2
valid_sources[0x60]	96350	1			T26	1		T34	2		T1	1
valid_sources[0x61]	98981	1			T31	1		T34	1		T1	1
valid_sources[0x62]	104753	1			T26	1		T29	1		T31	2
valid_sources[0x63]	98782	1			T26	1		T33	2		T34	2
valid_sources[0x64]	101804	1			T34	2		T12	1		T15	19
valid_sources[0x65]	90534	1			T31	2		T11	3		T15	10
valid_sources[0x66]	97565	1			T26	1		T34	1		T11	3
valid_sources[0x67]	102502	1			T26	1		T31	1		T34	1
valid_sources[0x68]	196923	1			T31	1		T11	1		T14	16
valid_sources[0x69]	99775	1			T26	2		T34	1		T11	5
valid_sources[0x6a]	100049	1			T26	2		T31	1		T34	2
valid_sources[0x6b]	90877	1			T26	2		T31	2		T34	2
valid_sources[0x6c]	97812	1			T34	2		T11	7		T13	1
valid_sources[0x6d]	93246	1			T26	1		T11	3		T15	9
valid_sources[0x6e]	104093	1			T28	2		T34	1		T1	1
valid_sources[0x6f]	98392	1			T26	2		T1	1		T15	15
valid_sources[0x70]	91238	1			T34	2		T11	2		T15	10
valid_sources[0x71]	89388	1			T34	4		T1	1		T2	1
valid_sources[0x72]	91168	1			T31	1		T34	1		T1	1
valid_sources[0x73]	91769	1			T26	1		T28	4		T34	2
valid_sources[0x74]	105748	1			T31	3		T34	2		T1	2
valid_sources[0x75]	102239	1			T28	1		T29	5		T34	4
valid_sources[0x76]	99113	1			T26	3		T1	2		T11	1
valid_sources[0x77]	106136	1			T26	3		T1	1		T11	2
valid_sources[0x78]	99397	1			T26	2		T34	1		T11	1
valid_sources[0x79]	96906	1			T31	2		T11	2		T14	7
valid_sources[0x7a]	98698	1			T11	5		T15	14		T19	1
valid_sources[0x7b]	92781	1			T31	2		T34	2		T11	4
valid_sources[0x7c]	92938	1			T31	2		T34	1		T2	1
valid_sources[0x7d]	95546	1			T26	1		T31	5		T34	3
valid_sources[0x7e]	93373	1			T26	2		T34	4		T11	1
valid_sources[0x7f]	94819	1			T33	11		T34	2		T1	1
valid_sources[0x80]	89980	1			T34	3		T1	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5911442

1

T25

11

T26

103

T27

5

values[0x0]

all_enables

biggest_size

7770776

1

T25

9

T26

61

T27

6

values[0x1]

all_enables

biggest_size

7772317

1

T25

20

T26

52

T27

5