Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	274054189	0	0	0
ctrl_en_input_filter_rd_A	274054189	380779	0	0
intr_ctrl_en_falling_rd_A	274054189	407649	0	0
intr_ctrl_en_lvlhigh_rd_A	274054189	380460	0	0
intr_ctrl_en_lvllow_rd_A	274054189	405337	0	0
intr_ctrl_en_rising_rd_A	274054189	382562	0	0
intr_enable_rd_A	274054189	380915	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	380779	0	0
T1	4418	14	0	0
T2	1054	8	0	0
T3	1655	6	0	0
T4	0	15	0	0
T5	0	36	0	0
T6	0	64	0	0
T7	0	19	0	0
T8	0	68	0	0
T9	0	41	0	0
T10	0	42	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T17	1579	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	407649	0	0
T1	4418	6	0	0
T2	1054	4	0	0
T3	1655	6	0	0
T4	0	14	0	0
T5	0	36	0	0
T6	0	77	0	0
T7	0	2	0	0
T8	0	50	0	0
T9	0	39	0	0
T10	0	18	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T17	1579	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	380460	0	0
T2	1054	4	0	0
T3	1655	8	0	0
T4	0	10	0	0
T5	0	48	0	0
T6	0	74	0	0
T7	0	18	0	0
T8	0	85	0	0
T9	0	32	0	0
T10	0	21	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T17	1579	0	0	0
T18	0	36	0	0
T19	1509	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	405337	0	0
T1	4418	13	0	0
T2	1054	3	0	0
T3	1655	3	0	0
T4	0	15	0	0
T5	0	18	0	0
T6	0	72	0	0
T8	0	60	0	0
T9	0	20	0	0
T10	0	4	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T17	1579	0	0	0
T20	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	382562	0	0
T2	1054	9	0	0
T3	1655	3	0	0
T4	0	5	0	0
T5	0	48	0	0
T6	0	93	0	0
T7	0	5	0	0
T8	0	69	0	0
T9	0	38	0	0
T10	0	37	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T17	1579	0	0	0
T19	1509	0	0	0
T20	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274054189	380915	0	0
T1	4418	14	0	0
T2	1054	4	0	0
T4	1506	6	0	0
T5	0	34	0	0
T6	0	91	0	0
T7	0	5	0	0
T8	0	40	0	0
T11	3466	0	0	0
T12	937	0	0	0
T13	1040	0	0	0
T14	1533	0	0	0
T15	24813	0	0	0
T16	1140	0	0	0
T21	0	13	0	0
T22	0	29	0	0
T23	0	15	0	0
T24	4375	0	0	0