Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	23012834	1			T1	1		T11	5		T12	5
all_values[1]	23012834	1			T1	1		T11	5		T12	5
all_values[2]	23012834	1			T1	1		T11	5		T12	5
all_values[3]	23012834	1			T1	1		T11	5		T12	5
all_values[4]	23012834	1			T1	1		T11	5		T12	5
all_values[5]	23012834	1			T1	1		T11	5		T12	5
all_values[6]	23012834	1			T1	1		T11	5		T12	5
all_values[7]	23012834	1			T1	1		T11	5		T12	5
all_values[8]	23012834	1			T1	1		T11	5		T12	5
all_values[9]	23012834	1			T1	1		T11	5		T12	5
all_values[10]	23012834	1			T1	1		T11	5		T12	5
all_values[11]	23012834	1			T1	1		T11	5		T12	5
all_values[12]	23012834	1			T1	1		T11	5		T12	5
all_values[13]	23012834	1			T1	1		T11	5		T12	5
all_values[14]	23012834	1			T1	1		T11	5		T12	5
all_values[15]	23012834	1			T1	1		T11	5		T12	5
all_values[16]	23012834	1			T1	1		T11	5		T12	5
all_values[17]	23012834	1			T1	1		T11	5		T12	5
all_values[18]	23012834	1			T1	1		T11	5		T12	5
all_values[19]	23012834	1			T1	1		T11	5		T12	5
all_values[20]	23012834	1			T1	1		T11	5		T12	5
all_values[21]	23012834	1			T1	1		T11	5		T12	5
all_values[22]	23012834	1			T1	1		T11	5		T12	5
all_values[23]	23012834	1			T1	1		T11	5		T12	5
all_values[24]	23012834	1			T1	1		T11	5		T12	5
all_values[25]	23012834	1			T1	1		T11	5		T12	5
all_values[26]	23012834	1			T1	1		T11	5		T12	5
all_values[27]	23012834	1			T1	1		T11	5		T12	5
all_values[28]	23012834	1			T1	1		T11	5		T12	5
all_values[29]	23012834	1			T1	1		T11	5		T12	5
all_values[30]	23012834	1			T1	1		T11	5		T12	5
all_values[31]	23012834	1			T1	1		T11	5		T12	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405808874

1

T1

32

T11

160

T12

112

auto[1]

330601814

1

T12

48

T13

542

T15

125

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136938823

1

T1

32

T11

140

T12

98

auto[1]

599471865

1

T11

20

T12

62

T13

521

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3308169	1			T1	1		T11	4		T12	1
all_values[0]	auto[0]	auto[1]	9369956	1			T11	1		T12	4		T15	2
all_values[0]	auto[1]	auto[0]	976622	1			T13	26		T15	3		T3	4
all_values[0]	auto[1]	auto[1]	9358087	1			T13	4		T2	4		T3	1
all_values[1]	auto[0]	auto[0]	3304639	1			T1	1		T11	4		T12	1
all_values[1]	auto[0]	auto[1]	9388249	1			T11	1		T12	4		T13	30
all_values[1]	auto[1]	auto[0]	967198	1			T15	2		T3	4		T17	4
all_values[1]	auto[1]	auto[1]	9352748	1			T15	3		T3	3		T17	9
all_values[2]	auto[0]	auto[0]	3307410	1			T1	1		T11	4		T12	1
all_values[2]	auto[0]	auto[1]	9357803	1			T11	1		T13	4		T15	4
all_values[2]	auto[1]	auto[0]	968067	1			T13	16		T15	2		T3	4
all_values[2]	auto[1]	auto[1]	9379554	1			T12	4		T13	10		T2	2
all_values[3]	auto[0]	auto[0]	3309884	1			T1	1		T11	4		T12	1
all_values[3]	auto[0]	auto[1]	9356803	1			T11	1		T12	4		T13	15
all_values[3]	auto[1]	auto[0]	988547	1			T13	15		T15	6		T3	4
all_values[3]	auto[1]	auto[1]	9357600	1			T15	2		T3	1		T17	4
all_values[4]	auto[0]	auto[0]	3304763	1			T1	1		T11	4		T12	5
all_values[4]	auto[0]	auto[1]	9373733	1			T11	1		T13	4		T2	1
all_values[4]	auto[1]	auto[0]	977192	1			T13	11		T15	2		T3	2
all_values[4]	auto[1]	auto[1]	9357146	1			T2	4		T3	1		T17	11
all_values[5]	auto[0]	auto[0]	3315014	1			T1	1		T11	4		T12	2
all_values[5]	auto[0]	auto[1]	9353641	1			T11	1		T12	3		T15	5
all_values[5]	auto[1]	auto[0]	969511	1			T13	30		T15	5		T3	4
all_values[5]	auto[1]	auto[1]	9374668	1			T2	4		T3	1		T17	6
all_values[6]	auto[0]	auto[0]	3316454	1			T1	1		T11	5		T12	1
all_values[6]	auto[0]	auto[1]	9395534	1			T12	4		T13	4		T15	2
all_values[6]	auto[1]	auto[0]	978384	1			T3	2		T17	13		T20	1
all_values[6]	auto[1]	auto[1]	9322462	1			T15	3		T2	4		T3	2
all_values[7]	auto[0]	auto[0]	3320811	1			T1	1		T11	5		T12	5
all_values[7]	auto[0]	auto[1]	9341179	1			T13	15		T15	2		T2	4
all_values[7]	auto[1]	auto[0]	958651	1			T15	5		T3	1		T17	6
all_values[7]	auto[1]	auto[1]	9392193	1			T13	15		T3	2		T17	4
all_values[8]	auto[0]	auto[0]	3311893	1			T1	1		T11	4		T12	1
all_values[8]	auto[0]	auto[1]	9369204	1			T11	1		T13	17		T15	9
all_values[8]	auto[1]	auto[0]	972843	1			T3	3		T17	3		T20	3
all_values[8]	auto[1]	auto[1]	9358894	1			T12	4		T13	11		T2	4
all_values[9]	auto[0]	auto[0]	3321137	1			T1	1		T11	4		T12	2
all_values[9]	auto[0]	auto[1]	9352564	1			T11	1		T12	3		T15	2
all_values[9]	auto[1]	auto[0]	968952	1			T13	16		T15	4		T2	1
all_values[9]	auto[1]	auto[1]	9370181	1			T13	14		T15	4		T2	3
all_values[10]	auto[0]	auto[0]	3304463	1			T1	1		T11	5		T12	1
all_values[10]	auto[0]	auto[1]	9422829	1			T13	14		T15	2		T2	1
all_values[10]	auto[1]	auto[0]	978672	1			T13	11		T15	4		T3	2
all_values[10]	auto[1]	auto[1]	9306870	1			T12	4		T15	4		T2	2
all_values[11]	auto[0]	auto[0]	3321659	1			T1	1		T11	5		T12	2
all_values[11]	auto[0]	auto[1]	9341886	1			T12	3		T13	4		T15	4
all_values[11]	auto[1]	auto[0]	963430	1			T13	10		T3	2		T17	2
all_values[11]	auto[1]	auto[1]	9385859	1			T13	1		T2	2		T3	1
all_values[12]	auto[0]	auto[0]	3307834	1			T1	1		T11	5		T12	1
all_values[12]	auto[0]	auto[1]	9376315	1			T13	4		T15	2		T3	6
all_values[12]	auto[1]	auto[0]	977866	1			T12	4		T13	5		T15	3
all_values[12]	auto[1]	auto[1]	9350819	1			T13	21		T15	2		T2	4
all_values[13]	auto[0]	auto[0]	3301896	1			T1	1		T11	4		T12	1
all_values[13]	auto[0]	auto[1]	9347833	1			T11	1		T2	2		T3	4
all_values[13]	auto[1]	auto[0]	971387	1			T12	4		T13	2		T15	8
all_values[13]	auto[1]	auto[1]	9391718	1			T13	28		T15	2		T2	2
all_values[14]	auto[0]	auto[0]	3311773	1			T1	1		T11	5		T12	5
all_values[14]	auto[0]	auto[1]	9384816	1			T2	2		T3	3		T17	1
all_values[14]	auto[1]	auto[0]	964115	1			T13	2		T15	3		T3	3
all_values[14]	auto[1]	auto[1]	9352130	1			T13	28		T2	2		T3	1
all_values[15]	auto[0]	auto[0]	3309565	1			T1	1		T11	3		T12	1
all_values[15]	auto[0]	auto[1]	9354898	1			T11	2		T2	3		T3	4
all_values[15]	auto[1]	auto[0]	977070	1			T12	4		T13	15		T15	5
all_values[15]	auto[1]	auto[1]	9371301	1			T13	15		T2	2		T3	2
all_values[16]	auto[0]	auto[0]	3301127	1			T1	1		T11	4		T12	5
all_values[16]	auto[0]	auto[1]	9418268	1			T11	1		T2	3		T3	4
all_values[16]	auto[1]	auto[0]	968244	1			T13	15		T15	5		T3	5
all_values[16]	auto[1]	auto[1]	9325195	1			T13	15		T2	2		T3	2
all_values[17]	auto[0]	auto[0]	3301848	1			T1	1		T11	4		T12	5
all_values[17]	auto[0]	auto[1]	9379225	1			T11	1		T13	15		T15	3
all_values[17]	auto[1]	auto[0]	980708	1			T13	15		T15	6		T3	2
all_values[17]	auto[1]	auto[1]	9351053	1			T15	1		T3	2		T17	4
all_values[18]	auto[0]	auto[0]	3293269	1			T1	1		T11	3		T12	1
all_values[18]	auto[0]	auto[1]	9367825	1			T11	2		T13	10		T15	3
all_values[18]	auto[1]	auto[0]	972420	1			T12	4		T13	15		T15	1
all_values[18]	auto[1]	auto[1]	9379320	1			T13	4		T15	1		T2	4
all_values[19]	auto[0]	auto[0]	3305567	1			T1	1		T11	5		T12	1
all_values[19]	auto[0]	auto[1]	9390162	1			T12	4		T13	4		T15	3
all_values[19]	auto[1]	auto[0]	963224	1			T13	16		T15	1		T2	1
all_values[19]	auto[1]	auto[1]	9353881	1			T13	10		T15	1		T2	3
all_values[20]	auto[0]	auto[0]	3317455	1			T1	1		T11	4		T12	1
all_values[20]	auto[0]	auto[1]	9325810	1			T11	1		T15	5		T2	2
all_values[20]	auto[1]	auto[0]	964840	1			T13	11		T15	1		T3	2
all_values[20]	auto[1]	auto[1]	9404729	1			T12	4		T15	4		T2	2
all_values[21]	auto[0]	auto[0]	3305957	1			T1	1		T11	5		T12	5
all_values[21]	auto[0]	auto[1]	9368650	1			T13	11		T15	2		T2	5
all_values[21]	auto[1]	auto[0]	966959	1			T3	3		T17	6		T20	1
all_values[21]	auto[1]	auto[1]	9371268	1			T13	11		T3	1		T17	2
all_values[22]	auto[0]	auto[0]	3315070	1			T1	1		T11	4		T12	5
all_values[22]	auto[0]	auto[1]	9368154	1			T11	1		T13	4		T3	6
all_values[22]	auto[1]	auto[0]	964774	1			T15	8		T17	6		T20	9
all_values[22]	auto[1]	auto[1]	9364836	1			T13	11		T2	4		T17	5
all_values[23]	auto[0]	auto[0]	3318154	1			T1	1		T11	5		T12	1
all_values[23]	auto[0]	auto[1]	9392702	1			T12	4		T13	26		T15	4
all_values[23]	auto[1]	auto[0]	962073	1			T3	3		T17	5		T20	1
all_values[23]	auto[1]	auto[1]	9339905	1			T13	4		T2	4		T3	2
all_values[24]	auto[0]	auto[0]	3317287	1			T1	1		T11	5		T12	1
all_values[24]	auto[0]	auto[1]	9343851	1			T15	2		T2	2		T3	4
all_values[24]	auto[1]	auto[0]	969730	1			T12	4		T13	11		T2	1
all_values[24]	auto[1]	auto[1]	9381966	1			T13	4		T2	1		T3	2
all_values[25]	auto[0]	auto[0]	3305165	1			T1	1		T11	5		T12	1
all_values[25]	auto[0]	auto[1]	9356205	1			T12	4		T15	6		T2	3
all_values[25]	auto[1]	auto[0]	975415	1			T13	11		T15	4		T3	1
all_values[25]	auto[1]	auto[1]	9376049	1			T15	1		T2	2		T3	3
all_values[26]	auto[0]	auto[0]	3313960	1			T1	1		T11	4		T12	1
all_values[26]	auto[0]	auto[1]	9372033	1			T11	1		T15	3		T2	5
all_values[26]	auto[1]	auto[0]	957240	1			T12	2		T13	7		T15	2
all_values[26]	auto[1]	auto[1]	9369601	1			T12	2		T13	8		T15	3
all_values[27]	auto[0]	auto[0]	3317219	1			T1	1		T11	5		T12	5
all_values[27]	auto[0]	auto[1]	9400877	1			T13	15		T3	4		T17	2
all_values[27]	auto[1]	auto[0]	957027	1			T13	1		T17	8		T20	6
all_values[27]	auto[1]	auto[1]	9337711	1			T13	14		T2	2		T3	3
all_values[28]	auto[0]	auto[0]	3310785	1			T1	1		T11	5		T12	5
all_values[28]	auto[0]	auto[1]	9348253	1			T13	15		T15	2		T3	5
all_values[28]	auto[1]	auto[0]	969784	1			T13	7		T15	2		T2	2
all_values[28]	auto[1]	auto[1]	9384012	1			T13	8		T2	2		T3	2
all_values[29]	auto[0]	auto[0]	3301235	1			T1	1		T11	5		T12	1
all_values[29]	auto[0]	auto[1]	9413666	1			T15	7		T3	3		T17	2
all_values[29]	auto[1]	auto[0]	970880	1			T12	4		T13	4		T3	5
all_values[29]	auto[1]	auto[1]	9327053	1			T13	15		T15	3		T3	3
all_values[30]	auto[0]	auto[0]	3307002	1			T1	1		T11	4		T12	1
all_values[30]	auto[0]	auto[1]	9424665	1			T11	1		T12	4		T13	26
all_values[30]	auto[1]	auto[0]	956811	1			T15	2		T3	2		T17	6
all_values[30]	auto[1]	auto[1]	9324356	1			T13	4		T3	2		T17	2
all_values[31]	auto[0]	auto[0]	3306731	1			T1	1		T11	4		T12	1
all_values[31]	auto[0]	auto[1]	9336090	1			T11	1		T13	15		T15	1
all_values[31]	auto[1]	auto[0]	964992	1			T12	1		T13	1		T15	4
all_values[31]	auto[1]	auto[1]	9405021	1			T12	3		T13	14		T15	3