Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350060 |
1 |
|
|
T35 |
819 |
|
T52 |
3315 |
|
T53 |
3 |
auto[1] |
349418 |
1 |
|
|
T35 |
801 |
|
T52 |
3425 |
|
T100 |
8 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349968 |
1 |
|
|
T35 |
816 |
|
T52 |
3451 |
|
T100 |
9 |
auto[1] |
349510 |
1 |
|
|
T35 |
804 |
|
T52 |
3289 |
|
T53 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175380 |
1 |
|
|
T35 |
417 |
|
T52 |
1688 |
|
T100 |
5 |
auto[0] |
auto[1] |
174680 |
1 |
|
|
T35 |
402 |
|
T52 |
1627 |
|
T53 |
3 |
auto[1] |
auto[0] |
174588 |
1 |
|
|
T35 |
399 |
|
T52 |
1763 |
|
T100 |
4 |
auto[1] |
auto[1] |
174830 |
1 |
|
|
T35 |
402 |
|
T52 |
1662 |
|
T100 |
4 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349511 |
1 |
|
|
T35 |
801 |
|
T52 |
3392 |
|
T53 |
2 |
auto[1] |
349967 |
1 |
|
|
T35 |
819 |
|
T52 |
3348 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349461 |
1 |
|
|
T35 |
817 |
|
T52 |
3389 |
|
T100 |
4 |
auto[1] |
350017 |
1 |
|
|
T35 |
803 |
|
T52 |
3351 |
|
T53 |
3 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174651 |
1 |
|
|
T35 |
411 |
|
T52 |
1695 |
|
T100 |
2 |
auto[0] |
auto[1] |
174860 |
1 |
|
|
T35 |
390 |
|
T52 |
1697 |
|
T53 |
2 |
auto[1] |
auto[0] |
174810 |
1 |
|
|
T35 |
406 |
|
T52 |
1694 |
|
T100 |
2 |
auto[1] |
auto[1] |
175157 |
1 |
|
|
T35 |
413 |
|
T52 |
1654 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349137 |
1 |
|
|
T35 |
796 |
|
T52 |
3390 |
|
T53 |
1 |
auto[1] |
350341 |
1 |
|
|
T35 |
824 |
|
T52 |
3350 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349663 |
1 |
|
|
T35 |
745 |
|
T52 |
3415 |
|
T53 |
1 |
auto[1] |
349815 |
1 |
|
|
T35 |
875 |
|
T52 |
3325 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174003 |
1 |
|
|
T35 |
375 |
|
T52 |
1667 |
|
T100 |
3 |
auto[0] |
auto[1] |
175134 |
1 |
|
|
T35 |
421 |
|
T52 |
1723 |
|
T53 |
1 |
auto[1] |
auto[0] |
175660 |
1 |
|
|
T35 |
370 |
|
T52 |
1748 |
|
T53 |
1 |
auto[1] |
auto[1] |
174681 |
1 |
|
|
T35 |
454 |
|
T52 |
1602 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350248 |
1 |
|
|
T35 |
821 |
|
T52 |
3368 |
|
T53 |
1 |
auto[1] |
349230 |
1 |
|
|
T35 |
799 |
|
T52 |
3372 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349797 |
1 |
|
|
T35 |
789 |
|
T52 |
3373 |
|
T53 |
3 |
auto[1] |
349681 |
1 |
|
|
T35 |
831 |
|
T52 |
3367 |
|
T100 |
12 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175243 |
1 |
|
|
T35 |
400 |
|
T52 |
1705 |
|
T53 |
1 |
auto[0] |
auto[1] |
175005 |
1 |
|
|
T35 |
421 |
|
T52 |
1663 |
|
T100 |
4 |
auto[1] |
auto[0] |
174554 |
1 |
|
|
T35 |
389 |
|
T52 |
1668 |
|
T53 |
2 |
auto[1] |
auto[1] |
174676 |
1 |
|
|
T35 |
410 |
|
T52 |
1704 |
|
T100 |
8 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349623 |
1 |
|
|
T35 |
811 |
|
T52 |
3375 |
|
T53 |
1 |
auto[1] |
349855 |
1 |
|
|
T35 |
809 |
|
T52 |
3365 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349976 |
1 |
|
|
T35 |
809 |
|
T52 |
3345 |
|
T53 |
2 |
auto[1] |
349502 |
1 |
|
|
T35 |
811 |
|
T52 |
3395 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174987 |
1 |
|
|
T35 |
414 |
|
T52 |
1706 |
|
T100 |
8 |
auto[0] |
auto[1] |
174636 |
1 |
|
|
T35 |
397 |
|
T52 |
1669 |
|
T53 |
1 |
auto[1] |
auto[0] |
174989 |
1 |
|
|
T35 |
395 |
|
T52 |
1639 |
|
T53 |
2 |
auto[1] |
auto[1] |
174866 |
1 |
|
|
T35 |
414 |
|
T52 |
1726 |
|
T100 |
6 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349989 |
1 |
|
|
T35 |
793 |
|
T52 |
3446 |
|
T53 |
2 |
auto[1] |
349489 |
1 |
|
|
T35 |
827 |
|
T52 |
3294 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349959 |
1 |
|
|
T35 |
821 |
|
T52 |
3354 |
|
T53 |
2 |
auto[1] |
349519 |
1 |
|
|
T35 |
799 |
|
T52 |
3386 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174984 |
1 |
|
|
T35 |
391 |
|
T52 |
1735 |
|
T53 |
1 |
auto[0] |
auto[1] |
175005 |
1 |
|
|
T35 |
402 |
|
T52 |
1711 |
|
T53 |
1 |
auto[1] |
auto[0] |
174975 |
1 |
|
|
T35 |
430 |
|
T52 |
1619 |
|
T53 |
1 |
auto[1] |
auto[1] |
174514 |
1 |
|
|
T35 |
397 |
|
T52 |
1675 |
|
T100 |
9 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350187 |
1 |
|
|
T35 |
816 |
|
T52 |
3435 |
|
T53 |
1 |
auto[1] |
349291 |
1 |
|
|
T35 |
804 |
|
T52 |
3305 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349988 |
1 |
|
|
T35 |
803 |
|
T52 |
3359 |
|
T53 |
2 |
auto[1] |
349490 |
1 |
|
|
T35 |
817 |
|
T52 |
3381 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175132 |
1 |
|
|
T35 |
394 |
|
T52 |
1701 |
|
T53 |
1 |
auto[0] |
auto[1] |
175055 |
1 |
|
|
T35 |
422 |
|
T52 |
1734 |
|
T100 |
7 |
auto[1] |
auto[0] |
174856 |
1 |
|
|
T35 |
409 |
|
T52 |
1658 |
|
T53 |
1 |
auto[1] |
auto[1] |
174435 |
1 |
|
|
T35 |
395 |
|
T52 |
1647 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349830 |
1 |
|
|
T35 |
814 |
|
T52 |
3270 |
|
T53 |
1 |
auto[1] |
349450 |
1 |
|
|
T35 |
883 |
|
T52 |
3368 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349661 |
1 |
|
|
T35 |
833 |
|
T52 |
3344 |
|
T53 |
1 |
auto[1] |
349619 |
1 |
|
|
T35 |
864 |
|
T52 |
3294 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
175127 |
1 |
|
|
T35 |
403 |
|
T52 |
1679 |
|
T53 |
1 |
auto[0] |
auto[1] |
174703 |
1 |
|
|
T35 |
411 |
|
T52 |
1591 |
|
T100 |
4 |
auto[1] |
auto[0] |
174534 |
1 |
|
|
T35 |
430 |
|
T52 |
1665 |
|
T100 |
4 |
auto[1] |
auto[1] |
174916 |
1 |
|
|
T35 |
453 |
|
T52 |
1703 |
|
T53 |
2 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349683 |
1 |
|
|
T35 |
848 |
|
T52 |
3331 |
|
T53 |
2 |
auto[1] |
349597 |
1 |
|
|
T35 |
849 |
|
T52 |
3307 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349375 |
1 |
|
|
T35 |
824 |
|
T52 |
3264 |
|
T53 |
3 |
auto[1] |
349905 |
1 |
|
|
T35 |
873 |
|
T52 |
3374 |
|
T100 |
9 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174827 |
1 |
|
|
T35 |
422 |
|
T52 |
1619 |
|
T53 |
2 |
auto[0] |
auto[1] |
174856 |
1 |
|
|
T35 |
426 |
|
T52 |
1712 |
|
T100 |
5 |
auto[1] |
auto[0] |
174548 |
1 |
|
|
T35 |
402 |
|
T52 |
1645 |
|
T53 |
1 |
auto[1] |
auto[1] |
175049 |
1 |
|
|
T35 |
447 |
|
T52 |
1662 |
|
T100 |
4 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349719 |
1 |
|
|
T35 |
859 |
|
T52 |
3312 |
|
T53 |
2 |
auto[1] |
349561 |
1 |
|
|
T35 |
838 |
|
T52 |
3326 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349085 |
1 |
|
|
T35 |
850 |
|
T52 |
3362 |
|
T53 |
3 |
auto[1] |
350195 |
1 |
|
|
T35 |
847 |
|
T52 |
3276 |
|
T100 |
6 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174333 |
1 |
|
|
T35 |
418 |
|
T52 |
1680 |
|
T53 |
2 |
auto[0] |
auto[1] |
175386 |
1 |
|
|
T35 |
441 |
|
T52 |
1632 |
|
T100 |
3 |
auto[1] |
auto[0] |
174752 |
1 |
|
|
T35 |
432 |
|
T52 |
1682 |
|
T53 |
1 |
auto[1] |
auto[1] |
174809 |
1 |
|
|
T35 |
406 |
|
T52 |
1644 |
|
T100 |
3 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349251 |
1 |
|
|
T35 |
896 |
|
T52 |
3255 |
|
T53 |
2 |
auto[1] |
350029 |
1 |
|
|
T35 |
801 |
|
T52 |
3383 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349509 |
1 |
|
|
T35 |
852 |
|
T52 |
3337 |
|
T53 |
1 |
auto[1] |
349771 |
1 |
|
|
T35 |
845 |
|
T52 |
3301 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174409 |
1 |
|
|
T35 |
451 |
|
T52 |
1610 |
|
T100 |
3 |
auto[0] |
auto[1] |
174842 |
1 |
|
|
T35 |
445 |
|
T52 |
1645 |
|
T53 |
2 |
auto[1] |
auto[0] |
175100 |
1 |
|
|
T35 |
401 |
|
T52 |
1727 |
|
T53 |
1 |
auto[1] |
auto[1] |
174929 |
1 |
|
|
T35 |
400 |
|
T52 |
1656 |
|
T100 |
4 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349663 |
1 |
|
|
T35 |
827 |
|
T52 |
3306 |
|
T100 |
5 |
auto[1] |
349617 |
1 |
|
|
T35 |
870 |
|
T52 |
3332 |
|
T53 |
3 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349409 |
1 |
|
|
T35 |
862 |
|
T52 |
3268 |
|
T53 |
2 |
auto[1] |
349871 |
1 |
|
|
T35 |
835 |
|
T52 |
3370 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174905 |
1 |
|
|
T35 |
421 |
|
T52 |
1600 |
|
T100 |
4 |
auto[0] |
auto[1] |
174758 |
1 |
|
|
T35 |
406 |
|
T52 |
1706 |
|
T100 |
1 |
auto[1] |
auto[0] |
174504 |
1 |
|
|
T35 |
441 |
|
T52 |
1668 |
|
T53 |
2 |
auto[1] |
auto[1] |
175113 |
1 |
|
|
T35 |
429 |
|
T52 |
1664 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349999 |
1 |
|
|
T35 |
848 |
|
T52 |
3384 |
|
T53 |
2 |
auto[1] |
349281 |
1 |
|
|
T35 |
849 |
|
T52 |
3254 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348815 |
1 |
|
|
T35 |
845 |
|
T52 |
3270 |
|
T53 |
1 |
auto[1] |
350465 |
1 |
|
|
T35 |
852 |
|
T52 |
3368 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174817 |
1 |
|
|
T35 |
413 |
|
T52 |
1655 |
|
T100 |
2 |
auto[0] |
auto[1] |
175182 |
1 |
|
|
T35 |
435 |
|
T52 |
1729 |
|
T53 |
2 |
auto[1] |
auto[0] |
173998 |
1 |
|
|
T35 |
432 |
|
T52 |
1615 |
|
T53 |
1 |
auto[1] |
auto[1] |
175283 |
1 |
|
|
T35 |
417 |
|
T52 |
1639 |
|
T100 |
6 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349227 |
1 |
|
|
T35 |
855 |
|
T52 |
3295 |
|
T53 |
2 |
auto[1] |
350053 |
1 |
|
|
T35 |
842 |
|
T52 |
3343 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349482 |
1 |
|
|
T35 |
871 |
|
T52 |
3381 |
|
T53 |
2 |
auto[1] |
349798 |
1 |
|
|
T35 |
826 |
|
T52 |
3257 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174696 |
1 |
|
|
T35 |
441 |
|
T52 |
1671 |
|
T53 |
1 |
auto[0] |
auto[1] |
174531 |
1 |
|
|
T35 |
414 |
|
T52 |
1624 |
|
T53 |
1 |
auto[1] |
auto[0] |
174786 |
1 |
|
|
T35 |
430 |
|
T52 |
1710 |
|
T53 |
1 |
auto[1] |
auto[1] |
175267 |
1 |
|
|
T35 |
412 |
|
T52 |
1633 |
|
T100 |
4 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349451 |
1 |
|
|
T35 |
857 |
|
T52 |
3331 |
|
T53 |
1 |
auto[1] |
349829 |
1 |
|
|
T35 |
840 |
|
T52 |
3307 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349631 |
1 |
|
|
T35 |
806 |
|
T52 |
3337 |
|
T53 |
2 |
auto[1] |
349649 |
1 |
|
|
T35 |
891 |
|
T52 |
3301 |
|
T53 |
1 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174882 |
1 |
|
|
T35 |
413 |
|
T52 |
1694 |
|
T53 |
1 |
auto[0] |
auto[1] |
174569 |
1 |
|
|
T35 |
444 |
|
T52 |
1637 |
|
T100 |
6 |
auto[1] |
auto[0] |
174749 |
1 |
|
|
T35 |
393 |
|
T52 |
1643 |
|
T53 |
1 |
auto[1] |
auto[1] |
175080 |
1 |
|
|
T35 |
447 |
|
T52 |
1664 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349723 |
1 |
|
|
T35 |
832 |
|
T52 |
3265 |
|
T53 |
1 |
auto[1] |
349557 |
1 |
|
|
T35 |
865 |
|
T52 |
3373 |
|
T53 |
2 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349665 |
1 |
|
|
T35 |
801 |
|
T52 |
3368 |
|
T53 |
1 |
auto[1] |
349615 |
1 |
|
|
T35 |
896 |
|
T52 |
3270 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174968 |
1 |
|
|
T35 |
394 |
|
T52 |
1612 |
|
T100 |
4 |
auto[0] |
auto[1] |
174755 |
1 |
|
|
T35 |
438 |
|
T52 |
1653 |
|
T53 |
1 |
auto[1] |
auto[0] |
174697 |
1 |
|
|
T35 |
407 |
|
T52 |
1756 |
|
T53 |
1 |
auto[1] |
auto[1] |
174860 |
1 |
|
|
T35 |
458 |
|
T52 |
1617 |
|
T53 |
1 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348665 |
1 |
|
|
T35 |
842 |
|
T52 |
3297 |
|
T53 |
3 |
auto[1] |
350615 |
1 |
|
|
T35 |
855 |
|
T52 |
3341 |
|
T100 |
6 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349775 |
1 |
|
|
T35 |
822 |
|
T52 |
3431 |
|
T53 |
1 |
auto[1] |
349505 |
1 |
|
|
T35 |
875 |
|
T52 |
3207 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174442 |
1 |
|
|
T35 |
393 |
|
T52 |
1712 |
|
T53 |
1 |
auto[0] |
auto[1] |
174223 |
1 |
|
|
T35 |
449 |
|
T52 |
1585 |
|
T53 |
2 |
auto[1] |
auto[0] |
175333 |
1 |
|
|
T35 |
429 |
|
T52 |
1719 |
|
T100 |
2 |
auto[1] |
auto[1] |
175282 |
1 |
|
|
T35 |
426 |
|
T52 |
1622 |
|
T100 |
4 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349655 |
1 |
|
|
T35 |
844 |
|
T52 |
3313 |
|
T53 |
2 |
auto[1] |
349625 |
1 |
|
|
T35 |
853 |
|
T52 |
3325 |
|
T53 |
1 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349600 |
1 |
|
|
T35 |
873 |
|
T52 |
3316 |
|
T53 |
1 |
auto[1] |
349680 |
1 |
|
|
T35 |
824 |
|
T52 |
3322 |
|
T53 |
2 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174985 |
1 |
|
|
T35 |
426 |
|
T52 |
1685 |
|
T100 |
2 |
auto[0] |
auto[1] |
174670 |
1 |
|
|
T35 |
418 |
|
T52 |
1628 |
|
T53 |
2 |
auto[1] |
auto[0] |
174615 |
1 |
|
|
T35 |
447 |
|
T52 |
1631 |
|
T53 |
1 |
auto[1] |
auto[1] |
175010 |
1 |
|
|
T35 |
406 |
|
T52 |
1694 |
|
T100 |
4 |