Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7014400	1			T1	1		T11	6		T12	5
all_pins[1]	7014400	1			T1	1		T11	6		T12	5
all_pins[2]	7014400	1			T1	1		T11	6		T12	5
all_pins[3]	7014400	1			T1	1		T11	6		T12	5
all_pins[4]	7014400	1			T1	1		T11	6		T12	5
all_pins[5]	7014400	1			T1	1		T11	6		T12	5
all_pins[6]	7014400	1			T1	1		T11	6		T12	5
all_pins[7]	7014400	1			T1	1		T11	6		T12	5
all_pins[8]	7014400	1			T1	1		T11	6		T12	5
all_pins[9]	7014400	1			T1	1		T11	6		T12	5
all_pins[10]	7014400	1			T1	1		T11	6		T12	5
all_pins[11]	7014400	1			T1	1		T11	6		T12	5
all_pins[12]	7014400	1			T1	1		T11	6		T12	5
all_pins[13]	7014400	1			T1	1		T11	6		T12	5
all_pins[14]	7014400	1			T1	1		T11	6		T12	5
all_pins[15]	7014400	1			T1	1		T11	6		T12	5
all_pins[16]	7014400	1			T1	1		T11	6		T12	5
all_pins[17]	7014400	1			T1	1		T11	6		T12	5
all_pins[18]	7014400	1			T1	1		T11	6		T12	5
all_pins[19]	7014400	1			T1	1		T11	6		T12	5
all_pins[20]	7014400	1			T1	1		T11	6		T12	5
all_pins[21]	7014400	1			T1	1		T11	6		T12	5
all_pins[22]	7014400	1			T1	1		T11	6		T12	5
all_pins[23]	7014400	1			T1	1		T11	6		T12	5
all_pins[24]	7014400	1			T1	1		T11	6		T12	5
all_pins[25]	7014400	1			T1	1		T11	6		T12	5
all_pins[26]	7014400	1			T1	1		T11	6		T12	5
all_pins[27]	7014400	1			T1	1		T11	6		T12	5
all_pins[28]	7014400	1			T1	1		T11	6		T12	5
all_pins[29]	7014400	1			T1	1		T11	6		T12	5
all_pins[30]	7014400	1			T1	1		T11	6		T12	5
all_pins[31]	7014400	1			T1	1		T11	6		T12	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	139219771	1			T1	32		T11	172		T12	130
values[0x1]	85241029	1			T11	20		T12	30		T13	320
transitions[0x0=>0x1]	51029269	1			T11	16		T12	30		T13	156
transitions[0x1=>0x0]	51029107	1			T11	16		T12	29		T13	156

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4346971	1			T1	1		T11	6		T12	5
all_pins[0]	values[0x1]	2667429	1			T13	11		T2	7		T3	12
all_pins[0]	transitions[0x0=>0x1]	1648435	1			T13	7		T2	4		T3	11
all_pins[0]	transitions[0x1=>0x0]	1649084	1			T12	1		T13	9		T15	2
all_pins[1]	values[0x0]	4347069	1			T1	1		T11	6		T12	5
all_pins[1]	values[0x1]	2667331	1			T13	5		T15	3		T3	11
all_pins[1]	transitions[0x0=>0x1]	1590698	1			T13	3		T15	3		T3	7
all_pins[1]	transitions[0x1=>0x0]	1590796	1			T13	9		T2	7		T3	8
all_pins[2]	values[0x0]	4351311	1			T1	1		T11	5		T12	2
all_pins[2]	values[0x1]	2663089	1			T11	1		T12	3		T13	11
all_pins[2]	transitions[0x0=>0x1]	1589877	1			T11	1		T12	3		T13	9
all_pins[2]	transitions[0x1=>0x0]	1594119	1			T13	3		T15	3		T3	11
all_pins[3]	values[0x0]	4343683	1			T1	1		T11	4		T12	5
all_pins[3]	values[0x1]	2670717	1			T11	2		T13	5		T15	2
all_pins[3]	transitions[0x0=>0x1]	1597167	1			T11	1		T13	2		T15	2
all_pins[3]	transitions[0x1=>0x0]	1589539	1			T12	3		T13	8		T2	1
all_pins[4]	values[0x0]	4348277	1			T1	1		T11	4		T12	5
all_pins[4]	values[0x1]	2666123	1			T11	2		T13	5		T2	7
all_pins[4]	transitions[0x0=>0x1]	1594084	1			T11	1		T13	4		T2	7
all_pins[4]	transitions[0x1=>0x0]	1598678	1			T11	1		T13	4		T15	2
all_pins[5]	values[0x0]	4345219	1			T1	1		T11	5		T12	5
all_pins[5]	values[0x1]	2669181	1			T11	1		T13	13		T2	7
all_pins[5]	transitions[0x0=>0x1]	1597394	1			T11	1		T13	10		T3	4
all_pins[5]	transitions[0x1=>0x0]	1594336	1			T11	2		T13	2		T3	6
all_pins[6]	values[0x0]	4343112	1			T1	1		T11	6		T12	5
all_pins[6]	values[0x1]	2671288	1			T13	4		T15	3		T2	4
all_pins[6]	transitions[0x0=>0x1]	1594513	1			T13	2		T15	3		T3	5
all_pins[6]	transitions[0x1=>0x0]	1592406	1			T11	1		T13	11		T2	3
all_pins[7]	values[0x0]	4346037	1			T1	1		T11	6		T12	5
all_pins[7]	values[0x1]	2668363	1			T13	11		T3	3		T17	4
all_pins[7]	transitions[0x0=>0x1]	1594267	1			T13	9		T3	2		T17	2
all_pins[7]	transitions[0x1=>0x0]	1597192	1			T13	2		T15	3		T2	4
all_pins[8]	values[0x0]	4355111	1			T1	1		T11	5		T12	4
all_pins[8]	values[0x1]	2659289	1			T11	1		T12	1		T13	9
all_pins[8]	transitions[0x0=>0x1]	1589927	1			T11	1		T12	1		T13	8
all_pins[8]	transitions[0x1=>0x0]	1599001	1			T13	10		T3	3		T17	4
all_pins[9]	values[0x0]	4352466	1			T1	1		T11	6		T12	5
all_pins[9]	values[0x1]	2661934	1			T13	13		T15	3		T2	2
all_pins[9]	transitions[0x0=>0x1]	1591850	1			T13	7		T15	3		T3	7
all_pins[9]	transitions[0x1=>0x0]	1589205	1			T11	1		T12	1		T13	3
all_pins[10]	values[0x0]	4351734	1			T1	1		T11	6		T12	1
all_pins[10]	values[0x1]	2662666	1			T12	4		T13	7		T15	3
all_pins[10]	transitions[0x0=>0x1]	1592057	1			T12	4		T13	2		T15	1
all_pins[10]	transitions[0x1=>0x0]	1591325	1			T13	8		T15	1		T2	1
all_pins[11]	values[0x0]	4347926	1			T1	1		T11	6		T12	5
all_pins[11]	values[0x1]	2666474	1			T13	9		T2	3		T3	5
all_pins[11]	transitions[0x0=>0x1]	1595621	1			T13	4		T2	3		T3	5
all_pins[11]	transitions[0x1=>0x0]	1591813	1			T12	4		T13	2		T15	3
all_pins[12]	values[0x0]	4350979	1			T1	1		T11	6		T12	5
all_pins[12]	values[0x1]	2663421	1			T13	12		T15	1		T2	6
all_pins[12]	transitions[0x0=>0x1]	1590239	1			T13	6		T15	1		T2	4
all_pins[12]	transitions[0x1=>0x0]	1593292	1			T13	3		T2	1		T3	3
all_pins[13]	values[0x0]	4345207	1			T1	1		T11	4		T12	5
all_pins[13]	values[0x1]	2669193	1			T11	2		T13	21		T15	2
all_pins[13]	transitions[0x0=>0x1]	1594667	1			T11	2		T13	11		T15	2
all_pins[13]	transitions[0x1=>0x0]	1588895	1			T13	2		T15	1		T2	2
all_pins[14]	values[0x0]	4354009	1			T1	1		T11	6		T12	5
all_pins[14]	values[0x1]	2660391	1			T13	13		T2	1		T3	8
all_pins[14]	transitions[0x0=>0x1]	1588897	1			T13	2		T3	4		T17	8
all_pins[14]	transitions[0x1=>0x0]	1597699	1			T11	2		T13	10		T15	2
all_pins[15]	values[0x0]	4351685	1			T1	1		T11	6		T12	1
all_pins[15]	values[0x1]	2662715	1			T12	4		T13	15		T2	1
all_pins[15]	transitions[0x0=>0x1]	1595694	1			T12	4		T13	6		T3	7
all_pins[15]	transitions[0x1=>0x0]	1593370	1			T13	4		T3	6		T17	9
all_pins[16]	values[0x0]	4358964	1			T1	1		T11	4		T12	5
all_pins[16]	values[0x1]	2655436	1			T11	2		T13	14		T2	1
all_pins[16]	transitions[0x0=>0x1]	1588290	1			T11	2		T13	3		T3	5
all_pins[16]	transitions[0x1=>0x0]	1595569	1			T12	4		T13	4		T3	7
all_pins[17]	values[0x0]	4348707	1			T1	1		T11	4		T12	5
all_pins[17]	values[0x1]	2665693	1			T11	2		T13	5		T15	1
all_pins[17]	transitions[0x0=>0x1]	1598339	1			T11	1		T13	2		T15	1
all_pins[17]	transitions[0x1=>0x0]	1588082	1			T11	1		T13	11		T2	1
all_pins[18]	values[0x0]	4354004	1			T1	1		T11	6		T12	1
all_pins[18]	values[0x1]	2660396	1			T12	4		T13	10		T15	1
all_pins[18]	transitions[0x0=>0x1]	1589515	1			T12	4		T13	6		T2	4
all_pins[18]	transitions[0x1=>0x0]	1594812	1			T11	2		T13	1		T3	9
all_pins[19]	values[0x0]	4348349	1			T1	1		T11	6		T12	5
all_pins[19]	values[0x1]	2666051	1			T13	13		T15	1		T2	3
all_pins[19]	transitions[0x0=>0x1]	1597531	1			T13	6		T2	2		T3	7
all_pins[19]	transitions[0x1=>0x0]	1591876	1			T12	4		T13	3		T2	3
all_pins[20]	values[0x0]	4344920	1			T1	1		T11	5		T12	1
all_pins[20]	values[0x1]	2669480	1			T11	1		T12	4		T13	10
all_pins[20]	transitions[0x0=>0x1]	1594899	1			T11	1		T12	4		T13	3
all_pins[20]	transitions[0x1=>0x0]	1591470	1			T13	6		T15	1		T2	3
all_pins[21]	values[0x0]	4345352	1			T1	1		T11	5		T12	5
all_pins[21]	values[0x1]	2669048	1			T11	1		T13	8		T2	3
all_pins[21]	transitions[0x0=>0x1]	1593160	1			T11	1		T13	2		T2	3
all_pins[21]	transitions[0x1=>0x0]	1593592	1			T11	1		T12	4		T13	4
all_pins[22]	values[0x0]	4355114	1			T1	1		T11	4		T12	5
all_pins[22]	values[0x1]	2659286	1			T11	2		T13	7		T2	7
all_pins[22]	transitions[0x0=>0x1]	1588551	1			T11	1		T13	2		T2	4
all_pins[22]	transitions[0x1=>0x0]	1598313	1			T13	3		T3	3		T17	2
all_pins[23]	values[0x0]	4354628	1			T1	1		T11	6		T12	5
all_pins[23]	values[0x1]	2659772	1			T13	5		T2	5		T3	9
all_pins[23]	transitions[0x0=>0x1]	1594425	1			T13	3		T3	8		T17	7
all_pins[23]	transitions[0x1=>0x0]	1593939	1			T11	2		T13	5		T2	2
all_pins[24]	values[0x0]	4355308	1			T1	1		T11	6		T12	5
all_pins[24]	values[0x1]	2659092	1			T13	10		T2	1		T3	5
all_pins[24]	transitions[0x0=>0x1]	1591314	1			T13	7		T3	5		T17	11
all_pins[24]	transitions[0x1=>0x0]	1591994	1			T13	2		T2	4		T3	9
all_pins[25]	values[0x0]	4356131	1			T1	1		T11	5		T12	5
all_pins[25]	values[0x1]	2658269	1			T11	1		T13	11		T15	1
all_pins[25]	transitions[0x0=>0x1]	1591375	1			T11	1		T13	4		T15	1
all_pins[25]	transitions[0x1=>0x0]	1592198	1			T13	3		T3	3		T17	11
all_pins[26]	values[0x0]	4354153	1			T1	1		T11	6		T12	1
all_pins[26]	values[0x1]	2660247	1			T12	4		T13	11		T15	2
all_pins[26]	transitions[0x0=>0x1]	1593800	1			T12	4		T13	3		T15	1
all_pins[26]	transitions[0x1=>0x0]	1591822	1			T11	1		T13	3		T2	6
all_pins[27]	values[0x0]	4352558	1			T1	1		T11	6		T12	5
all_pins[27]	values[0x1]	2661842	1			T13	10		T2	2		T3	9
all_pins[27]	transitions[0x0=>0x1]	1592030	1			T13	2		T2	2		T3	8
all_pins[27]	transitions[0x1=>0x0]	1590435	1			T12	4		T13	3		T15	2
all_pins[28]	values[0x0]	4352223	1			T1	1		T11	5		T12	5
all_pins[28]	values[0x1]	2662177	1			T11	1		T13	8		T2	1
all_pins[28]	transitions[0x0=>0x1]	1593575	1			T11	1		T3	5		T17	3
all_pins[28]	transitions[0x1=>0x0]	1593240	1			T13	2		T2	1		T3	6
all_pins[29]	values[0x0]	4357282	1			T1	1		T11	6		T12	1
all_pins[29]	values[0x1]	2657118	1			T12	4		T13	12		T15	3
all_pins[29]	transitions[0x0=>0x1]	1588377	1			T12	4		T13	11		T15	3
all_pins[29]	transitions[0x1=>0x0]	1593436	1			T11	1		T13	7		T2	1
all_pins[30]	values[0x0]	4355122	1			T1	1		T11	5		T12	5
all_pins[30]	values[0x1]	2659278	1			T11	1		T13	9		T3	5
all_pins[30]	transitions[0x0=>0x1]	1592968	1			T11	1		T13	3		T3	1
all_pins[30]	transitions[0x1=>0x0]	1590808	1			T12	4		T13	6		T15	3
all_pins[31]	values[0x0]	4346160	1			T1	1		T11	6		T12	3
all_pins[31]	values[0x1]	2668240	1			T12	2		T13	13		T15	2
all_pins[31]	transitions[0x0=>0x1]	1595733	1			T12	2		T13	7		T15	2
all_pins[31]	transitions[0x1=>0x0]	1586771	1			T11	1		T13	3		T3	5