Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	23012834	1			T1	1		T11	5		T12	5
all_values[1]	23012834	1			T1	1		T11	5		T12	5
all_values[2]	23012834	1			T1	1		T11	5		T12	5
all_values[3]	23012834	1			T1	1		T11	5		T12	5
all_values[4]	23012834	1			T1	1		T11	5		T12	5
all_values[5]	23012834	1			T1	1		T11	5		T12	5
all_values[6]	23012834	1			T1	1		T11	5		T12	5
all_values[7]	23012834	1			T1	1		T11	5		T12	5
all_values[8]	23012834	1			T1	1		T11	5		T12	5
all_values[9]	23012834	1			T1	1		T11	5		T12	5
all_values[10]	23012834	1			T1	1		T11	5		T12	5
all_values[11]	23012834	1			T1	1		T11	5		T12	5
all_values[12]	23012834	1			T1	1		T11	5		T12	5
all_values[13]	23012834	1			T1	1		T11	5		T12	5
all_values[14]	23012834	1			T1	1		T11	5		T12	5
all_values[15]	23012834	1			T1	1		T11	5		T12	5
all_values[16]	23012834	1			T1	1		T11	5		T12	5
all_values[17]	23012834	1			T1	1		T11	5		T12	5
all_values[18]	23012834	1			T1	1		T11	5		T12	5
all_values[19]	23012834	1			T1	1		T11	5		T12	5
all_values[20]	23012834	1			T1	1		T11	5		T12	5
all_values[21]	23012834	1			T1	1		T11	5		T12	5
all_values[22]	23012834	1			T1	1		T11	5		T12	5
all_values[23]	23012834	1			T1	1		T11	5		T12	5
all_values[24]	23012834	1			T1	1		T11	5		T12	5
all_values[25]	23012834	1			T1	1		T11	5		T12	5
all_values[26]	23012834	1			T1	1		T11	5		T12	5
all_values[27]	23012834	1			T1	1		T11	5		T12	5
all_values[28]	23012834	1			T1	1		T11	5		T12	5
all_values[29]	23012834	1			T1	1		T11	5		T12	5
all_values[30]	23012834	1			T1	1		T11	5		T12	5
all_values[31]	23012834	1			T1	1		T11	5		T12	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405808874

1

T1

32

T11

160

T12

112

auto[1]

330601814

1

T12

48

T13

542

T15

125

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136938823

1

T1

32

T11

140

T12

98

auto[1]

599471865

1

T11

20

T12

62

T13

521

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

728083630

1

T1

32

T11

160

T12

160

auto[1]

8327058

1

T15

44

T17

137

T20

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3308169	1			T1	1		T11	4		T12	1
all_values[0]	auto[0]	auto[0]	auto[1]	9240198	1			T11	1		T12	4		T15	1
all_values[0]	auto[0]	auto[1]	auto[0]	976622	1			T13	26		T15	3		T3	4
all_values[0]	auto[0]	auto[1]	auto[1]	9227773	1			T13	4		T2	4		T3	1
all_values[0]	auto[1]	auto[0]	auto[1]	129758	1			T15	1		T17	2		T20	2
all_values[0]	auto[1]	auto[1]	auto[1]	130314	1			T17	3		T20	1		T21	1
all_values[1]	auto[0]	auto[0]	auto[0]	3304639	1			T1	1		T11	4		T12	1
all_values[1]	auto[0]	auto[0]	auto[1]	9257830	1			T11	1		T12	4		T13	30
all_values[1]	auto[0]	auto[1]	auto[0]	967198	1			T15	2		T3	4		T17	4
all_values[1]	auto[0]	auto[1]	auto[1]	9223091	1			T15	2		T3	3		T17	9
all_values[1]	auto[1]	auto[0]	auto[1]	130419	1			T17	4		T76	1		T21	4
all_values[1]	auto[1]	auto[1]	auto[1]	129657	1			T15	1		T20	1		T21	2
all_values[2]	auto[0]	auto[0]	auto[0]	3307410	1			T1	1		T11	4		T12	1
all_values[2]	auto[0]	auto[0]	auto[1]	9228081	1			T11	1		T13	4		T15	2
all_values[2]	auto[0]	auto[1]	auto[0]	968067	1			T13	16		T15	2		T3	4
all_values[2]	auto[0]	auto[1]	auto[1]	9249209	1			T12	4		T13	10		T2	2
all_values[2]	auto[1]	auto[0]	auto[1]	129722	1			T15	2		T76	2		T21	1
all_values[2]	auto[1]	auto[1]	auto[1]	130345	1			T17	3		T20	1		T21	4
all_values[3]	auto[0]	auto[0]	auto[0]	3309884	1			T1	1		T11	4		T12	1
all_values[3]	auto[0]	auto[0]	auto[1]	9226721	1			T11	1		T12	4		T13	15
all_values[3]	auto[0]	auto[1]	auto[0]	988547	1			T13	15		T15	6		T3	4
all_values[3]	auto[0]	auto[1]	auto[1]	9227687	1			T15	1		T3	1		T17	3
all_values[3]	auto[1]	auto[0]	auto[1]	130082	1			T15	1		T17	5		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	129913	1			T15	1		T17	1		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	3304763	1			T1	1		T11	4		T12	5
all_values[4]	auto[0]	auto[0]	auto[1]	9243772	1			T11	1		T13	4		T2	1
all_values[4]	auto[0]	auto[1]	auto[0]	977192	1			T13	11		T15	2		T3	2
all_values[4]	auto[0]	auto[1]	auto[1]	9226910	1			T2	4		T3	1		T17	7
all_values[4]	auto[1]	auto[0]	auto[1]	129961	1			T17	4		T21	2		T99	3
all_values[4]	auto[1]	auto[1]	auto[1]	130236	1			T17	4		T20	1		T76	1
all_values[5]	auto[0]	auto[0]	auto[0]	3315014	1			T1	1		T11	4		T12	2
all_values[5]	auto[0]	auto[0]	auto[1]	9224501	1			T11	1		T12	3		T15	4
all_values[5]	auto[0]	auto[1]	auto[0]	969511	1			T13	30		T15	5		T3	4
all_values[5]	auto[0]	auto[1]	auto[1]	9243561	1			T2	4		T3	1		T17	3
all_values[5]	auto[1]	auto[0]	auto[1]	129140	1			T15	1		T17	2		T76	1
all_values[5]	auto[1]	auto[1]	auto[1]	131107	1			T17	3		T76	2		T21	1
all_values[6]	auto[0]	auto[0]	auto[0]	3316454	1			T1	1		T11	5		T12	1
all_values[6]	auto[0]	auto[0]	auto[1]	9266007	1			T12	4		T13	4		T15	1
all_values[6]	auto[0]	auto[1]	auto[0]	978384	1			T3	2		T17	13		T20	1
all_values[6]	auto[0]	auto[1]	auto[1]	9191989	1			T15	3		T2	4		T3	2
all_values[6]	auto[1]	auto[0]	auto[1]	129527	1			T15	1		T20	1		T21	2
all_values[6]	auto[1]	auto[1]	auto[1]	130473	1			T17	3		T20	1		T81	2
all_values[7]	auto[0]	auto[0]	auto[0]	3320811	1			T1	1		T11	5		T12	5
all_values[7]	auto[0]	auto[0]	auto[1]	9211142	1			T13	15		T15	1		T2	4
all_values[7]	auto[0]	auto[1]	auto[0]	958651	1			T15	5		T3	1		T17	6
all_values[7]	auto[0]	auto[1]	auto[1]	9261506	1			T13	15		T3	2		T17	3
all_values[7]	auto[1]	auto[0]	auto[1]	130037	1			T15	1		T17	1		T20	1
all_values[7]	auto[1]	auto[1]	auto[1]	130687	1			T17	1		T20	1		T21	5
all_values[8]	auto[0]	auto[0]	auto[0]	3311893	1			T1	1		T11	4		T12	1
all_values[8]	auto[0]	auto[0]	auto[1]	9238688	1			T11	1		T13	17		T15	7
all_values[8]	auto[0]	auto[1]	auto[0]	972843	1			T3	3		T17	3		T20	3
all_values[8]	auto[0]	auto[1]	auto[1]	9228932	1			T12	4		T13	11		T2	4
all_values[8]	auto[1]	auto[0]	auto[1]	130516	1			T15	2		T17	4		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	129962	1			T17	1		T20	1		T21	1
all_values[9]	auto[0]	auto[0]	auto[0]	3321137	1			T1	1		T11	4		T12	2
all_values[9]	auto[0]	auto[0]	auto[1]	9222236	1			T11	1		T12	3		T15	1
all_values[9]	auto[0]	auto[1]	auto[0]	968952	1			T13	16		T15	4		T2	1
all_values[9]	auto[0]	auto[1]	auto[1]	9240333	1			T13	14		T15	2		T2	3
all_values[9]	auto[1]	auto[0]	auto[1]	130328	1			T15	1		T17	1		T20	1
all_values[9]	auto[1]	auto[1]	auto[1]	129848	1			T15	2		T17	3		T99	3
all_values[10]	auto[0]	auto[0]	auto[0]	3304463	1			T1	1		T11	5		T12	1
all_values[10]	auto[0]	auto[0]	auto[1]	9292489	1			T13	14		T15	2		T2	1
all_values[10]	auto[0]	auto[1]	auto[0]	978672	1			T13	11		T15	4		T3	2
all_values[10]	auto[0]	auto[1]	auto[1]	9176975	1			T12	4		T15	2		T2	2
all_values[10]	auto[1]	auto[0]	auto[1]	130340	1			T17	2		T20	2		T76	2
all_values[10]	auto[1]	auto[1]	auto[1]	129895	1			T15	2		T17	1		T21	3
all_values[11]	auto[0]	auto[0]	auto[0]	3321659	1			T1	1		T11	5		T12	2
all_values[11]	auto[0]	auto[0]	auto[1]	9211834	1			T12	3		T13	4		T15	2
all_values[11]	auto[0]	auto[1]	auto[0]	963430	1			T13	10		T3	2		T17	2
all_values[11]	auto[0]	auto[1]	auto[1]	9255745	1			T13	1		T2	2		T3	1
all_values[11]	auto[1]	auto[0]	auto[1]	130052	1			T15	2		T17	3		T20	1
all_values[11]	auto[1]	auto[1]	auto[1]	130114	1			T17	2		T76	1		T21	1
all_values[12]	auto[0]	auto[0]	auto[0]	3307834	1			T1	1		T11	5		T12	1
all_values[12]	auto[0]	auto[0]	auto[1]	9246139	1			T13	4		T15	1		T3	6
all_values[12]	auto[0]	auto[1]	auto[0]	977866	1			T12	4		T13	5		T15	3
all_values[12]	auto[0]	auto[1]	auto[1]	9220983	1			T13	21		T15	1		T2	4
all_values[12]	auto[1]	auto[0]	auto[1]	130176	1			T15	1		T21	2		T99	1
all_values[12]	auto[1]	auto[1]	auto[1]	129836	1			T15	1		T17	2		T20	1
all_values[13]	auto[0]	auto[0]	auto[0]	3301896	1			T1	1		T11	4		T12	1
all_values[13]	auto[0]	auto[0]	auto[1]	9217986	1			T11	1		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	auto[0]	971387	1			T12	4		T13	2		T15	8
all_values[13]	auto[0]	auto[1]	auto[1]	9261337	1			T13	28		T15	1		T2	2
all_values[13]	auto[1]	auto[0]	auto[1]	129847	1			T17	1		T20	2		T76	1
all_values[13]	auto[1]	auto[1]	auto[1]	130381	1			T15	1		T17	4		T20	1
all_values[14]	auto[0]	auto[0]	auto[0]	3311773	1			T1	1		T11	5		T12	5
all_values[14]	auto[0]	auto[0]	auto[1]	9254416	1			T2	2		T3	3		T17	1
all_values[14]	auto[0]	auto[1]	auto[0]	964115	1			T13	2		T15	3		T3	3
all_values[14]	auto[0]	auto[1]	auto[1]	9222500	1			T13	28		T2	2		T3	1
all_values[14]	auto[1]	auto[0]	auto[1]	130400	1			T76	1		T21	2		T99	4
all_values[14]	auto[1]	auto[1]	auto[1]	129630	1			T17	5		T21	2		T99	1
all_values[15]	auto[0]	auto[0]	auto[0]	3309565	1			T1	1		T11	3		T12	1
all_values[15]	auto[0]	auto[0]	auto[1]	9224835	1			T11	2		T2	3		T3	4
all_values[15]	auto[0]	auto[1]	auto[0]	977070	1			T12	4		T13	15		T15	5
all_values[15]	auto[0]	auto[1]	auto[1]	9241143	1			T13	15		T2	2		T3	2
all_values[15]	auto[1]	auto[0]	auto[1]	130063	1			T17	2		T20	2		T76	2
all_values[15]	auto[1]	auto[1]	auto[1]	130158	1			T17	5		T21	2		T81	4
all_values[16]	auto[0]	auto[0]	auto[0]	3301127	1			T1	1		T11	4		T12	5
all_values[16]	auto[0]	auto[0]	auto[1]	9288454	1			T11	1		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	auto[0]	968244	1			T13	15		T15	5		T3	5
all_values[16]	auto[0]	auto[1]	auto[1]	9195051	1			T13	15		T2	2		T3	2
all_values[16]	auto[1]	auto[0]	auto[1]	129814	1			T17	4		T20	2		T76	1
all_values[16]	auto[1]	auto[1]	auto[1]	130144	1			T21	7		T99	5		T22	1
all_values[17]	auto[0]	auto[0]	auto[0]	3301848	1			T1	1		T11	4		T12	5
all_values[17]	auto[0]	auto[0]	auto[1]	9249448	1			T11	1		T13	15		T15	1
all_values[17]	auto[0]	auto[1]	auto[0]	980708	1			T13	15		T15	6		T3	2
all_values[17]	auto[0]	auto[1]	auto[1]	9220221	1			T15	1		T3	2		T17	2
all_values[17]	auto[1]	auto[0]	auto[1]	129777	1			T15	2		T17	2		T20	2
all_values[17]	auto[1]	auto[1]	auto[1]	130832	1			T17	2		T21	5		T99	3
all_values[18]	auto[0]	auto[0]	auto[0]	3293269	1			T1	1		T11	3		T12	1
all_values[18]	auto[0]	auto[0]	auto[1]	9237469	1			T11	2		T13	10		T15	1
all_values[18]	auto[0]	auto[1]	auto[0]	972420	1			T12	4		T13	15		T15	1
all_values[18]	auto[0]	auto[1]	auto[1]	9249431	1			T13	4		T15	1		T2	4
all_values[18]	auto[1]	auto[0]	auto[1]	130356	1			T15	2		T17	4		T21	6
all_values[18]	auto[1]	auto[1]	auto[1]	129889	1			T17	1		T20	1		T76	1
all_values[19]	auto[0]	auto[0]	auto[0]	3305567	1			T1	1		T11	5		T12	1
all_values[19]	auto[0]	auto[0]	auto[1]	9260241	1			T12	4		T13	4		T15	1
all_values[19]	auto[0]	auto[1]	auto[0]	963224	1			T13	16		T15	1		T2	1
all_values[19]	auto[0]	auto[1]	auto[1]	9224016	1			T13	10		T15	1		T2	3
all_values[19]	auto[1]	auto[0]	auto[1]	129921	1			T15	2		T17	6		T20	2
all_values[19]	auto[1]	auto[1]	auto[1]	129865	1			T17	1		T76	2		T21	1
all_values[20]	auto[0]	auto[0]	auto[0]	3317455	1			T1	1		T11	4		T12	1
all_values[20]	auto[0]	auto[0]	auto[1]	9195745	1			T11	1		T15	3		T2	2
all_values[20]	auto[0]	auto[1]	auto[0]	964840	1			T13	11		T15	1		T3	2
all_values[20]	auto[0]	auto[1]	auto[1]	9273996	1			T12	4		T15	3		T2	2
all_values[20]	auto[1]	auto[0]	auto[1]	130065	1			T15	2		T17	2		T20	1
all_values[20]	auto[1]	auto[1]	auto[1]	130733	1			T15	1		T17	1		T20	1
all_values[21]	auto[0]	auto[0]	auto[0]	3305957	1			T1	1		T11	5		T12	5
all_values[21]	auto[0]	auto[0]	auto[1]	9238168	1			T13	11		T15	1		T2	5
all_values[21]	auto[0]	auto[1]	auto[0]	966959	1			T3	3		T17	6		T20	1
all_values[21]	auto[0]	auto[1]	auto[1]	9240732	1			T13	11		T3	1		T17	1
all_values[21]	auto[1]	auto[0]	auto[1]	130482	1			T15	1		T17	1		T20	2
all_values[21]	auto[1]	auto[1]	auto[1]	130536	1			T17	1		T20	1		T21	4
all_values[22]	auto[0]	auto[0]	auto[0]	3315070	1			T1	1		T11	4		T12	5
all_values[22]	auto[0]	auto[0]	auto[1]	9238056	1			T11	1		T13	4		T3	6
all_values[22]	auto[0]	auto[1]	auto[0]	964774	1			T15	8		T17	6		T20	9
all_values[22]	auto[0]	auto[1]	auto[1]	9235069	1			T13	11		T2	4		T17	3
all_values[22]	auto[1]	auto[0]	auto[1]	130098	1			T17	3		T76	2		T21	2
all_values[22]	auto[1]	auto[1]	auto[1]	129767	1			T17	2		T76	1		T21	6
all_values[23]	auto[0]	auto[0]	auto[0]	3318154	1			T1	1		T11	5		T12	1
all_values[23]	auto[0]	auto[0]	auto[1]	9262553	1			T12	4		T13	26		T15	2
all_values[23]	auto[0]	auto[1]	auto[0]	962073	1			T3	3		T17	5		T20	1
all_values[23]	auto[0]	auto[1]	auto[1]	9210620	1			T13	4		T2	4		T3	2
all_values[23]	auto[1]	auto[0]	auto[1]	130149	1			T15	2		T17	4		T20	2
all_values[23]	auto[1]	auto[1]	auto[1]	129285	1			T17	3		T20	1		T21	1
all_values[24]	auto[0]	auto[0]	auto[0]	3317287	1			T1	1		T11	5		T12	1
all_values[24]	auto[0]	auto[0]	auto[1]	9212906	1			T15	1		T2	2		T3	4
all_values[24]	auto[0]	auto[1]	auto[0]	969730	1			T12	4		T13	11		T2	1
all_values[24]	auto[0]	auto[1]	auto[1]	9252773	1			T13	4		T2	1		T3	2
all_values[24]	auto[1]	auto[0]	auto[1]	130945	1			T15	1		T20	1		T21	1
all_values[24]	auto[1]	auto[1]	auto[1]	129193	1			T17	5		T76	1		T21	5
all_values[25]	auto[0]	auto[0]	auto[0]	3305165	1			T1	1		T11	5		T12	1
all_values[25]	auto[0]	auto[0]	auto[1]	9225064	1			T12	4		T15	4		T2	3
all_values[25]	auto[0]	auto[1]	auto[0]	975415	1			T13	11		T15	4		T3	1
all_values[25]	auto[0]	auto[1]	auto[1]	9246474	1			T15	1		T2	2		T3	3
all_values[25]	auto[1]	auto[0]	auto[1]	131141	1			T15	2		T17	5		T20	1
all_values[25]	auto[1]	auto[1]	auto[1]	129575	1			T17	1		T20	1		T21	2
all_values[26]	auto[0]	auto[0]	auto[0]	3313960	1			T1	1		T11	4		T12	1
all_values[26]	auto[0]	auto[0]	auto[1]	9242071	1			T11	1		T15	2		T2	5
all_values[26]	auto[0]	auto[1]	auto[0]	957240	1			T12	2		T13	7		T15	2
all_values[26]	auto[0]	auto[1]	auto[1]	9239285	1			T12	2		T13	8		T15	2
all_values[26]	auto[1]	auto[0]	auto[1]	129962	1			T15	1		T17	1		T76	1
all_values[26]	auto[1]	auto[1]	auto[1]	130316	1			T15	1		T17	2		T21	4
all_values[27]	auto[0]	auto[0]	auto[0]	3317219	1			T1	1		T11	5		T12	5
all_values[27]	auto[0]	auto[0]	auto[1]	9270464	1			T13	15		T3	4		T17	2
all_values[27]	auto[0]	auto[1]	auto[0]	957027	1			T13	1		T17	8		T20	6
all_values[27]	auto[0]	auto[1]	auto[1]	9207881	1			T13	14		T2	2		T3	3
all_values[27]	auto[1]	auto[0]	auto[1]	130413	1			T21	1		T99	2		T81	3
all_values[27]	auto[1]	auto[1]	auto[1]	129830	1			T17	3		T20	1		T76	1
all_values[28]	auto[0]	auto[0]	auto[0]	3310785	1			T1	1		T11	5		T12	5
all_values[28]	auto[0]	auto[0]	auto[1]	9217829	1			T13	15		T15	1		T3	5
all_values[28]	auto[0]	auto[1]	auto[0]	969784	1			T13	7		T15	2		T2	2
all_values[28]	auto[0]	auto[1]	auto[1]	9253856	1			T13	8		T2	2		T3	2
all_values[28]	auto[1]	auto[0]	auto[1]	130424	1			T15	1		T17	1		T76	1
all_values[28]	auto[1]	auto[1]	auto[1]	130156	1			T17	1		T20	1		T99	3
all_values[29]	auto[0]	auto[0]	auto[0]	3301235	1			T1	1		T11	5		T12	1
all_values[29]	auto[0]	auto[0]	auto[1]	9282751	1			T15	5		T3	3		T17	1
all_values[29]	auto[0]	auto[1]	auto[0]	970880	1			T12	4		T13	4		T3	5
all_values[29]	auto[0]	auto[1]	auto[1]	9197490	1			T13	15		T15	3		T3	3
all_values[29]	auto[1]	auto[0]	auto[1]	130915	1			T15	2		T17	1		T21	1
all_values[29]	auto[1]	auto[1]	auto[1]	129563	1			T17	1		T20	1		T21	1
all_values[30]	auto[0]	auto[0]	auto[0]	3307002	1			T1	1		T11	4		T12	1
all_values[30]	auto[0]	auto[0]	auto[1]	9294094	1			T11	1		T12	4		T13	26
all_values[30]	auto[0]	auto[1]	auto[0]	956811	1			T15	2		T3	2		T17	6
all_values[30]	auto[0]	auto[1]	auto[1]	9194964	1			T13	4		T3	2		T17	1
all_values[30]	auto[1]	auto[0]	auto[1]	130571	1			T15	1		T17	2		T76	2
all_values[30]	auto[1]	auto[1]	auto[1]	129392	1			T17	1		T76	1		T21	1
all_values[31]	auto[0]	auto[0]	auto[0]	3306731	1			T1	1		T11	4		T12	1
all_values[31]	auto[0]	auto[0]	auto[1]	9206028	1			T11	1		T13	15		T2	5
all_values[31]	auto[0]	auto[1]	auto[0]	964992	1			T12	1		T13	1		T15	4
all_values[31]	auto[0]	auto[1]	auto[1]	9275058	1			T12	3		T13	14		T15	2
all_values[31]	auto[1]	auto[0]	auto[1]	130062	1			T15	1		T17	1		T20	3
all_values[31]	auto[1]	auto[1]	auto[1]	129963	1			T15	1		T17	3		T76	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal