Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[1]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[2]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[3]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[4]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[5]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[6]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[7]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[8]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[9]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[10]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[11]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[12]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[13]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[14]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[15]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[16]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[17]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[18]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[19]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[20]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[21]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[22]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[23]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[24]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[25]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[26]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[27]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[28]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[29]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[30]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[31]	22637396	1			T1	1		T11	5		T12	5

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449073638

1

T1

32

T11

160

T12

160

auto[1]

275323034

1

T42

9983

T43

5771

T44

6220

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576534362

1

T1

32

T11

160

T12

160

auto[1]

147862310

1

T42

4997

T43

7728

T44

11022

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

532983048

1

T1

32

T11

160

T12

160

auto[1]

191413624

1

T42

5251

T43

7842

T44

10816

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	8516519	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5808369	1			T42	171		T43	57		T44	25
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2329204	1			T42	64		T43	126		T44	162
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	3166756	1			T43	118		T44	181		T54	180
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	512499	1			T42	83		T58	34		T103	162
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2304049	1			T42	72		T43	110		T44	158
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	8544531	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5788804	1			T42	126		T43	69		T44	19
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2327119	1			T42	84		T43	130		T44	162
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	3167061	1			T43	144		T44	161		T54	174
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	512206	1			T42	82		T58	30		T103	128
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2297675	1			T42	93		T43	107		T44	206
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	8532549	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5805445	1			T42	149		T43	67		T44	21
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2325872	1			T42	89		T43	147		T44	179
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	3164030	1			T43	114		T44	158		T54	163
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	509426	1			T42	76		T58	22		T103	172
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2300074	1			T42	72		T43	102		T44	166
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	8525773	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5803515	1			T42	148		T43	61		T44	20
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2325861	1			T42	82		T43	100		T44	148
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3168310	1			T43	134		T44	184		T54	128
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	508166	1			T42	72		T58	50		T103	178
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2305771	1			T42	79		T43	117		T44	184
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	8536070	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5794949	1			T42	171		T43	65		T44	19
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2320666	1			T42	65		T43	108		T44	203
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	3169786	1			T43	167		T44	150		T54	168
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	509698	1			T42	116		T58	50		T103	128
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2306227	1			T42	40		T43	120		T44	166
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	8545887	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5798447	1			T42	159		T43	64		T44	26
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2327692	1			T42	92		T43	106		T44	176
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3157327	1			T43	145		T44	155		T54	216
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	507953	1			T42	60		T58	42		T103	156
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2300090	1			T42	76		T43	90		T44	176
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	8516918	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5799382	1			T42	173		T43	58		T44	18
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2322643	1			T42	65		T43	98		T44	190
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	3173602	1			T43	157		T44	165		T54	162
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	511971	1			T42	92		T58	56		T103	158
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2312880	1			T42	64		T43	106		T44	150
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	8540012	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5793120	1			T42	163		T43	52		T44	18
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2324371	1			T42	56		T43	122		T44	158
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	3165762	1			T43	105		T44	162		T54	135
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	512774	1			T42	88		T58	50		T103	141
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2301357	1			T42	84		T43	158		T44	186
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	8533281	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5800822	1			T42	136		T43	56		T44	17
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2321441	1			T42	85		T43	136		T44	158
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	3165194	1			T43	111		T44	160		T54	154
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	510349	1			T42	64		T58	52		T103	156
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2306309	1			T42	96		T43	136		T44	195
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	8563895	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5777540	1			T42	125		T43	55		T44	23
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2326524	1			T42	60		T43	127		T44	206
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	3160950	1			T43	114		T44	181		T54	128
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	509537	1			T42	108		T58	44		T103	145
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2298950	1			T42	84		T43	102		T44	146
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	8545846	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5783568	1			T42	179		T43	59		T44	25
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2323377	1			T42	78		T43	139		T44	183
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	3173885	1			T43	134		T44	146		T54	162
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	511627	1			T42	68		T58	46		T103	176
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2299093	1			T42	63		T43	122		T44	146
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	8540174	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5795463	1			T42	155		T43	64		T44	21
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2323220	1			T42	52		T43	106		T44	151
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	3169433	1			T43	133		T44	186		T54	172
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	510609	1			T42	98		T58	52		T103	153
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2298497	1			T42	89		T43	150		T44	166
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	8536539	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5791513	1			T42	160		T43	60		T44	21
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2328181	1			T42	86		T43	128		T44	124
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	3167113	1			T43	127		T44	227		T54	163
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	511497	1			T42	60		T58	61		T103	171
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2302553	1			T42	95		T43	124		T44	160
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	8525639	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5799632	1			T42	115		T43	66		T44	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2328011	1			T42	56		T43	132		T44	132
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3167694	1			T43	114		T44	199		T54	143
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	509068	1			T42	104		T58	76		T103	162
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2307352	1			T42	116		T43	89		T44	164
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	8544528	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5781685	1			T42	140		T43	62		T44	22
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2324656	1			T42	94		T43	128		T44	157
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3168935	1			T43	94		T44	144		T54	158
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	510478	1			T42	74		T58	50		T103	138
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2307114	1			T42	78		T43	117		T44	196
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	8534953	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5790129	1			T42	131		T43	63		T44	16
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2324840	1			T42	85		T43	160		T44	152
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	3170024	1			T43	112		T44	186		T54	144
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	509591	1			T42	72		T58	70		T103	185
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2307859	1			T42	92		T43	116		T44	189
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	8542936	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5789858	1			T42	117		T43	64		T44	17
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2320977	1			T42	92		T43	128		T44	202
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3173605	1			T43	111		T44	156		T54	159
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	514442	1			T42	78		T58	44		T103	125
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2295578	1			T42	89		T43	124		T44	163
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	8546069	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5798817	1			T42	160		T43	71		T44	21
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2316109	1			T42	78		T43	122		T44	149
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	3176716	1			T43	117		T44	200		T54	168
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	510087	1			T42	90		T58	40		T103	152
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2289598	1			T42	58		T43	134		T44	148
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	8542460	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5797077	1			T42	151		T43	71		T44	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2312395	1			T42	83		T43	154		T44	170
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	3176191	1			T43	106		T44	166		T54	174
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	511879	1			T42	78		T58	50		T103	147
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2297394	1			T42	78		T43	90		T44	182
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	8548984	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5795101	1			T42	147		T43	66		T44	21
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2320912	1			T42	74		T43	122		T44	184
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3169412	1			T43	132		T44	131		T54	180
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	510408	1			T42	80		T58	30		T103	178
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2292579	1			T42	83		T43	107		T44	180
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	8558087	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5781739	1			T42	156		T43	61		T44	25
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2313158	1			T42	47		T43	124		T44	186
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3177177	1			T43	119		T44	154		T54	148
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	513517	1			T42	98		T58	34		T103	152
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2293718	1			T42	98		T43	108		T44	178
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	8545182	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5794763	1			T42	129		T43	62		T44	23
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2317515	1			T42	65		T43	142		T44	140
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3174121	1			T43	130		T44	180		T54	166
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	511822	1			T42	96		T58	48		T103	148
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2293993	1			T42	88		T43	118		T44	200
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	8550589	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5780885	1			T42	140		T43	53		T44	19
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2314761	1			T42	67		T43	117		T44	165
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	3176486	1			T43	120		T44	144		T54	174
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	514443	1			T42	94		T58	36		T103	122
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2300232	1			T42	90		T43	128		T44	168
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	8548980	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5793767	1			T42	154		T43	64		T44	24
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2317112	1			T42	76		T43	114		T44	191
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3173063	1			T43	129		T44	138		T54	144
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	510676	1			T42	64		T58	50		T103	178
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2293798	1			T42	92		T43	134		T44	190
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	8545094	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5797706	1			T42	168		T43	65		T44	20
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2312439	1			T42	80		T43	104		T44	193
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3173386	1			T43	159		T44	156		T54	189
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	511281	1			T42	71		T58	58		T103	162
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2297490	1			T42	68		T43	128		T44	148
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	8545853	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5792681	1			T42	144		T43	68		T44	20
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2317873	1			T42	64		T43	150		T44	175
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	3169731	1			T43	96		T44	150		T54	148
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	511216	1			T42	102		T58	61		T103	180
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2300042	1			T42	73		T43	135		T44	186
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	8551453	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5790444	1			T42	155		T43	68		T44	23
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2318223	1			T42	74		T43	94		T44	166
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3171511	1			T43	169		T44	132		T54	174
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	511154	1			T42	58		T58	60		T103	174
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2294611	1			T42	90		T43	102		T44	195
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	8544971	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5792851	1			T42	152		T43	66		T44	18
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2318162	1			T42	82		T43	130		T44	212
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3168939	1			T43	149		T44	131		T54	112
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	513407	1			T42	61		T58	48		T103	166
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2299066	1			T42	98		T43	118		T44	160
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	8541291	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5800536	1			T42	141		T43	64		T44	17
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2320769	1			T42	94		T43	128		T44	185
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	3166978	1			T43	123		T44	148		T54	151
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	510277	1			T42	78		T58	60		T103	176
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2297545	1			T42	74		T43	112		T44	180
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	8550488	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5782370	1			T42	133		T43	60		T44	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2315368	1			T42	78		T43	111		T44	182
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3176918	1			T43	146		T44	176		T54	148
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	511866	1			T42	86		T58	70		T103	146
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2300386	1			T42	94		T43	106		T44	179
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	8554076	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5783201	1			T42	126		T43	66		T44	21
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2311657	1			T42	80		T43	119		T44	168
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3177800	1			T43	122		T44	178		T54	155
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	510438	1			T42	115		T58	48		T103	134
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2300224	1			T42	64		T43	126		T44	157
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	8545108	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5787089	1			T42	158		T43	60		T44	17
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2315937	1			T42	74		T43	112		T44	154
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3183962	1			T43	127		T44	172		T54	175
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	512139	1			T42	89		T58	42		T103	130
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2293161	1			T42	66		T43	128		T44	191

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal