Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[1]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[2]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[3]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[4]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[5]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[6]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[7]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[8]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[9]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[10]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[11]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[12]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[13]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[14]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[15]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[16]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[17]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[18]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[19]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[20]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[21]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[22]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[23]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[24]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[25]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[26]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[27]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[28]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[29]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[30]	22637396	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[31]	22637396	1			T1	1		T11	5		T12	5

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449073638

1

T1

32

T11

160

T12

160

auto[1]

275323034

1

T42

9983

T43

5771

T44

6220

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449063626

1

T1

32

T11

146

T12

132

auto[1]

275333046

1

T11

14

T12

28

T13

233

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	13600154	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[0]	auto[0]	auto[1]	412034	1			T42	16		T43	29		T44	43
bins_for_gpio_bits[0]	auto[1]	auto[0]	412325	1			T13	3		T2	3		T3	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	8212883	1			T42	310		T43	138		T44	140
bins_for_gpio_bits[1]	auto[0]	auto[0]	13627736	1			T1	1		T11	4		T12	3
bins_for_gpio_bits[1]	auto[0]	auto[1]	410644	1			T42	21		T43	34		T44	49
bins_for_gpio_bits[1]	auto[1]	auto[0]	410975	1			T11	1		T12	2		T13	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	8188041	1			T42	280		T43	142		T44	176
bins_for_gpio_bits[2]	auto[0]	auto[0]	13611038	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[2]	auto[0]	auto[1]	411091	1			T42	21		T43	29		T44	48
bins_for_gpio_bits[2]	auto[1]	auto[0]	411413	1			T11	1		T13	10		T2	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	8203854	1			T42	276		T43	140		T44	139
bins_for_gpio_bits[3]	auto[0]	auto[0]	13607677	1			T1	1		T11	5		T12	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	411959	1			T42	24		T43	31		T44	42
bins_for_gpio_bits[3]	auto[1]	auto[0]	412267	1			T12	4		T13	3		T3	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	8205493	1			T42	275		T43	147		T44	162
bins_for_gpio_bits[4]	auto[0]	auto[0]	13614506	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[4]	auto[0]	auto[1]	411710	1			T42	16		T43	36		T44	39
bins_for_gpio_bits[4]	auto[1]	auto[0]	412016	1			T11	1		T13	3		T3	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	8199164	1			T42	311		T43	149		T44	146
bins_for_gpio_bits[5]	auto[0]	auto[0]	13619751	1			T1	1		T11	5		T12	4
bins_for_gpio_bits[5]	auto[0]	auto[1]	410841	1			T42	20		T43	29		T44	46
bins_for_gpio_bits[5]	auto[1]	auto[0]	411155	1			T12	1		T2	1		T3	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	8195649	1			T42	275		T43	125		T44	156
bins_for_gpio_bits[6]	auto[0]	auto[0]	13600882	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[6]	auto[0]	auto[1]	411966	1			T42	17		T43	33		T44	39
bins_for_gpio_bits[6]	auto[1]	auto[0]	412281	1			T13	5		T3	5		T24	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	8212267	1			T42	312		T43	131		T44	129
bins_for_gpio_bits[7]	auto[0]	auto[0]	13618245	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[7]	auto[0]	auto[1]	411568	1			T42	17		T43	33		T44	47
bins_for_gpio_bits[7]	auto[1]	auto[0]	411900	1			T13	15		T2	1		T3	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	8195683	1			T42	318		T43	177		T44	157
bins_for_gpio_bits[8]	auto[0]	auto[0]	13608261	1			T1	1		T11	5		T12	3
bins_for_gpio_bits[8]	auto[0]	auto[1]	411350	1			T42	21		T43	34		T44	41
bins_for_gpio_bits[8]	auto[1]	auto[0]	411655	1			T12	2		T13	12		T3	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	8206130	1			T42	275		T43	158		T44	171
bins_for_gpio_bits[9]	auto[0]	auto[0]	13640362	1			T1	1		T11	5		T12	3
bins_for_gpio_bits[9]	auto[0]	auto[1]	410681	1			T42	16		T43	27		T44	43
bins_for_gpio_bits[9]	auto[1]	auto[0]	411007	1			T12	2		T13	7		T3	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	8175346	1			T42	301		T43	130		T44	126
bins_for_gpio_bits[10]	auto[0]	auto[0]	13631185	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[10]	auto[0]	auto[1]	411639	1			T42	18		T43	31		T44	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	411923	1			T13	7		T2	1		T3	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	8182649	1			T42	292		T43	150		T44	132
bins_for_gpio_bits[11]	auto[0]	auto[0]	13621744	1			T1	1		T11	4		T12	3
bins_for_gpio_bits[11]	auto[0]	auto[1]	410813	1			T42	16		T43	31		T44	39
bins_for_gpio_bits[11]	auto[1]	auto[0]	411083	1			T11	1		T12	2		T13	4
bins_for_gpio_bits[11]	auto[1]	auto[1]	8193756	1			T42	326		T43	183		T44	148
bins_for_gpio_bits[12]	auto[0]	auto[0]	13620070	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[12]	auto[0]	auto[1]	411419	1			T42	27		T43	31		T44	44
bins_for_gpio_bits[12]	auto[1]	auto[0]	411763	1			T13	6		T2	2		T3	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	8194144	1			T42	288		T43	153		T44	137
bins_for_gpio_bits[13]	auto[0]	auto[0]	13608928	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[13]	auto[0]	auto[1]	412117	1			T42	16		T43	26		T44	47
bins_for_gpio_bits[13]	auto[1]	auto[0]	412416	1			T11	1		T13	15		T2	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	8203935	1			T42	319		T43	129		T44	140
bins_for_gpio_bits[14]	auto[0]	auto[0]	13626496	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[14]	auto[0]	auto[1]	411305	1			T42	19		T43	27		T44	46
bins_for_gpio_bits[14]	auto[1]	auto[0]	411623	1			T13	12		T2	2		T3	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	8187972	1			T42	273		T43	152		T44	172
bins_for_gpio_bits[15]	auto[0]	auto[0]	13617363	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[15]	auto[0]	auto[1]	412155	1			T42	23		T43	34		T44	50
bins_for_gpio_bits[15]	auto[1]	auto[0]	412454	1			T11	1		T2	1		T3	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	8195424	1			T42	272		T43	145		T44	155
bins_for_gpio_bits[16]	auto[0]	auto[0]	13625662	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[16]	auto[0]	auto[1]	411540	1			T42	18		T43	33		T44	44
bins_for_gpio_bits[16]	auto[1]	auto[0]	411856	1			T11	1		T2	3		T3	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	8188338	1			T42	266		T43	155		T44	136
bins_for_gpio_bits[17]	auto[0]	auto[0]	13626834	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[17]	auto[0]	auto[1]	411749	1			T42	21		T43	34		T44	45
bins_for_gpio_bits[17]	auto[1]	auto[0]	412060	1			T11	1		T13	14		T2	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	8186753	1			T42	287		T43	171		T44	124
bins_for_gpio_bits[18]	auto[0]	auto[0]	13619308	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[18]	auto[0]	auto[1]	411409	1			T42	19		T43	26		T44	38
bins_for_gpio_bits[18]	auto[1]	auto[0]	411738	1			T11	1		T13	10		T2	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	8194941	1			T42	288		T43	135		T44	167
bins_for_gpio_bits[19]	auto[0]	auto[0]	13627344	1			T1	1		T11	5		T12	3
bins_for_gpio_bits[19]	auto[0]	auto[1]	411623	1			T42	18		T43	28		T44	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	411964	1			T12	2		T13	8		T2	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	8186465	1			T42	292		T43	145		T44	161
bins_for_gpio_bits[20]	auto[0]	auto[0]	13637118	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[20]	auto[0]	auto[1]	411025	1			T42	18		T43	27		T44	48
bins_for_gpio_bits[20]	auto[1]	auto[0]	411304	1			T11	1		T2	3		T3	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	8177949	1			T42	334		T43	142		T44	155
bins_for_gpio_bits[21]	auto[0]	auto[0]	13625390	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[21]	auto[0]	auto[1]	411107	1			T42	19		T43	32		T44	43
bins_for_gpio_bits[21]	auto[1]	auto[0]	411428	1			T13	12		T2	3		T3	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	8189471	1			T42	294		T43	148		T44	180
bins_for_gpio_bits[22]	auto[0]	auto[0]	13628927	1			T1	1		T11	4		T12	5
bins_for_gpio_bits[22]	auto[0]	auto[1]	412589	1			T42	25		T43	31		T44	39
bins_for_gpio_bits[22]	auto[1]	auto[0]	412909	1			T11	1		T13	3		T2	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	8182971	1			T42	299		T43	150		T44	148
bins_for_gpio_bits[23]	auto[0]	auto[0]	13627102	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[23]	auto[0]	auto[1]	411729	1			T42	23		T43	34		T44	41
bins_for_gpio_bits[23]	auto[1]	auto[0]	412053	1			T13	12		T2	3		T3	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	8186512	1			T42	287		T43	164		T44	173
bins_for_gpio_bits[24]	auto[0]	auto[0]	13618800	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[24]	auto[0]	auto[1]	411776	1			T42	18		T43	29		T44	43
bins_for_gpio_bits[24]	auto[1]	auto[0]	412119	1			T13	2		T3	4		T73	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	8194701	1			T42	289		T43	164		T44	125
bins_for_gpio_bits[25]	auto[0]	auto[0]	13621228	1			T1	1		T11	5		T12	3
bins_for_gpio_bits[25]	auto[0]	auto[1]	411922	1			T42	13		T43	32		T44	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	412229	1			T12	2		T3	4		T73	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	8192017	1			T42	306		T43	171		T44	165
bins_for_gpio_bits[26]	auto[0]	auto[0]	13628953	1			T1	1		T11	4		T12	3
bins_for_gpio_bits[26]	auto[0]	auto[1]	411933	1			T42	23		T43	28		T44	37
bins_for_gpio_bits[26]	auto[1]	auto[0]	412234	1			T11	1		T12	2		T13	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	8184276	1			T42	280		T43	142		T44	181
bins_for_gpio_bits[27]	auto[0]	auto[0]	13619595	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	412097	1			T42	22		T43	34		T44	44
bins_for_gpio_bits[27]	auto[1]	auto[0]	412477	1			T13	17		T2	5		T3	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	8193227	1			T42	289		T43	150		T44	134
bins_for_gpio_bits[28]	auto[0]	auto[0]	13617616	1			T1	1		T11	5		T12	5
bins_for_gpio_bits[28]	auto[0]	auto[1]	411121	1			T42	23		T43	28		T44	47
bins_for_gpio_bits[28]	auto[1]	auto[0]	411422	1			T13	14		T2	2		T3	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	8197237	1			T42	270		T43	148		T44	150
bins_for_gpio_bits[29]	auto[0]	auto[0]	13630289	1			T1	1		T11	4		T12	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	412170	1			T42	23		T43	32		T44	45
bins_for_gpio_bits[29]	auto[1]	auto[0]	412485	1			T11	1		T12	4		T13	6
bins_for_gpio_bits[29]	auto[1]	auto[1]	8182452	1			T42	290		T43	134		T44	152
bins_for_gpio_bits[30]	auto[0]	auto[0]	13631114	1			T1	1		T11	4		T12	3
bins_for_gpio_bits[30]	auto[0]	auto[1]	412133	1			T42	14		T43	35		T44	45
bins_for_gpio_bits[30]	auto[1]	auto[0]	412419	1			T11	1		T12	2		T13	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	8181730	1			T42	291		T43	157		T44	133
bins_for_gpio_bits[31]	auto[0]	auto[0]	13632599	1			T1	1		T11	5		T12	2
bins_for_gpio_bits[31]	auto[0]	auto[1]	412134	1			T42	17		T43	34		T44	45
bins_for_gpio_bits[31]	auto[1]	auto[0]	412408	1			T12	3		T13	7		T2	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	8180255	1			T42	296		T43	154		T44	163