Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678125 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10334709 |
1 |
|
|
T13 |
30 |
|
T15 |
3 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21673616 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1339218 |
1 |
|
|
T6 |
3 |
|
T93 |
2 |
|
T94 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12672230 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10340604 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4513959 |
1 |
|
|
T12 |
4 |
|
T3 |
3 |
|
T24 |
7 |
| auto[1] |
auto[0] |
auto[1] |
671367 |
1 |
|
|
T6 |
3 |
|
T94 |
1 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4487427 |
1 |
|
|
T13 |
15 |
|
T3 |
3 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
667851 |
1 |
|
|
T93 |
2 |
|
T35 |
2223 |
|
T52 |
8331 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12692888 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10319946 |
1 |
|
|
T15 |
5 |
|
T3 |
7 |
|
T17 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21673261 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1339573 |
1 |
|
|
T13 |
4 |
|
T78 |
1 |
|
T93 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12680407 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10332427 |
1 |
|
|
T13 |
19 |
|
T3 |
6 |
|
T73 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4504690 |
1 |
|
|
T13 |
15 |
|
T3 |
2 |
|
T73 |
3 |
| auto[1] |
auto[0] |
auto[1] |
671547 |
1 |
|
|
T13 |
4 |
|
T78 |
1 |
|
T80 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4488164 |
1 |
|
|
T3 |
4 |
|
T24 |
4 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
668026 |
1 |
|
|
T93 |
5 |
|
T95 |
1 |
|
T35 |
2316 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12727292 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10285542 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T15 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21673576 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1339258 |
1 |
|
|
T78 |
1 |
|
T93 |
1 |
|
T35 |
5000 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12675739 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10337095 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4527653 |
1 |
|
|
T13 |
4 |
|
T3 |
2 |
|
T73 |
3 |
| auto[1] |
auto[0] |
auto[1] |
675319 |
1 |
|
|
T78 |
1 |
|
T35 |
2627 |
|
T52 |
8276 |
| auto[1] |
auto[1] |
auto[0] |
4470184 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T3 |
3 |
| auto[1] |
auto[1] |
auto[1] |
663939 |
1 |
|
|
T93 |
1 |
|
T35 |
2373 |
|
T52 |
7293 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12663545 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10349289 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21672660 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
4 |
| auto[1] |
1340174 |
1 |
|
|
T12 |
1 |
|
T6 |
5 |
|
T93 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12668972 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10343862 |
1 |
|
|
T12 |
4 |
|
T13 |
26 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4503083 |
1 |
|
|
T12 |
3 |
|
T13 |
15 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
671586 |
1 |
|
|
T12 |
1 |
|
T93 |
1 |
|
T35 |
2326 |
| auto[1] |
auto[1] |
auto[0] |
4500605 |
1 |
|
|
T13 |
11 |
|
T3 |
1 |
|
T73 |
3 |
| auto[1] |
auto[1] |
auto[1] |
668588 |
1 |
|
|
T6 |
5 |
|
T35 |
2635 |
|
T52 |
7259 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12684149 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10328685 |
1 |
|
|
T12 |
4 |
|
T13 |
26 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21678399 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1334435 |
1 |
|
|
T93 |
3 |
|
T80 |
1 |
|
T105 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12697232 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10315602 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T73 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4490557 |
1 |
|
|
T3 |
3 |
|
T73 |
3 |
|
T24 |
7 |
| auto[1] |
auto[0] |
auto[1] |
666923 |
1 |
|
|
T93 |
3 |
|
T80 |
1 |
|
T105 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4490610 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[1] |
667512 |
1 |
|
|
T35 |
2595 |
|
T52 |
7800 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12649729 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10363105 |
1 |
|
|
T12 |
4 |
|
T13 |
30 |
|
T15 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21669388 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1343446 |
1 |
|
|
T13 |
5 |
|
T106 |
1 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12657576 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10355258 |
1 |
|
|
T13 |
19 |
|
T3 |
8 |
|
T24 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4498788 |
1 |
|
|
T3 |
6 |
|
T24 |
7 |
|
T98 |
1 |
| auto[1] |
auto[0] |
auto[1] |
669914 |
1 |
|
|
T10 |
1 |
|
T35 |
2303 |
|
T52 |
7373 |
| auto[1] |
auto[1] |
auto[0] |
4513024 |
1 |
|
|
T13 |
14 |
|
T3 |
2 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
673532 |
1 |
|
|
T13 |
5 |
|
T106 |
1 |
|
T104 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12696589 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10316245 |
1 |
|
|
T13 |
30 |
|
T15 |
3 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21664000 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1348834 |
1 |
|
|
T13 |
4 |
|
T2 |
1 |
|
T6 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12623228 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10389606 |
1 |
|
|
T12 |
4 |
|
T13 |
19 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4528900 |
1 |
|
|
T12 |
4 |
|
T2 |
2 |
|
T3 |
6 |
| auto[1] |
auto[0] |
auto[1] |
675444 |
1 |
|
|
T93 |
4 |
|
T35 |
2548 |
|
T52 |
7874 |
| auto[1] |
auto[1] |
auto[0] |
4511872 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
auto[1] |
auto[1] |
673390 |
1 |
|
|
T13 |
4 |
|
T2 |
1 |
|
T6 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12664463 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10348371 |
1 |
|
|
T12 |
4 |
|
T13 |
30 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21672483 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1340351 |
1 |
|
|
T6 |
3 |
|
T106 |
1 |
|
T93 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12684363 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10328471 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4488406 |
1 |
|
|
T3 |
4 |
|
T73 |
3 |
|
T24 |
5 |
| auto[1] |
auto[0] |
auto[1] |
669100 |
1 |
|
|
T104 |
1 |
|
T35 |
2576 |
|
T52 |
7585 |
| auto[1] |
auto[1] |
auto[0] |
4499714 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[1] |
671251 |
1 |
|
|
T6 |
3 |
|
T106 |
1 |
|
T93 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12719395 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10293439 |
1 |
|
|
T13 |
30 |
|
T15 |
5 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21680132 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1332702 |
1 |
|
|
T73 |
1 |
|
T98 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12713327 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10299507 |
1 |
|
|
T13 |
15 |
|
T3 |
3 |
|
T73 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4503424 |
1 |
|
|
T24 |
5 |
|
T32 |
1 |
|
T77 |
1 |
| auto[1] |
auto[0] |
auto[1] |
670652 |
1 |
|
|
T5 |
1 |
|
T93 |
4 |
|
T95 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4463381 |
1 |
|
|
T13 |
15 |
|
T3 |
3 |
|
T73 |
2 |
| auto[1] |
auto[1] |
auto[1] |
662050 |
1 |
|
|
T73 |
1 |
|
T98 |
1 |
|
T35 |
2479 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681073 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10331761 |
1 |
|
|
T13 |
15 |
|
T15 |
7 |
|
T3 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21677468 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1335366 |
1 |
|
|
T13 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12703811 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10309023 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4503602 |
1 |
|
|
T13 |
14 |
|
T3 |
4 |
|
T24 |
6 |
| auto[1] |
auto[0] |
auto[1] |
671386 |
1 |
|
|
T13 |
1 |
|
T2 |
1 |
|
T83 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4470055 |
1 |
|
|
T3 |
3 |
|
T24 |
2 |
|
T98 |
1 |
| auto[1] |
auto[1] |
auto[1] |
663980 |
1 |
|
|
T5 |
1 |
|
T35 |
2654 |
|
T52 |
7697 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661094 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10351740 |
1 |
|
|
T12 |
4 |
|
T13 |
19 |
|
T15 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21679899 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1332935 |
1 |
|
|
T2 |
1 |
|
T77 |
1 |
|
T6 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12713957 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10298877 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4461934 |
1 |
|
|
T3 |
4 |
|
T24 |
7 |
|
T32 |
1 |
| auto[1] |
auto[0] |
auto[1] |
662503 |
1 |
|
|
T77 |
1 |
|
T6 |
3 |
|
T35 |
2406 |
| auto[1] |
auto[1] |
auto[0] |
4504008 |
1 |
|
|
T13 |
15 |
|
T3 |
2 |
|
T73 |
3 |
| auto[1] |
auto[1] |
auto[1] |
670432 |
1 |
|
|
T2 |
1 |
|
T93 |
3 |
|
T35 |
2408 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12695729 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10317105 |
1 |
|
|
T13 |
26 |
|
T15 |
2 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21677395 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
4 |
| auto[1] |
1335439 |
1 |
|
|
T12 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12723664 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10289170 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4474531 |
1 |
|
|
T12 |
3 |
|
T3 |
6 |
|
T24 |
6 |
| auto[1] |
auto[0] |
auto[1] |
667751 |
1 |
|
|
T12 |
1 |
|
T83 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4479200 |
1 |
|
|
T13 |
15 |
|
T2 |
3 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[1] |
667688 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T35 |
2283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12665213 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10347621 |
1 |
|
|
T12 |
4 |
|
T13 |
26 |
|
T15 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21670200 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1342634 |
1 |
|
|
T13 |
2 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12665659 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10347175 |
1 |
|
|
T13 |
19 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4513292 |
1 |
|
|
T13 |
2 |
|
T3 |
1 |
|
T24 |
8 |
| auto[1] |
auto[0] |
auto[1] |
673954 |
1 |
|
|
T13 |
2 |
|
T6 |
2 |
|
T93 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4491249 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[1] |
668680 |
1 |
|
|
T5 |
1 |
|
T104 |
1 |
|
T105 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12643265 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10369569 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21678797 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1334037 |
1 |
|
|
T2 |
1 |
|
T83 |
2 |
|
T6 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12710523 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10302311 |
1 |
|
|
T12 |
4 |
|
T13 |
30 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4483355 |
1 |
|
|
T13 |
19 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
auto[0] |
auto[1] |
666135 |
1 |
|
|
T2 |
1 |
|
T83 |
2 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4484919 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
667902 |
1 |
|
|
T93 |
1 |
|
T35 |
2634 |
|
T52 |
7759 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12674607 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10338227 |
1 |
|
|
T13 |
11 |
|
T3 |
4 |
|
T17 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21669256 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1343578 |
1 |
|
|
T13 |
3 |
|
T73 |
1 |
|
T98 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12670138 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10342696 |
1 |
|
|
T12 |
4 |
|
T13 |
19 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4488245 |
1 |
|
|
T12 |
4 |
|
T13 |
16 |
|
T3 |
4 |
| auto[1] |
auto[0] |
auto[1] |
669228 |
1 |
|
|
T13 |
3 |
|
T73 |
1 |
|
T6 |
5 |
| auto[1] |
auto[1] |
auto[0] |
4510873 |
1 |
|
|
T3 |
2 |
|
T24 |
2 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[1] |
674350 |
1 |
|
|
T98 |
1 |
|
T77 |
1 |
|
T79 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683224 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10329610 |
1 |
|
|
T13 |
11 |
|
T15 |
8 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21669894 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1342940 |
1 |
|
|
T77 |
1 |
|
T93 |
4 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12654963 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10357871 |
1 |
|
|
T12 |
4 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4506190 |
1 |
|
|
T12 |
4 |
|
T3 |
7 |
|
T24 |
4 |
| auto[1] |
auto[0] |
auto[1] |
670895 |
1 |
|
|
T93 |
3 |
|
T35 |
2703 |
|
T52 |
7132 |
| auto[1] |
auto[1] |
auto[0] |
4508741 |
1 |
|
|
T2 |
1 |
|
T73 |
3 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[1] |
672045 |
1 |
|
|
T77 |
1 |
|
T93 |
1 |
|
T80 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12710856 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10301978 |
1 |
|
|
T13 |
4 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21683026 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1329808 |
1 |
|
|
T73 |
1 |
|
T78 |
1 |
|
T6 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12747456 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10265378 |
1 |
|
|
T13 |
4 |
|
T2 |
3 |
|
T3 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4484741 |
1 |
|
|
T3 |
2 |
|
T24 |
8 |
|
T98 |
1 |
| auto[1] |
auto[0] |
auto[1] |
667530 |
1 |
|
|
T78 |
1 |
|
T6 |
2 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4450829 |
1 |
|
|
T13 |
4 |
|
T2 |
3 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[1] |
662278 |
1 |
|
|
T73 |
1 |
|
T6 |
3 |
|
T35 |
2435 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661138 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10351696 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21674054 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1338780 |
1 |
|
|
T83 |
2 |
|
T6 |
1 |
|
T106 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683229 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10329605 |
1 |
|
|
T13 |
15 |
|
T2 |
4 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4479504 |
1 |
|
|
T13 |
15 |
|
T2 |
2 |
|
T3 |
5 |
| auto[1] |
auto[0] |
auto[1] |
664663 |
1 |
|
|
T83 |
2 |
|
T6 |
1 |
|
T106 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4511321 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[1] |
674117 |
1 |
|
|
T106 |
1 |
|
T8 |
1 |
|
T35 |
2375 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661370 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10351464 |
1 |
|
|
T13 |
11 |
|
T15 |
5 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21663800 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1349034 |
1 |
|
|
T83 |
2 |
|
T6 |
2 |
|
T79 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12622061 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10390773 |
1 |
|
|
T13 |
26 |
|
T2 |
4 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4511986 |
1 |
|
|
T13 |
15 |
|
T2 |
2 |
|
T3 |
3 |
| auto[1] |
auto[0] |
auto[1] |
672200 |
1 |
|
|
T83 |
2 |
|
T6 |
2 |
|
T35 |
2318 |
| auto[1] |
auto[1] |
auto[0] |
4529753 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
3 |
| auto[1] |
auto[1] |
auto[1] |
676834 |
1 |
|
|
T79 |
1 |
|
T93 |
1 |
|
T35 |
2593 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12685993 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10326841 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T15 |
5 |