Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21668118 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
1344716 |
1 |
|
|
T6 |
2 |
|
T93 |
5 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12652557 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10360277 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4510820 |
1 |
|
|
T13 |
15 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
auto[0] |
auto[1] |
672901 |
1 |
|
|
T6 |
2 |
|
T93 |
5 |
|
T35 |
2525 |
| auto[1] |
auto[1] |
auto[0] |
4504741 |
1 |
|
|
T3 |
4 |
|
T73 |
3 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[1] |
671815 |
1 |
|
|
T80 |
1 |
|
T35 |
2274 |
|
T52 |
7179 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |