Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12719395 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
10293439 |
1 |
|
|
T13 |
30 |
|
T15 |
5 |
|
T2 |
2 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
18906760 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
4106074 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T73 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12673681 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
10339153 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3126698 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
6 |
auto[1] |
auto[0] |
auto[1] |
2061630 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
auto[1] |
auto[0] |
3106381 |
1 |
|
|
T13 |
11 |
|
T3 |
2 |
|
T73 |
2 |
auto[1] |
auto[1] |
auto[1] |
2044444 |
1 |
|
|
T73 |
1 |
|
T98 |
1 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |