Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12718096 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
10294738 |
1 |
|
|
T13 |
15 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21670028 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
1342806 |
1 |
|
|
T13 |
3 |
|
T77 |
1 |
|
T79 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12664380 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
auto[1] |
10348454 |
1 |
|
|
T13 |
11 |
|
T2 |
4 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4521127 |
1 |
|
|
T2 |
2 |
|
T3 |
5 |
|
T24 |
7 |
auto[1] |
auto[0] |
auto[1] |
675172 |
1 |
|
|
T77 |
1 |
|
T93 |
3 |
|
T35 |
2368 |
auto[1] |
auto[1] |
auto[0] |
4484521 |
1 |
|
|
T13 |
8 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
auto[1] |
auto[1] |
667634 |
1 |
|
|
T13 |
3 |
|
T79 |
1 |
|
T80 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |