Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12692888 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10319946 |
1 |
|
|
T15 |
5 |
|
T3 |
7 |
|
T17 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16751104 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
6261730 |
1 |
|
|
T12 |
2 |
|
T13 |
10 |
|
T3 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12632312 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10380522 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2058105 |
1 |
|
|
T12 |
2 |
|
T13 |
1 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3128054 |
1 |
|
|
T12 |
2 |
|
T13 |
10 |
|
T3 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2060687 |
1 |
|
|
T3 |
1 |
|
T24 |
1 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[1] |
3133676 |
1 |
|
|
T3 |
2 |
|
T24 |
3 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12727292 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10285542 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T15 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16798598 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
6214236 |
1 |
|
|
T12 |
4 |
|
T3 |
2 |
|
T73 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12696051 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10316783 |
1 |
|
|
T12 |
4 |
|
T3 |
3 |
|
T73 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2057470 |
1 |
|
|
T3 |
1 |
|
T73 |
2 |
|
T24 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3119136 |
1 |
|
|
T73 |
1 |
|
T24 |
1 |
|
T98 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2045077 |
1 |
|
|
T24 |
1 |
|
T25 |
1 |
|
T93 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3095100 |
1 |
|
|
T12 |
4 |
|
T3 |
2 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12663545 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10349289 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16816022 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
6196812 |
1 |
|
|
T12 |
2 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12731013 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
10281821 |
1 |
|
|
T11 |
1 |
|
T12 |
4 |
|
T2 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2037160 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T24 |
4 |
| auto[1] |
auto[0] |
auto[1] |
3083926 |
1 |
|
|
T12 |
2 |
|
T2 |
1 |
|
T3 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2047849 |
1 |
|
|
T3 |
1 |
|
T24 |
1 |
|
T98 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3112886 |
1 |
|
|
T2 |
1 |
|
T73 |
3 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12684149 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10328685 |
1 |
|
|
T12 |
4 |
|
T13 |
26 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16799896 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6212938 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12707213 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10305621 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2047642 |
1 |
|
|
T3 |
3 |
|
T24 |
1 |
|
T32 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3103320 |
1 |
|
|
T3 |
3 |
|
T73 |
3 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2045041 |
1 |
|
|
T3 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3109618 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12649729 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10363105 |
1 |
|
|
T12 |
4 |
|
T13 |
30 |
|
T15 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16806371 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6206463 |
1 |
|
|
T2 |
3 |
|
T24 |
6 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12700646 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10312188 |
1 |
|
|
T2 |
4 |
|
T3 |
3 |
|
T24 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2057774 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3109272 |
1 |
|
|
T2 |
1 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2047951 |
1 |
|
|
T24 |
1 |
|
T4 |
1 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3097191 |
1 |
|
|
T2 |
2 |
|
T24 |
2 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12696589 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10316245 |
1 |
|
|
T13 |
30 |
|
T15 |
3 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16778316 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6234518 |
1 |
|
|
T13 |
8 |
|
T3 |
3 |
|
T73 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12669694 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10343140 |
1 |
|
|
T13 |
11 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2062085 |
1 |
|
|
T2 |
1 |
|
T24 |
2 |
|
T38 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3117476 |
1 |
|
|
T3 |
2 |
|
T73 |
3 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2046537 |
1 |
|
|
T13 |
3 |
|
T5 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3117042 |
1 |
|
|
T13 |
8 |
|
T3 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12664463 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10348371 |
1 |
|
|
T12 |
4 |
|
T13 |
30 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16801189 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6211645 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12706347 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10306487 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2046165 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3103261 |
1 |
|
|
T11 |
1 |
|
T2 |
2 |
|
T3 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2048677 |
1 |
|
|
T25 |
1 |
|
T29 |
1 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3108384 |
1 |
|
|
T13 |
11 |
|
T3 |
2 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12719395 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10293439 |
1 |
|
|
T13 |
30 |
|
T15 |
5 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16771899 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6240935 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12659817 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10353017 |
1 |
|
|
T13 |
11 |
|
T2 |
5 |
|
T3 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2064890 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T5 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3140756 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2047192 |
1 |
|
|
T2 |
2 |
|
T73 |
1 |
|
T98 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3100179 |
1 |
|
|
T13 |
11 |
|
T3 |
1 |
|
T73 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681073 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10331761 |
1 |
|
|
T13 |
15 |
|
T15 |
7 |
|
T3 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16782253 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6230581 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12668137 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10344697 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2061986 |
1 |
|
|
T3 |
3 |
|
T24 |
1 |
|
T25 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3125943 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2052130 |
1 |
|
|
T77 |
2 |
|
T29 |
1 |
|
T80 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3104638 |
1 |
|
|
T3 |
2 |
|
T24 |
3 |
|
T98 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661094 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10351740 |
1 |
|
|
T12 |
4 |
|
T13 |
19 |
|
T15 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16783216 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6229618 |
1 |
|
|
T11 |
1 |
|
T13 |
4 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12663668 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10349166 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2062993 |
1 |
|
|
T13 |
7 |
|
T3 |
3 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3121658 |
1 |
|
|
T11 |
1 |
|
T13 |
4 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2056555 |
1 |
|
|
T2 |
1 |
|
T25 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3107960 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T73 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12695729 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10317105 |
1 |
|
|
T13 |
26 |
|
T15 |
2 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764319 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6248515 |
1 |
|
|
T3 |
4 |
|
T24 |
6 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12645878 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10366956 |
1 |
|
|
T3 |
7 |
|
T24 |
6 |
|
T32 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2068720 |
1 |
|
|
T3 |
3 |
|
T25 |
2 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3143248 |
1 |
|
|
T3 |
4 |
|
T24 |
5 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2049721 |
1 |
|
|
T98 |
1 |
|
T77 |
1 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3105267 |
1 |
|
|
T24 |
1 |
|
T98 |
1 |
|
T77 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12665213 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10347621 |
1 |
|
|
T12 |
4 |
|
T13 |
26 |
|
T15 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16760268 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
6252566 |
1 |
|
|
T12 |
4 |
|
T13 |
2 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12643501 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10369333 |
1 |
|
|
T12 |
4 |
|
T13 |
4 |
|
T2 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2062894 |
1 |
|
|
T13 |
2 |
|
T3 |
2 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3130342 |
1 |
|
|
T13 |
2 |
|
T2 |
2 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2053873 |
1 |
|
|
T24 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3122224 |
1 |
|
|
T12 |
4 |
|
T3 |
1 |
|
T77 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12643265 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10369569 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16773750 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
6239084 |
1 |
|
|
T12 |
4 |
|
T3 |
4 |
|
T73 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12648563 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10364271 |
1 |
|
|
T12 |
4 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2052937 |
1 |
|
|
T3 |
3 |
|
T73 |
1 |
|
T24 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3120360 |
1 |
|
|
T3 |
3 |
|
T73 |
2 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2072250 |
1 |
|
|
T2 |
1 |
|
T24 |
2 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3118724 |
1 |
|
|
T12 |
4 |
|
T3 |
1 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12674607 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10338227 |
1 |
|
|
T13 |
11 |
|
T3 |
4 |
|
T17 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16809328 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6203506 |
1 |
|
|
T13 |
4 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12713545 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10299289 |
1 |
|
|
T13 |
4 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2041812 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T73 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3104924 |
1 |
|
|
T13 |
4 |
|
T2 |
2 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2053971 |
1 |
|
|
T24 |
1 |
|
T98 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3098582 |
1 |
|
|
T3 |
1 |
|
T24 |
1 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683224 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10329610 |
1 |
|
|
T13 |
11 |
|
T15 |
8 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16799850 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6212984 |
1 |
|
|
T13 |
9 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12699368 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10313466 |
1 |
|
|
T13 |
11 |
|
T2 |
3 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2052921 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3110457 |
1 |
|
|
T3 |
3 |
|
T24 |
2 |
|
T98 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2047561 |
1 |
|
|
T13 |
2 |
|
T77 |
1 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3102527 |
1 |
|
|
T13 |
9 |
|
T2 |
2 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |