Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12710856 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10301978 |
1 |
|
|
T13 |
4 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16786297 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
6226537 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12682133 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10330701 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2067881 |
1 |
|
|
T13 |
4 |
|
T3 |
1 |
|
T24 |
3 |
| auto[1] |
auto[0] |
auto[1] |
3135126 |
1 |
|
|
T12 |
4 |
|
T13 |
7 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2036283 |
1 |
|
|
T2 |
1 |
|
T73 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3091411 |
1 |
|
|
T13 |
4 |
|
T73 |
2 |
|
T24 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661138 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10351696 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16812457 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6200377 |
1 |
|
|
T13 |
3 |
|
T2 |
1 |
|
T3 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12706945 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10305889 |
1 |
|
|
T13 |
4 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2045353 |
1 |
|
|
T3 |
1 |
|
T73 |
2 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3097669 |
1 |
|
|
T3 |
4 |
|
T73 |
1 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2060159 |
1 |
|
|
T13 |
1 |
|
T25 |
2 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3102708 |
1 |
|
|
T13 |
3 |
|
T2 |
1 |
|
T3 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661370 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10351464 |
1 |
|
|
T13 |
11 |
|
T15 |
5 |
|
T2 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16807792 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
6205042 |
1 |
|
|
T12 |
2 |
|
T2 |
3 |
|
T3 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12713785 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10299049 |
1 |
|
|
T12 |
4 |
|
T2 |
3 |
|
T3 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2047125 |
1 |
|
|
T12 |
2 |
|
T3 |
1 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3101999 |
1 |
|
|
T12 |
2 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2046882 |
1 |
|
|
T3 |
3 |
|
T73 |
1 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3103043 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T73 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12685993 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10326841 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T15 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16758332 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
6254502 |
1 |
|
|
T12 |
2 |
|
T2 |
2 |
|
T3 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12631451 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10381383 |
1 |
|
|
T12 |
4 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2066000 |
1 |
|
|
T24 |
1 |
|
T78 |
2 |
|
T25 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3119027 |
1 |
|
|
T2 |
2 |
|
T3 |
4 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2060881 |
1 |
|
|
T12 |
2 |
|
T3 |
1 |
|
T73 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3135475 |
1 |
|
|
T12 |
2 |
|
T3 |
1 |
|
T73 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12718096 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10294738 |
1 |
|
|
T13 |
15 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16834735 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6178099 |
1 |
|
|
T13 |
1 |
|
T3 |
6 |
|
T73 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12738217 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10274617 |
1 |
|
|
T13 |
4 |
|
T2 |
1 |
|
T3 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2047753 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T73 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3081402 |
1 |
|
|
T3 |
3 |
|
T73 |
2 |
|
T24 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2048765 |
1 |
|
|
T13 |
3 |
|
T77 |
1 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3096697 |
1 |
|
|
T13 |
1 |
|
T3 |
3 |
|
T4 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12659038 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10353796 |
1 |
|
|
T13 |
15 |
|
T15 |
2 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16819260 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6193574 |
1 |
|
|
T13 |
1 |
|
T2 |
2 |
|
T3 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12730246 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10282588 |
1 |
|
|
T13 |
4 |
|
T2 |
2 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2046966 |
1 |
|
|
T3 |
1 |
|
T24 |
2 |
|
T32 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3084870 |
1 |
|
|
T3 |
4 |
|
T73 |
3 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2042048 |
1 |
|
|
T13 |
3 |
|
T98 |
1 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3108704 |
1 |
|
|
T13 |
1 |
|
T2 |
2 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12714901 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10297933 |
1 |
|
|
T12 |
4 |
|
T13 |
19 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16795456 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6217378 |
1 |
|
|
T13 |
4 |
|
T3 |
5 |
|
T73 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12694402 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10318432 |
1 |
|
|
T12 |
4 |
|
T13 |
4 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2056704 |
1 |
|
|
T29 |
2 |
|
T38 |
2 |
|
T6 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3117405 |
1 |
|
|
T3 |
2 |
|
T24 |
4 |
|
T98 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2044350 |
1 |
|
|
T12 |
4 |
|
T77 |
2 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3099973 |
1 |
|
|
T13 |
4 |
|
T3 |
3 |
|
T73 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12666687 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10346147 |
1 |
|
|
T13 |
15 |
|
T15 |
8 |
|
T3 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16807347 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6205487 |
1 |
|
|
T11 |
1 |
|
T13 |
12 |
|
T2 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12705141 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10307693 |
1 |
|
|
T11 |
1 |
|
T13 |
15 |
|
T2 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2049879 |
1 |
|
|
T13 |
3 |
|
T24 |
4 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3114188 |
1 |
|
|
T11 |
1 |
|
T13 |
12 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2052327 |
1 |
|
|
T98 |
1 |
|
T77 |
1 |
|
T38 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3091299 |
1 |
|
|
T3 |
1 |
|
T77 |
4 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12731667 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10281167 |
1 |
|
|
T13 |
4 |
|
T15 |
2 |
|
T3 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16750301 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
6262533 |
1 |
|
|
T12 |
2 |
|
T13 |
9 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12627789 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
10385045 |
1 |
|
|
T11 |
1 |
|
T12 |
4 |
|
T13 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2065276 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T13 |
6 |
| auto[1] |
auto[0] |
auto[1] |
3140272 |
1 |
|
|
T12 |
2 |
|
T13 |
5 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2057236 |
1 |
|
|
T38 |
1 |
|
T93 |
4 |
|
T10 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3122261 |
1 |
|
|
T13 |
4 |
|
T3 |
1 |
|
T77 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12642821 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10370013 |
1 |
|
|
T12 |
4 |
|
T13 |
15 |
|
T15 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16770235 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6242599 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12656785 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10356049 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2054956 |
1 |
|
|
T24 |
2 |
|
T38 |
3 |
|
T6 |
5 |
| auto[1] |
auto[0] |
auto[1] |
3109651 |
1 |
|
|
T11 |
1 |
|
T13 |
11 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2058494 |
1 |
|
|
T24 |
1 |
|
T5 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3132948 |
1 |
|
|
T3 |
3 |
|
T24 |
2 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678496 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10334338 |
1 |
|
|
T13 |
11 |
|
T15 |
2 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16794489 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6218345 |
1 |
|
|
T13 |
1 |
|
T2 |
5 |
|
T3 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12702845 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10309989 |
1 |
|
|
T13 |
4 |
|
T2 |
5 |
|
T3 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2042616 |
1 |
|
|
T13 |
3 |
|
T24 |
1 |
|
T25 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3105203 |
1 |
|
|
T13 |
1 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2049028 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3113142 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T73 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12668655 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10344179 |
1 |
|
|
T13 |
30 |
|
T15 |
5 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16756636 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6256198 |
1 |
|
|
T11 |
1 |
|
T2 |
2 |
|
T3 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12640810 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10372024 |
1 |
|
|
T11 |
1 |
|
T2 |
2 |
|
T3 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2054930 |
1 |
|
|
T3 |
1 |
|
T24 |
2 |
|
T25 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3120345 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T3 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2060896 |
1 |
|
|
T98 |
1 |
|
T77 |
2 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3135853 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12711988 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10300846 |
1 |
|
|
T15 |
3 |
|
T2 |
4 |
|
T3 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16783537 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
6229297 |
1 |
|
|
T12 |
4 |
|
T13 |
2 |
|
T2 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12676097 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10336737 |
1 |
|
|
T12 |
4 |
|
T13 |
4 |
|
T2 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2066624 |
1 |
|
|
T13 |
2 |
|
T3 |
2 |
|
T24 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3144180 |
1 |
|
|
T12 |
4 |
|
T13 |
2 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2040816 |
1 |
|
|
T3 |
1 |
|
T77 |
4 |
|
T93 |
2 |
| auto[1] |
auto[1] |
auto[1] |
3085117 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12661990 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10350844 |
1 |
|
|
T13 |
15 |
|
T15 |
5 |
|
T3 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16786156 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
6226678 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12671646 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
5 |
| auto[1] |
10341188 |
1 |
|
|
T13 |
15 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2052121 |
1 |
|
|
T13 |
4 |
|
T3 |
1 |
|
T24 |
1 |
| auto[1] |
auto[0] |
auto[1] |
3097429 |
1 |
|
|
T13 |
11 |
|
T2 |
2 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2062389 |
1 |
|
|
T24 |
2 |
|
T77 |
1 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3129249 |
1 |
|
|
T77 |
3 |
|
T5 |
2 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681097 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T12 |
1 |
| auto[1] |
10331737 |
1 |
|
|
T12 |
4 |
|
T13 |
11 |
|
T2 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16814818 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
6198016 |
1 |
|
|
T11 |
1 |
|
T13 |
12 |
|
T2 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12715396 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
5 |
| auto[1] |
10297438 |
1 |
|
|
T11 |
1 |
|
T13 |
15 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2050430 |
1 |
|
|
T13 |
3 |
|
T3 |
1 |
|
T24 |
2 |
| auto[1] |
auto[0] |
auto[1] |
3095665 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2048992 |
1 |
|
|
T3 |
1 |
|
T77 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
3102351 |
1 |
|
|
T13 |
11 |
|
T2 |
3 |
|
T3 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |