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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 100.00


Total test records in report: 970
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T765 /workspace/coverage/default/37.gpio_intr_rand_pgm.415424568 Feb 04 02:43:56 PM PST 24 Feb 04 02:44:05 PM PST 24 198372954 ps
T766 /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.862505762 Feb 04 02:44:02 PM PST 24 Feb 04 02:44:23 PM PST 24 106778050 ps
T767 /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3737494152 Feb 04 02:42:56 PM PST 24 Feb 04 02:43:04 PM PST 24 79014918 ps
T768 /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2032656214 Feb 04 02:43:25 PM PST 24 Feb 04 02:43:33 PM PST 24 358600226 ps
T769 /workspace/coverage/default/8.gpio_stress_all.1362830943 Feb 04 02:42:33 PM PST 24 Feb 04 02:46:15 PM PST 24 32877536749 ps
T770 /workspace/coverage/default/29.gpio_filter_stress.4286447464 Feb 04 02:43:48 PM PST 24 Feb 04 02:44:22 PM PST 24 8116523622 ps
T771 /workspace/coverage/default/27.gpio_rand_intr_trigger.4263790953 Feb 04 02:43:37 PM PST 24 Feb 04 02:43:41 PM PST 24 57844359 ps
T772 /workspace/coverage/default/26.gpio_smoke.260525917 Feb 04 02:43:26 PM PST 24 Feb 04 02:43:33 PM PST 24 48547439 ps
T773 /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.939420268 Feb 04 02:42:17 PM PST 24 Feb 04 02:42:24 PM PST 24 129439914 ps
T774 /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.765140559 Feb 04 02:42:49 PM PST 24 Feb 04 02:42:52 PM PST 24 312218908 ps
T775 /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.112755774 Feb 04 02:42:14 PM PST 24 Feb 04 02:42:19 PM PST 24 60780229 ps
T776 /workspace/coverage/default/5.gpio_alert_test.3959066663 Feb 04 02:42:22 PM PST 24 Feb 04 02:42:27 PM PST 24 34620322 ps
T777 /workspace/coverage/default/34.gpio_full_random.127051694 Feb 04 02:43:50 PM PST 24 Feb 04 02:44:00 PM PST 24 112349927 ps
T778 /workspace/coverage/default/41.gpio_random_dout_din.3253478377 Feb 04 02:44:16 PM PST 24 Feb 04 02:44:24 PM PST 24 338300072 ps
T779 /workspace/coverage/default/11.gpio_smoke.2455271793 Feb 04 02:42:52 PM PST 24 Feb 04 02:42:56 PM PST 24 58906793 ps
T780 /workspace/coverage/default/10.gpio_filter_stress.2016540867 Feb 04 02:42:56 PM PST 24 Feb 04 02:43:12 PM PST 24 1459956686 ps
T781 /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.830073134 Feb 04 02:44:41 PM PST 24 Feb 04 02:44:48 PM PST 24 78456618 ps
T782 /workspace/coverage/default/32.gpio_filter_stress.974708329 Feb 04 02:43:50 PM PST 24 Feb 04 02:44:20 PM PST 24 4965749564 ps
T783 /workspace/coverage/default/12.gpio_filter_stress.1624475728 Feb 04 02:42:51 PM PST 24 Feb 04 02:43:15 PM PST 24 925209444 ps
T784 /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2031523505 Feb 04 02:43:29 PM PST 24 Feb 04 02:43:37 PM PST 24 319213374 ps
T785 /workspace/coverage/default/19.gpio_filter_stress.3321543941 Feb 04 02:43:12 PM PST 24 Feb 04 02:43:44 PM PST 24 770980930 ps
T786 /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.679627266 Feb 04 02:43:09 PM PST 24 Feb 04 02:43:24 PM PST 24 400519459 ps
T787 /workspace/coverage/default/29.gpio_full_random.2058891806 Feb 04 02:43:41 PM PST 24 Feb 04 02:43:44 PM PST 24 76037413 ps
T788 /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3078880175 Feb 04 02:43:03 PM PST 24 Feb 04 02:43:12 PM PST 24 49751579 ps
T789 /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2976500836 Feb 04 02:42:46 PM PST 24 Feb 04 02:42:48 PM PST 24 38357079 ps
T790 /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2240754773 Feb 04 02:44:02 PM PST 24 Feb 04 02:44:19 PM PST 24 57255704 ps
T791 /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.619874275 Feb 04 02:42:07 PM PST 24 Feb 04 02:42:16 PM PST 24 432281145 ps
T792 /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.379197052 Feb 04 02:44:59 PM PST 24 Feb 04 02:50:30 PM PST 24 11549017418 ps
T793 /workspace/coverage/default/0.gpio_intr_rand_pgm.2759043789 Feb 04 02:42:13 PM PST 24 Feb 04 02:42:17 PM PST 24 176211164 ps
T794 /workspace/coverage/default/21.gpio_full_random.401353935 Feb 04 02:43:11 PM PST 24 Feb 04 02:43:22 PM PST 24 129312760 ps
T795 /workspace/coverage/default/45.gpio_random_dout_din.3552271706 Feb 04 02:44:56 PM PST 24 Feb 04 02:45:18 PM PST 24 37502869 ps
T796 /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.101555664 Feb 04 02:42:52 PM PST 24 Feb 04 02:42:57 PM PST 24 248114278 ps
T797 /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3510347088 Feb 04 02:43:46 PM PST 24 Feb 04 02:43:51 PM PST 24 34141585 ps
T798 /workspace/coverage/default/7.gpio_filter_stress.2953627666 Feb 04 02:42:33 PM PST 24 Feb 04 02:42:54 PM PST 24 332218307 ps
T799 /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4165003204 Feb 04 02:42:16 PM PST 24 Feb 04 02:42:22 PM PST 24 139361920 ps
T800 /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4247405229 Feb 04 02:43:28 PM PST 24 Feb 04 02:43:35 PM PST 24 307763211 ps
T801 /workspace/coverage/default/2.gpio_smoke.2383904557 Feb 04 02:42:12 PM PST 24 Feb 04 02:42:16 PM PST 24 405397468 ps
T802 /workspace/coverage/default/13.gpio_alert_test.3773713267 Feb 04 02:42:56 PM PST 24 Feb 04 02:43:02 PM PST 24 11552364 ps
T803 /workspace/coverage/default/30.gpio_filter_stress.332831784 Feb 04 02:43:50 PM PST 24 Feb 04 02:44:27 PM PST 24 6619840175 ps
T804 /workspace/coverage/default/42.gpio_rand_intr_trigger.768486204 Feb 04 02:44:40 PM PST 24 Feb 04 02:44:50 PM PST 24 527477433 ps
T805 /workspace/coverage/default/7.gpio_random_dout_din.1772357335 Feb 04 02:42:40 PM PST 24 Feb 04 02:42:45 PM PST 24 44416190 ps
T806 /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2860485656 Feb 04 02:42:54 PM PST 24 Feb 04 02:43:02 PM PST 24 84469726 ps
T807 /workspace/coverage/default/1.gpio_rand_intr_trigger.3213443112 Feb 04 02:42:12 PM PST 24 Feb 04 02:42:15 PM PST 24 116788984 ps
T808 /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.901488193 Feb 04 02:44:02 PM PST 24 Feb 04 02:44:19 PM PST 24 64122690 ps
T809 /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1689346424 Feb 04 02:43:13 PM PST 24 Feb 04 03:15:52 PM PST 24 287117485765 ps
T810 /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.4066982264 Feb 04 02:42:57 PM PST 24 Feb 04 02:43:06 PM PST 24 71429472 ps
T811 /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1748151053 Feb 04 02:42:29 PM PST 24 Feb 04 02:42:32 PM PST 24 158552248 ps
T812 /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1152389220 Feb 04 02:42:06 PM PST 24 Feb 04 02:42:10 PM PST 24 49914029 ps
T813 /workspace/coverage/default/36.gpio_filter_stress.3170875473 Feb 04 02:44:02 PM PST 24 Feb 04 02:44:24 PM PST 24 515356781 ps
T814 /workspace/coverage/default/27.gpio_smoke.644974862 Feb 04 02:43:24 PM PST 24 Feb 04 02:43:32 PM PST 24 870387613 ps
T815 /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3316518847 Feb 04 02:43:58 PM PST 24 Feb 04 02:44:11 PM PST 24 93764831 ps
T816 /workspace/coverage/default/39.gpio_random_dout_din.4112111931 Feb 04 02:43:59 PM PST 24 Feb 04 02:44:11 PM PST 24 120888358 ps
T817 /workspace/coverage/default/20.gpio_stress_all.285929343 Feb 04 02:43:10 PM PST 24 Feb 04 02:45:26 PM PST 24 21357762058 ps
T818 /workspace/coverage/default/18.gpio_filter_stress.2153100881 Feb 04 02:43:12 PM PST 24 Feb 04 02:43:46 PM PST 24 687615991 ps
T819 /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.574337206 Feb 04 02:43:16 PM PST 24 Feb 04 02:43:27 PM PST 24 251473882 ps
T820 /workspace/coverage/default/42.gpio_alert_test.1207741527 Feb 04 02:44:36 PM PST 24 Feb 04 02:44:40 PM PST 24 12608206 ps
T821 /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1198170087 Feb 04 02:44:55 PM PST 24 Feb 04 03:09:47 PM PST 24 315724317325 ps
T822 /workspace/coverage/default/45.gpio_full_random.3266910062 Feb 04 02:44:54 PM PST 24 Feb 04 02:45:17 PM PST 24 187333505 ps
T823 /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.568165966 Feb 04 02:42:19 PM PST 24 Feb 04 02:42:23 PM PST 24 92460800 ps
T824 /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1003385577 Feb 04 02:44:15 PM PST 24 Feb 04 02:44:29 PM PST 24 135681597 ps
T825 /workspace/coverage/default/23.gpio_intr_rand_pgm.3039780009 Feb 04 02:43:26 PM PST 24 Feb 04 02:43:33 PM PST 24 180945544 ps
T826 /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2254397215 Feb 04 02:44:56 PM PST 24 Feb 04 02:45:18 PM PST 24 618038242 ps
T827 /workspace/coverage/default/21.gpio_filter_stress.110908688 Feb 04 02:43:09 PM PST 24 Feb 04 02:43:28 PM PST 24 1293248227 ps
T828 /workspace/coverage/default/28.gpio_stress_all.2058408367 Feb 04 02:43:45 PM PST 24 Feb 04 02:44:12 PM PST 24 1656848894 ps
T829 /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3065616743 Feb 04 02:44:23 PM PST 24 Feb 04 02:44:28 PM PST 24 299372770 ps
T830 /workspace/coverage/default/2.gpio_alert_test.2671082108 Feb 04 02:42:21 PM PST 24 Feb 04 02:42:25 PM PST 24 27030246 ps
T831 /workspace/coverage/default/32.gpio_random_dout_din.167890905 Feb 04 02:43:46 PM PST 24 Feb 04 02:43:52 PM PST 24 82620211 ps
T832 /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3859084265 Feb 04 02:43:02 PM PST 24 Feb 04 03:13:46 PM PST 24 68603642039 ps
T833 /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3610976182 Feb 04 02:43:55 PM PST 24 Feb 04 02:44:04 PM PST 24 26171516 ps
T84 /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2518807921 Feb 04 02:43:07 PM PST 24 Feb 04 03:11:21 PM PST 24 114790909034 ps
T834 /workspace/coverage/default/43.gpio_smoke.3377963365 Feb 04 02:44:19 PM PST 24 Feb 04 02:44:26 PM PST 24 236178799 ps
T835 /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.695692500 Feb 04 02:42:13 PM PST 24 Feb 04 02:42:16 PM PST 24 21643554 ps
T836 /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2594580316 Feb 04 02:42:19 PM PST 24 Feb 04 02:42:26 PM PST 24 145845311 ps
T837 /workspace/coverage/default/46.gpio_smoke.1710013049 Feb 04 02:44:56 PM PST 24 Feb 04 02:45:18 PM PST 24 70057867 ps
T838 /workspace/coverage/default/25.gpio_filter_stress.2088123579 Feb 04 02:43:28 PM PST 24 Feb 04 02:43:57 PM PST 24 1778055259 ps
T839 /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3484225594 Feb 04 02:44:47 PM PST 24 Feb 04 02:45:03 PM PST 24 179335465 ps
T840 /workspace/coverage/default/38.gpio_random_dout_din.242836675 Feb 04 02:44:00 PM PST 24 Feb 04 02:44:11 PM PST 24 126162437 ps
T841 /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1832309088 Feb 04 02:42:35 PM PST 24 Feb 04 02:42:38 PM PST 24 34465871 ps
T842 /workspace/coverage/default/19.gpio_stress_all.592561570 Feb 04 02:43:12 PM PST 24 Feb 04 02:45:03 PM PST 24 35152448042 ps
T843 /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.338123757 Feb 04 02:42:21 PM PST 24 Feb 04 02:42:26 PM PST 24 31549052 ps
T844 /workspace/coverage/default/37.gpio_stress_all.965435240 Feb 04 02:44:04 PM PST 24 Feb 04 02:47:05 PM PST 24 14872306856 ps
T845 /workspace/coverage/default/23.gpio_alert_test.4185513554 Feb 04 02:43:27 PM PST 24 Feb 04 02:43:33 PM PST 24 14669612 ps
T846 /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2120174831 Feb 04 02:45:00 PM PST 24 Feb 04 02:45:24 PM PST 24 48146026 ps
T847 /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1837799632 Feb 04 02:44:20 PM PST 24 Feb 04 02:58:59 PM PST 24 92508145663 ps
T848 /workspace/coverage/default/47.gpio_smoke.478209075 Feb 04 02:44:54 PM PST 24 Feb 04 02:45:17 PM PST 24 265220670 ps
T849 /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2659098010 Feb 04 02:42:22 PM PST 24 Feb 04 02:42:27 PM PST 24 268724407 ps
T850 /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3025190954 Feb 04 02:44:29 PM PST 24 Feb 04 03:00:21 PM PST 24 77545326115 ps
T851 /workspace/coverage/default/31.gpio_random_dout_din.2020590643 Feb 04 02:43:46 PM PST 24 Feb 04 02:43:51 PM PST 24 34526078 ps
T852 /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2602393431 Feb 04 02:43:45 PM PST 24 Feb 04 02:43:50 PM PST 24 40776638 ps
T853 /workspace/coverage/default/19.gpio_alert_test.1920714733 Feb 04 02:43:12 PM PST 24 Feb 04 02:43:24 PM PST 24 12863509 ps
T854 /workspace/coverage/default/32.gpio_stress_all.1406900738 Feb 04 02:44:04 PM PST 24 Feb 04 02:44:40 PM PST 24 3532479078 ps
T855 /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2539923489 Feb 04 02:43:42 PM PST 24 Feb 04 02:43:46 PM PST 24 32488392 ps
T856 /workspace/coverage/default/20.gpio_random_dout_din.400584800 Feb 04 02:43:11 PM PST 24 Feb 04 02:43:22 PM PST 24 30706206 ps
T857 /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.900320965 Feb 04 02:42:34 PM PST 24 Feb 04 02:42:37 PM PST 24 45348515 ps
T858 /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3415295119 Feb 04 02:44:41 PM PST 24 Feb 04 03:07:40 PM PST 24 97884836784 ps
T859 /workspace/coverage/default/10.gpio_stress_all.1624507274 Feb 04 02:42:52 PM PST 24 Feb 04 02:45:28 PM PST 24 10647155902 ps
T860 /workspace/coverage/default/19.gpio_smoke.3095722752 Feb 04 02:43:12 PM PST 24 Feb 04 02:43:24 PM PST 24 93032689 ps
T861 /workspace/coverage/default/12.gpio_full_random.1777440895 Feb 04 02:42:53 PM PST 24 Feb 04 02:42:57 PM PST 24 292078570 ps
T862 /workspace/coverage/default/38.gpio_alert_test.104266089 Feb 04 02:44:03 PM PST 24 Feb 04 02:44:19 PM PST 24 17104102 ps
T863 /workspace/coverage/default/46.gpio_stress_all.3160879141 Feb 04 02:44:29 PM PST 24 Feb 04 02:44:50 PM PST 24 2277035161 ps
T864 /workspace/coverage/default/27.gpio_filter_stress.1270235230 Feb 04 02:43:44 PM PST 24 Feb 04 02:43:54 PM PST 24 800045395 ps
T865 /workspace/coverage/default/35.gpio_intr_rand_pgm.1033786967 Feb 04 02:43:50 PM PST 24 Feb 04 02:43:59 PM PST 24 164850377 ps
T866 /workspace/coverage/default/47.gpio_intr_rand_pgm.3848950181 Feb 04 02:44:40 PM PST 24 Feb 04 02:44:49 PM PST 24 55406819 ps
T867 /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1481734952 Feb 04 02:43:13 PM PST 24 Feb 04 02:43:26 PM PST 24 79473997 ps
T868 /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1973806967 Feb 04 02:43:42 PM PST 24 Feb 04 02:43:45 PM PST 24 96922904 ps
T869 /workspace/coverage/default/20.gpio_rand_intr_trigger.3631432584 Feb 04 02:43:10 PM PST 24 Feb 04 02:43:23 PM PST 24 85261543 ps
T870 /workspace/coverage/default/14.gpio_smoke.3925203107 Feb 04 02:42:57 PM PST 24 Feb 04 02:43:04 PM PST 24 249283428 ps
T871 /workspace/coverage/default/9.gpio_alert_test.3108102379 Feb 04 02:42:49 PM PST 24 Feb 04 02:42:52 PM PST 24 15846813 ps
T872 /workspace/coverage/default/17.gpio_random_dout_din.834255904 Feb 04 02:43:01 PM PST 24 Feb 04 02:43:10 PM PST 24 121214182 ps
T873 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3453416680 Feb 04 02:43:41 PM PST 24 Feb 04 02:43:45 PM PST 24 35351097 ps
T874 /workspace/coverage/default/24.gpio_filter_stress.1759295150 Feb 04 02:43:30 PM PST 24 Feb 04 02:43:59 PM PST 24 11843544624 ps
T875 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2597622477 Feb 04 02:44:47 PM PST 24 Feb 04 02:45:02 PM PST 24 218533064 ps
T876 /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.439436593 Feb 04 02:42:57 PM PST 24 Feb 04 02:43:04 PM PST 24 65406555 ps
T877 /workspace/coverage/default/13.gpio_stress_all.3610566942 Feb 04 02:42:50 PM PST 24 Feb 04 02:44:39 PM PST 24 41887756809 ps
T878 /workspace/coverage/default/9.gpio_full_random.2696961630 Feb 04 02:42:48 PM PST 24 Feb 04 02:42:51 PM PST 24 88706538 ps
T879 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3242182625 Feb 04 02:43:01 PM PST 24 Feb 04 02:43:09 PM PST 24 113655330 ps
T880 /workspace/coverage/default/24.gpio_full_random.3512830300 Feb 04 02:43:26 PM PST 24 Feb 04 02:43:32 PM PST 24 54910462 ps
T881 /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.184303317 Feb 04 02:44:05 PM PST 24 Feb 04 02:44:25 PM PST 24 1355555621 ps
T882 /workspace/coverage/default/37.gpio_random_dout_din.2112086786 Feb 04 02:43:58 PM PST 24 Feb 04 02:44:09 PM PST 24 22196455 ps
T883 /workspace/coverage/default/43.gpio_full_random.99796707 Feb 04 02:44:49 PM PST 24 Feb 04 02:45:10 PM PST 24 64085352 ps
T884 /workspace/coverage/default/8.gpio_rand_intr_trigger.3495968178 Feb 04 02:42:28 PM PST 24 Feb 04 02:42:33 PM PST 24 893928255 ps
T885 /workspace/coverage/default/6.gpio_smoke.3092839611 Feb 04 02:42:35 PM PST 24 Feb 04 02:42:38 PM PST 24 42800673 ps
T886 /workspace/coverage/default/44.gpio_rand_intr_trigger.4107007569 Feb 04 02:44:54 PM PST 24 Feb 04 02:45:19 PM PST 24 212960905 ps
T887 /workspace/coverage/default/14.gpio_random_dout_din.2612350584 Feb 04 02:42:53 PM PST 24 Feb 04 02:42:57 PM PST 24 34355084 ps
T888 /workspace/coverage/default/14.gpio_intr_rand_pgm.1483429640 Feb 04 02:42:54 PM PST 24 Feb 04 02:42:59 PM PST 24 164364887 ps
T40 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.32245185 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:07 PM PST 24 309347502 ps
T889 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.959357308 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:04 PM PST 24 95779863 ps
T890 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1991164400 Feb 04 12:44:16 PM PST 24 Feb 04 12:44:18 PM PST 24 91459545 ps
T891 /workspace/coverage/cover_reg_top/49.gpio_intr_test.643452658 Feb 04 12:44:21 PM PST 24 Feb 04 12:44:23 PM PST 24 19036726 ps
T892 /workspace/coverage/cover_reg_top/46.gpio_intr_test.894531535 Feb 04 12:44:19 PM PST 24 Feb 04 12:44:20 PM PST 24 29648188 ps
T893 /workspace/coverage/cover_reg_top/20.gpio_intr_test.799130969 Feb 04 12:44:19 PM PST 24 Feb 04 12:44:21 PM PST 24 45697317 ps
T894 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2305031499 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:05 PM PST 24 24065283 ps
T895 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3684440857 Feb 04 12:42:59 PM PST 24 Feb 04 12:43:04 PM PST 24 319716927 ps
T896 /workspace/coverage/cover_reg_top/18.gpio_intr_test.67252830 Feb 04 12:43:40 PM PST 24 Feb 04 12:43:42 PM PST 24 85485601 ps
T88 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3857855133 Feb 04 12:42:57 PM PST 24 Feb 04 12:43:00 PM PST 24 57401384 ps
T85 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.772426738 Feb 04 12:43:45 PM PST 24 Feb 04 12:43:46 PM PST 24 35856993 ps
T897 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2447417782 Feb 04 12:44:17 PM PST 24 Feb 04 12:44:19 PM PST 24 15454615 ps
T96 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3761748782 Feb 04 12:43:04 PM PST 24 Feb 04 12:43:07 PM PST 24 41891302 ps
T898 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.243526841 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:06 PM PST 24 42982529 ps
T899 /workspace/coverage/cover_reg_top/32.gpio_intr_test.774196163 Feb 04 12:44:22 PM PST 24 Feb 04 12:44:24 PM PST 24 39182135 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2227271324 Feb 04 12:42:57 PM PST 24 Feb 04 12:42:59 PM PST 24 29952657 ps
T900 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2234134054 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:04 PM PST 24 46070002 ps
T901 /workspace/coverage/cover_reg_top/14.gpio_intr_test.821433463 Feb 04 12:43:15 PM PST 24 Feb 04 12:43:18 PM PST 24 28546688 ps
T902 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1519385481 Feb 04 12:42:57 PM PST 24 Feb 04 12:42:59 PM PST 24 12174604 ps
T903 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2298752693 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:05 PM PST 24 38016574 ps
T904 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1358379718 Feb 04 12:43:04 PM PST 24 Feb 04 12:43:08 PM PST 24 743877078 ps
T905 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4174824557 Feb 04 12:44:14 PM PST 24 Feb 04 12:44:17 PM PST 24 38826759 ps
T906 /workspace/coverage/cover_reg_top/44.gpio_intr_test.59425566 Feb 04 12:44:34 PM PST 24 Feb 04 12:44:38 PM PST 24 13864486 ps
T907 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.582890316 Feb 04 12:42:56 PM PST 24 Feb 04 12:42:59 PM PST 24 108454124 ps
T908 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2742956266 Feb 04 12:44:13 PM PST 24 Feb 04 12:44:17 PM PST 24 25929326 ps
T909 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.654855836 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:05 PM PST 24 13216383 ps
T910 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2949088141 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:03 PM PST 24 35157806 ps
T911 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3433029407 Feb 04 12:44:34 PM PST 24 Feb 04 12:44:40 PM PST 24 298419342 ps
T97 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2932320345 Feb 04 12:43:09 PM PST 24 Feb 04 12:43:10 PM PST 24 140454822 ps
T31 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3778903925 Feb 04 12:42:58 PM PST 24 Feb 04 12:43:01 PM PST 24 132544569 ps
T912 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1051269693 Feb 04 12:44:25 PM PST 24 Feb 04 12:44:26 PM PST 24 62291686 ps
T913 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1179498564 Feb 04 12:44:25 PM PST 24 Feb 04 12:44:27 PM PST 24 42533203 ps
T914 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3609613703 Feb 04 12:43:08 PM PST 24 Feb 04 12:43:10 PM PST 24 160084853 ps
T915 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1586868981 Feb 04 12:44:19 PM PST 24 Feb 04 12:44:21 PM PST 24 25121271 ps
T916 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.442906729 Feb 04 12:43:08 PM PST 24 Feb 04 12:43:12 PM PST 24 57648949 ps
T917 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2262218279 Feb 04 12:43:18 PM PST 24 Feb 04 12:43:24 PM PST 24 17135010 ps
T918 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4154648493 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:04 PM PST 24 173672374 ps
T919 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3814237989 Feb 04 12:43:25 PM PST 24 Feb 04 12:43:27 PM PST 24 35578946 ps
T920 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1930373970 Feb 04 12:42:57 PM PST 24 Feb 04 12:43:00 PM PST 24 227205126 ps
T921 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1921581779 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:07 PM PST 24 221018928 ps
T922 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.630677538 Feb 04 12:42:56 PM PST 24 Feb 04 12:42:58 PM PST 24 281890638 ps
T923 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1842494670 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:04 PM PST 24 76219778 ps
T924 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3030764387 Feb 04 12:42:55 PM PST 24 Feb 04 12:42:58 PM PST 24 12867309 ps
T925 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3478227570 Feb 04 12:43:20 PM PST 24 Feb 04 12:43:24 PM PST 24 13750034 ps
T926 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3130441355 Feb 04 12:43:15 PM PST 24 Feb 04 12:43:18 PM PST 24 40738397 ps
T927 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4194488953 Feb 04 12:43:05 PM PST 24 Feb 04 12:43:09 PM PST 24 49396790 ps
T87 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.194629628 Feb 04 12:42:55 PM PST 24 Feb 04 12:42:58 PM PST 24 209210166 ps
T928 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1308062240 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:04 PM PST 24 78769076 ps
T929 /workspace/coverage/cover_reg_top/4.gpio_intr_test.889442868 Feb 04 12:42:56 PM PST 24 Feb 04 12:42:58 PM PST 24 17784876 ps
T930 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1341212140 Feb 04 12:44:26 PM PST 24 Feb 04 12:44:27 PM PST 24 128988544 ps
T931 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1450540005 Feb 04 12:43:05 PM PST 24 Feb 04 12:43:08 PM PST 24 70040946 ps
T932 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4240925943 Feb 04 12:42:59 PM PST 24 Feb 04 12:43:01 PM PST 24 12958051 ps
T933 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3566634813 Feb 04 12:43:05 PM PST 24 Feb 04 12:43:08 PM PST 24 33771306 ps
T934 /workspace/coverage/cover_reg_top/39.gpio_intr_test.397988134 Feb 04 12:44:25 PM PST 24 Feb 04 12:44:26 PM PST 24 14436182 ps
T935 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.911685372 Feb 04 12:43:08 PM PST 24 Feb 04 12:43:12 PM PST 24 87910023 ps
T36 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1117867550 Feb 04 12:43:34 PM PST 24 Feb 04 12:43:36 PM PST 24 380766690 ps
T936 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1101846864 Feb 04 12:43:40 PM PST 24 Feb 04 12:43:43 PM PST 24 95872043 ps
T937 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.202274743 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:04 PM PST 24 63894465 ps
T938 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.776121229 Feb 04 12:42:59 PM PST 24 Feb 04 12:43:03 PM PST 24 68804117 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1867367632 Feb 04 12:43:09 PM PST 24 Feb 04 12:43:11 PM PST 24 11939445 ps
T939 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.959285751 Feb 04 12:43:04 PM PST 24 Feb 04 12:43:07 PM PST 24 72849836 ps
T940 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.535241773 Feb 04 12:43:04 PM PST 24 Feb 04 12:43:08 PM PST 24 792927527 ps
T941 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2619730879 Feb 04 12:43:15 PM PST 24 Feb 04 12:43:18 PM PST 24 187065270 ps
T942 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2628512550 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:04 PM PST 24 40007718 ps
T943 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1168024327 Feb 04 12:43:09 PM PST 24 Feb 04 12:43:13 PM PST 24 146110105 ps
T944 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3205955688 Feb 04 12:44:26 PM PST 24 Feb 04 12:44:29 PM PST 24 30765221 ps
T945 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2650320970 Feb 04 12:44:17 PM PST 24 Feb 04 12:44:19 PM PST 24 16987070 ps
T101 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1281943773 Feb 04 12:43:12 PM PST 24 Feb 04 12:43:17 PM PST 24 397413727 ps
T946 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3754595330 Feb 04 12:43:33 PM PST 24 Feb 04 12:43:36 PM PST 24 12776282 ps
T947 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1932181634 Feb 04 12:42:59 PM PST 24 Feb 04 12:43:03 PM PST 24 263430405 ps
T948 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.996315990 Feb 04 12:43:02 PM PST 24 Feb 04 12:43:06 PM PST 24 252507790 ps
T949 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.193323789 Feb 04 12:43:06 PM PST 24 Feb 04 12:43:08 PM PST 24 19072141 ps
T950 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3008761774 Feb 04 12:43:40 PM PST 24 Feb 04 12:43:44 PM PST 24 62777091 ps
T951 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3706622385 Feb 04 12:43:07 PM PST 24 Feb 04 12:43:09 PM PST 24 15123802 ps
T952 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3782195924 Feb 04 12:43:45 PM PST 24 Feb 04 12:43:46 PM PST 24 153054965 ps
T953 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1216866371 Feb 04 12:43:12 PM PST 24 Feb 04 12:43:15 PM PST 24 98942631 ps
T954 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3121622618 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:05 PM PST 24 47830506 ps
T955 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1935139886 Feb 04 12:42:55 PM PST 24 Feb 04 12:42:59 PM PST 24 46503232 ps
T956 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3869186238 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:06 PM PST 24 24044380 ps
T957 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3418608497 Feb 04 12:43:10 PM PST 24 Feb 04 12:43:12 PM PST 24 67613164 ps
T958 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2939764603 Feb 04 12:43:03 PM PST 24 Feb 04 12:43:07 PM PST 24 354288793 ps
T959 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1454760442 Feb 04 12:43:07 PM PST 24 Feb 04 12:43:09 PM PST 24 20042406 ps
T960 /workspace/coverage/cover_reg_top/7.gpio_intr_test.125681105 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:03 PM PST 24 16327762 ps
T961 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2055913557 Feb 04 12:44:24 PM PST 24 Feb 04 12:44:26 PM PST 24 33851301 ps
T962 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3959136521 Feb 04 12:43:47 PM PST 24 Feb 04 12:43:49 PM PST 24 128510326 ps
T963 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1783032728 Feb 04 12:43:40 PM PST 24 Feb 04 12:43:42 PM PST 24 76575643 ps
T964 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3513267191 Feb 04 12:43:05 PM PST 24 Feb 04 12:43:08 PM PST 24 13129891 ps
T965 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1162995299 Feb 04 12:43:33 PM PST 24 Feb 04 12:43:36 PM PST 24 18969948 ps
T966 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1192008158 Feb 04 12:43:45 PM PST 24 Feb 04 12:43:47 PM PST 24 93170573 ps
T967 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3337797352 Feb 04 12:44:32 PM PST 24 Feb 04 12:44:34 PM PST 24 42404681 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4188232443 Feb 04 12:43:00 PM PST 24 Feb 04 12:43:03 PM PST 24 50472086 ps
T968 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1717612500 Feb 04 12:43:15 PM PST 24 Feb 04 12:43:18 PM PST 24 23812003 ps
T969 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.857874395 Feb 04 12:43:35 PM PST 24 Feb 04 12:43:37 PM PST 24 66161010 ps
T91 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2847351311 Feb 04 12:43:01 PM PST 24 Feb 04 12:43:05 PM PST 24 504461714 ps
T970 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2867286937 Feb 04 12:43:21 PM PST 24 Feb 04 12:43:24 PM PST 24 16331957 ps

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1523936200
Short name T3
Test name
Test status
Simulation time 601796287 ps
CPU time 1.14 seconds
Started Feb 04 12:43:12 PM PST 24
Finished Feb 04 12:43:15 PM PST 24
Peak memory 197652 kb
Host smart-a0d02803-2893-4dff-a3ed-a77bd62c9fb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523936200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1523936200
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2982374395
Short name T43
Test name
Test status
Simulation time 135320058 ps
CPU time 1.29 seconds
Started Feb 04 04:16:39 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 196488 kb
Host smart-cb9a583b-da90-41c1-828e-b2315e3313ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2982374395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2982374395
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1792018856
Short name T45
Test name
Test status
Simulation time 117361338 ps
CPU time 1.36 seconds
Started Feb 04 02:43:04 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 197740 kb
Host smart-93bfb628-2101-4c6e-8a50-8bd967461341
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792018856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1792018856
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2181308303
Short name T52
Test name
Test status
Simulation time 652816177717 ps
CPU time 1136.76 seconds
Started Feb 04 02:43:58 PM PST 24
Finished Feb 04 03:03:06 PM PST 24
Peak memory 206228 kb
Host smart-5765a557-c6c4-43e3-8549-ce523b7bd9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2181308303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2181308303
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.244146782
Short name T16
Test name
Test status
Simulation time 49573289 ps
CPU time 2.41 seconds
Started Feb 04 12:43:10 PM PST 24
Finished Feb 04 12:43:13 PM PST 24
Peak memory 197864 kb
Host smart-18effccb-4a9b-4784-82e8-76b1187ed0db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244146782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.244146782
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2084121443
Short name T5
Test name
Test status
Simulation time 37470087 ps
CPU time 0.85 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 195932 kb
Host smart-e0ebac0c-9ece-43ba-a518-d18855bbe600
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084121443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2084121443
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1048537225
Short name T17
Test name
Test status
Simulation time 19393519 ps
CPU time 0.62 seconds
Started Feb 04 12:44:25 PM PST 24
Finished Feb 04 12:44:27 PM PST 24
Peak memory 193612 kb
Host smart-ecb60975-5a0e-4930-90e9-6fbfcbb94c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048537225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1048537225
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3705646651
Short name T4
Test name
Test status
Simulation time 81890504 ps
CPU time 0.8 seconds
Started Feb 04 12:42:56 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 197656 kb
Host smart-43132750-fa4e-461f-8ac6-09d48720be9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705646651 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3705646651
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1320594174
Short name T26
Test name
Test status
Simulation time 65168002 ps
CPU time 0.88 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 213328 kb
Host smart-119211c9-89d9-4beb-8e7b-dfb887a8af43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320594174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1320594174
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2878857731
Short name T29
Test name
Test status
Simulation time 713524680 ps
CPU time 1.43 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 197792 kb
Host smart-781b018b-c23d-4967-b535-0b90efac979d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878857731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2878857731
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1669318474
Short name T58
Test name
Test status
Simulation time 259652233 ps
CPU time 1.18 seconds
Started Feb 04 04:16:04 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 195952 kb
Host smart-b88f12d8-3613-409d-bbbc-5b54bb5081e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1669318474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1669318474
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1584248654
Short name T13
Test name
Test status
Simulation time 66028482 ps
CPU time 0.8 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 196220 kb
Host smart-c32ce777-05ff-4fa2-9c2c-e249d21992ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584248654 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1584248654
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1281943773
Short name T101
Test name
Test status
Simulation time 397413727 ps
CPU time 1.38 seconds
Started Feb 04 12:43:12 PM PST 24
Finished Feb 04 12:43:17 PM PST 24
Peak memory 197848 kb
Host smart-0069ec3b-e0e5-455f-80e2-39b3cbba546f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281943773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1281943773
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1694133811
Short name T361
Test name
Test status
Simulation time 45357577 ps
CPU time 0.58 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 194736 kb
Host smart-bb05c482-e409-40f3-befb-9926445eb5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694133811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1694133811
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.882062035
Short name T82
Test name
Test status
Simulation time 14530544 ps
CPU time 0.62 seconds
Started Feb 04 12:43:45 PM PST 24
Finished Feb 04 12:43:46 PM PST 24
Peak memory 193680 kb
Host smart-f037adb4-f3d6-4fe2-a067-6eca5714c8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882062035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.882062035
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2810884526
Short name T30
Test name
Test status
Simulation time 73476759 ps
CPU time 1.11 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 197756 kb
Host smart-f4deaaa1-8584-4b9d-a26c-cbfd1f0b27f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810884526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2810884526
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1081212323
Short name T10
Test name
Test status
Simulation time 128712338 ps
CPU time 0.74 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:10 PM PST 24
Peak memory 195376 kb
Host smart-21497563-ba54-4b33-9a65-d413bc95e86d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081212323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1081212323
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1406212161
Short name T112
Test name
Test status
Simulation time 253528753 ps
CPU time 3.31 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:13 PM PST 24
Peak memory 197284 kb
Host smart-cf332aff-2a00-4b4f-94b3-79ac49bb4ed0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406212161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1406212161
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.243526841
Short name T898
Test name
Test status
Simulation time 42982529 ps
CPU time 0.64 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 195420 kb
Host smart-ddaa4a6a-3f79-42e4-a41e-afc091680365
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243526841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.243526841
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.630677538
Short name T922
Test name
Test status
Simulation time 281890638 ps
CPU time 0.93 seconds
Started Feb 04 12:42:56 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 197772 kb
Host smart-8cec2739-c331-45c5-8604-c0c2779485e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630677538 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.630677538
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3185497514
Short name T106
Test name
Test status
Simulation time 47745606 ps
CPU time 0.62 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 195052 kb
Host smart-8ef4210c-4879-4cb0-86e8-209510d9194b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185497514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3185497514
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1699214071
Short name T113
Test name
Test status
Simulation time 24611698 ps
CPU time 0.58 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 193924 kb
Host smart-5d1baaf6-2058-452b-8998-52a3680a760f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699214071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1699214071
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1112285616
Short name T94
Test name
Test status
Simulation time 32086960 ps
CPU time 0.79 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 196420 kb
Host smart-2208c486-5c4f-413a-bf3c-1ab6ff1dbc7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112285616 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1112285616
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2939764603
Short name T958
Test name
Test status
Simulation time 354288793 ps
CPU time 1.72 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 197856 kb
Host smart-08335fca-43ce-46ec-b6d1-3a0cfd0cb160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939764603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2939764603
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.32245185
Short name T40
Test name
Test status
Simulation time 309347502 ps
CPU time 1.18 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 197840 kb
Host smart-a8e6025a-e72e-4d5d-b82f-623c5c677815
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32245185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_tl_intg_err.32245185
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2227271324
Short name T86
Test name
Test status
Simulation time 29952657 ps
CPU time 0.71 seconds
Started Feb 04 12:42:57 PM PST 24
Finished Feb 04 12:42:59 PM PST 24
Peak memory 194864 kb
Host smart-3243cb7e-a470-4782-8057-65c1bcd50581
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227271324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2227271324
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2847351311
Short name T91
Test name
Test status
Simulation time 504461714 ps
CPU time 2.41 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 196424 kb
Host smart-067f7f03-30b0-46a2-8c43-1bb24958fe77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847351311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2847351311
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.654855836
Short name T909
Test name
Test status
Simulation time 13216383 ps
CPU time 0.63 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 194868 kb
Host smart-1f391926-9c5c-4f86-81b7-fe89ebdddcb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654855836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.654855836
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1935139886
Short name T955
Test name
Test status
Simulation time 46503232 ps
CPU time 1.32 seconds
Started Feb 04 12:42:55 PM PST 24
Finished Feb 04 12:42:59 PM PST 24
Peak memory 197856 kb
Host smart-fbfab309-cf61-4d2d-8660-4f8415263e56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935139886 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1935139886
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1867367632
Short name T92
Test name
Test status
Simulation time 11939445 ps
CPU time 0.59 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:11 PM PST 24
Peak memory 194820 kb
Host smart-0047e388-ab56-47c9-a26b-0242eafcb844
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867367632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1867367632
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3869186238
Short name T956
Test name
Test status
Simulation time 24044380 ps
CPU time 0.6 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 193548 kb
Host smart-83acfb36-3e68-4df5-ad27-02be3c3d952c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869186238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3869186238
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.259403084
Short name T1
Test name
Test status
Simulation time 50670679 ps
CPU time 1.18 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 197720 kb
Host smart-2ccc2505-56bc-48b2-a44d-bee678673471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259403084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.259403084
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.400981059
Short name T114
Test name
Test status
Simulation time 46092687 ps
CPU time 0.66 seconds
Started Feb 04 12:43:06 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 197248 kb
Host smart-81875a46-23d9-4c15-8d3f-7ab0b22d66ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400981059 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.400981059
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3513267191
Short name T964
Test name
Test status
Simulation time 13129891 ps
CPU time 0.64 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 194764 kb
Host smart-c15124b9-4860-4823-8d77-4c2fbf907bfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513267191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3513267191
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2305031499
Short name T894
Test name
Test status
Simulation time 24065283 ps
CPU time 0.62 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 194172 kb
Host smart-d9b7c467-af7a-4baa-bd11-cc3485a5dea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305031499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2305031499
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.193323789
Short name T949
Test name
Test status
Simulation time 19072141 ps
CPU time 0.84 seconds
Started Feb 04 12:43:06 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 196184 kb
Host smart-97da066e-7644-4c21-9eb3-4a0d4f62a544
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193323789 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.193323789
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1216866371
Short name T953
Test name
Test status
Simulation time 98942631 ps
CPU time 1.22 seconds
Started Feb 04 12:43:12 PM PST 24
Finished Feb 04 12:43:15 PM PST 24
Peak memory 197232 kb
Host smart-780b1a1f-acf1-4655-b96a-aac650e0b463
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216866371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1216866371
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.288072325
Short name T7
Test name
Test status
Simulation time 43796976 ps
CPU time 0.69 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 197548 kb
Host smart-0ae7c01c-28b6-445f-a016-14a5cbb49d91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288072325 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.288072325
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3701075508
Short name T2
Test name
Test status
Simulation time 57429469 ps
CPU time 0.63 seconds
Started Feb 04 12:43:12 PM PST 24
Finished Feb 04 12:43:15 PM PST 24
Peak memory 194908 kb
Host smart-cd6111ce-fc0f-460b-aecd-0412d62d0256
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701075508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3701075508
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1133445949
Short name T119
Test name
Test status
Simulation time 24519289 ps
CPU time 0.58 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 193624 kb
Host smart-df8a3978-8b14-4ed6-943a-0c8331e6e8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133445949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1133445949
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3761748782
Short name T96
Test name
Test status
Simulation time 41891302 ps
CPU time 0.69 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 194988 kb
Host smart-f5d5200d-e851-4695-808e-2dd7cc56e99f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761748782 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3761748782
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1450540005
Short name T931
Test name
Test status
Simulation time 70040946 ps
CPU time 1.46 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 197932 kb
Host smart-dfd23fb6-e1a6-4a50-8d34-95668b523122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450540005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1450540005
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3607296847
Short name T11
Test name
Test status
Simulation time 114133571 ps
CPU time 0.87 seconds
Started Feb 04 12:43:14 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 197736 kb
Host smart-993737db-d828-48a6-9350-5c17074abe80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607296847 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3607296847
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.509586154
Short name T104
Test name
Test status
Simulation time 15528412 ps
CPU time 0.65 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 194816 kb
Host smart-e78bea2f-6c46-4468-bf2f-c30c16c4fd64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509586154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.509586154
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3130441355
Short name T926
Test name
Test status
Simulation time 40738397 ps
CPU time 0.64 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 194288 kb
Host smart-ba56e841-0dc8-48b9-b634-83c5739e004b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130441355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3130441355
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1454760442
Short name T959
Test name
Test status
Simulation time 20042406 ps
CPU time 0.89 seconds
Started Feb 04 12:43:07 PM PST 24
Finished Feb 04 12:43:09 PM PST 24
Peak memory 196820 kb
Host smart-84630dc2-3969-44b1-a243-6a4593916d6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454760442 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1454760442
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3566634813
Short name T933
Test name
Test status
Simulation time 33771306 ps
CPU time 1.66 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 197844 kb
Host smart-5fe6c061-0a80-413f-870c-42d4f20d00d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566634813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3566634813
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1717612500
Short name T968
Test name
Test status
Simulation time 23812003 ps
CPU time 0.81 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 197776 kb
Host smart-e41c1b44-b208-4154-adfb-3a6babae2e3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717612500 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1717612500
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.704712627
Short name T80
Test name
Test status
Simulation time 17365790 ps
CPU time 0.65 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 194904 kb
Host smart-60be5c61-9f40-4495-98a8-5dbe38cb8264
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704712627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.704712627
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1229158082
Short name T109
Test name
Test status
Simulation time 72397030 ps
CPU time 0.59 seconds
Started Feb 04 12:43:06 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 193700 kb
Host smart-4bca5937-0183-40d6-bc68-1c7bffe844e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229158082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1229158082
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.591996447
Short name T93
Test name
Test status
Simulation time 32181336 ps
CPU time 0.87 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 196184 kb
Host smart-51b4ad4b-a391-4ad9-a3b4-e5ec4a89cdf9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591996447 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.591996447
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.911685372
Short name T935
Test name
Test status
Simulation time 87910023 ps
CPU time 2.32 seconds
Started Feb 04 12:43:08 PM PST 24
Finished Feb 04 12:43:12 PM PST 24
Peak memory 197928 kb
Host smart-43ea887d-8ce5-43a6-bd1d-f94495e40adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911685372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.911685372
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1358379718
Short name T904
Test name
Test status
Simulation time 743877078 ps
CPU time 1.49 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 197812 kb
Host smart-ea1f87f6-7293-4dc2-9370-e04e58706f86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358379718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1358379718
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3418608497
Short name T957
Test name
Test status
Simulation time 67613164 ps
CPU time 0.66 seconds
Started Feb 04 12:43:10 PM PST 24
Finished Feb 04 12:43:12 PM PST 24
Peak memory 196988 kb
Host smart-5d8efd8c-34e0-435c-8a4b-76563a5ff4bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418608497 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3418608497
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2412384833
Short name T8
Test name
Test status
Simulation time 13996771 ps
CPU time 0.62 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 194404 kb
Host smart-42648859-efd8-44ef-8a6c-5c5d04821310
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412384833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2412384833
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.821433463
Short name T901
Test name
Test status
Simulation time 28546688 ps
CPU time 0.61 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 193720 kb
Host smart-966f78e8-8e2f-4fbe-8a8c-f21b6f299298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821433463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.821433463
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.959285751
Short name T939
Test name
Test status
Simulation time 72849836 ps
CPU time 0.66 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 194916 kb
Host smart-d88b318e-2b16-4f75-b9fe-63fdb64f8d72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959285751 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.959285751
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.442906729
Short name T916
Test name
Test status
Simulation time 57648949 ps
CPU time 2.93 seconds
Started Feb 04 12:43:08 PM PST 24
Finished Feb 04 12:43:12 PM PST 24
Peak memory 197868 kb
Host smart-975bbfa0-3b7e-4bee-9a91-9b6e69c28554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442906729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.442906729
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2262218279
Short name T917
Test name
Test status
Simulation time 17135010 ps
CPU time 0.95 seconds
Started Feb 04 12:43:18 PM PST 24
Finished Feb 04 12:43:24 PM PST 24
Peak memory 197668 kb
Host smart-fa1319b5-8a57-4550-b053-94363228c4cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262218279 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2262218279
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3754595330
Short name T946
Test name
Test status
Simulation time 12776282 ps
CPU time 0.58 seconds
Started Feb 04 12:43:33 PM PST 24
Finished Feb 04 12:43:36 PM PST 24
Peak memory 193128 kb
Host smart-953320b8-1fb5-4ced-ad74-1bfb7e2113db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754595330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3754595330
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1162995299
Short name T965
Test name
Test status
Simulation time 18969948 ps
CPU time 0.65 seconds
Started Feb 04 12:43:33 PM PST 24
Finished Feb 04 12:43:36 PM PST 24
Peak memory 193612 kb
Host smart-a55d2d83-fd85-495a-bf36-0c581c2a91d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162995299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1162995299
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.857874395
Short name T969
Test name
Test status
Simulation time 66161010 ps
CPU time 0.82 seconds
Started Feb 04 12:43:35 PM PST 24
Finished Feb 04 12:43:37 PM PST 24
Peak memory 196164 kb
Host smart-c8d1f98c-dd83-418d-947f-7ea92906c785
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857874395 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.857874395
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3008761774
Short name T950
Test name
Test status
Simulation time 62777091 ps
CPU time 2.92 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:44 PM PST 24
Peak memory 197804 kb
Host smart-6f39aeb9-bce0-4924-9888-54080ee4b992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008761774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3008761774
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.233783201
Short name T24
Test name
Test status
Simulation time 117972694 ps
CPU time 1.44 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:43 PM PST 24
Peak memory 197780 kb
Host smart-2c547522-d1f9-4532-afe0-b2e28ce0190a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233783201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.233783201
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1192008158
Short name T966
Test name
Test status
Simulation time 93170573 ps
CPU time 0.85 seconds
Started Feb 04 12:43:45 PM PST 24
Finished Feb 04 12:43:47 PM PST 24
Peak memory 197752 kb
Host smart-ac6e34a4-2f90-47f2-b2f4-439027d63611
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192008158 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1192008158
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.772426738
Short name T85
Test name
Test status
Simulation time 35856993 ps
CPU time 0.62 seconds
Started Feb 04 12:43:45 PM PST 24
Finished Feb 04 12:43:46 PM PST 24
Peak memory 194848 kb
Host smart-3beedef0-5bdf-4ef2-9ff1-b5bee8f14324
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772426738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.772426738
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2833885423
Short name T121
Test name
Test status
Simulation time 43180914 ps
CPU time 0.55 seconds
Started Feb 04 12:43:34 PM PST 24
Finished Feb 04 12:43:36 PM PST 24
Peak memory 193560 kb
Host smart-db073294-2a8d-4c12-9a7e-8226721bad53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833885423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2833885423
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.57156341
Short name T83
Test name
Test status
Simulation time 19365267 ps
CPU time 0.74 seconds
Started Feb 04 12:43:20 PM PST 24
Finished Feb 04 12:43:24 PM PST 24
Peak memory 195832 kb
Host smart-686f4dea-3415-4926-8dd6-bf82c4833ca9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57156341 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.gpio_same_csr_outstanding.57156341
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.755382365
Short name T14
Test name
Test status
Simulation time 137032357 ps
CPU time 1.8 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:43 PM PST 24
Peak memory 197756 kb
Host smart-00fa56e4-957a-4414-9d6d-b9d72f2e55be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755382365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.755382365
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3782195924
Short name T952
Test name
Test status
Simulation time 153054965 ps
CPU time 0.9 seconds
Started Feb 04 12:43:45 PM PST 24
Finished Feb 04 12:43:46 PM PST 24
Peak memory 197588 kb
Host smart-5bb292e6-1d96-4013-9a1e-a215fe9ae5f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782195924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3782195924
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2867286937
Short name T970
Test name
Test status
Simulation time 16331957 ps
CPU time 0.73 seconds
Started Feb 04 12:43:21 PM PST 24
Finished Feb 04 12:43:24 PM PST 24
Peak memory 197040 kb
Host smart-34295d72-1a94-40ab-b0f3-c072bdbff8ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867286937 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2867286937
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3478227570
Short name T925
Test name
Test status
Simulation time 13750034 ps
CPU time 0.61 seconds
Started Feb 04 12:43:20 PM PST 24
Finished Feb 04 12:43:24 PM PST 24
Peak memory 194208 kb
Host smart-9ff189f7-48fd-4d41-aa23-b4f286ed0345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478227570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3478227570
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4008197597
Short name T6
Test name
Test status
Simulation time 129465687 ps
CPU time 0.78 seconds
Started Feb 04 12:43:35 PM PST 24
Finished Feb 04 12:43:42 PM PST 24
Peak memory 196252 kb
Host smart-3499d5ea-1e91-403c-ac2a-1c90c7634fcc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008197597 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4008197597
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4032945405
Short name T9
Test name
Test status
Simulation time 179360183 ps
CPU time 0.86 seconds
Started Feb 04 12:43:24 PM PST 24
Finished Feb 04 12:43:25 PM PST 24
Peak memory 197724 kb
Host smart-eab254fa-d20c-4cc9-b6cf-68eb241c6327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032945405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4032945405
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1101846864
Short name T936
Test name
Test status
Simulation time 95872043 ps
CPU time 1.17 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:43 PM PST 24
Peak memory 197828 kb
Host smart-9c88b493-c511-4f00-a0e4-6837f0613a51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101846864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1101846864
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.524764549
Short name T32
Test name
Test status
Simulation time 23276781 ps
CPU time 0.81 seconds
Started Feb 04 12:43:25 PM PST 24
Finished Feb 04 12:43:27 PM PST 24
Peak memory 197904 kb
Host smart-55dca097-a913-4b1b-99af-95e78a14e2be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524764549 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.524764549
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3024488495
Short name T105
Test name
Test status
Simulation time 16871908 ps
CPU time 0.63 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:42 PM PST 24
Peak memory 194812 kb
Host smart-d7604df3-16fb-4c67-9d4d-08ee50cda393
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024488495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3024488495
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.67252830
Short name T896
Test name
Test status
Simulation time 85485601 ps
CPU time 0.57 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:42 PM PST 24
Peak memory 193480 kb
Host smart-3479972a-6975-4286-bf78-5faa76b72ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67252830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.67252830
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3814237989
Short name T919
Test name
Test status
Simulation time 35578946 ps
CPU time 0.62 seconds
Started Feb 04 12:43:25 PM PST 24
Finished Feb 04 12:43:27 PM PST 24
Peak memory 194920 kb
Host smart-9643dd2e-f4c6-4e4f-970d-aa1cf57d5a8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814237989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3814237989
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3959136521
Short name T962
Test name
Test status
Simulation time 128510326 ps
CPU time 2.23 seconds
Started Feb 04 12:43:47 PM PST 24
Finished Feb 04 12:43:49 PM PST 24
Peak memory 197780 kb
Host smart-a6a3587b-8f05-430c-abbf-bdf692a74130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959136521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3959136521
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1117867550
Short name T36
Test name
Test status
Simulation time 380766690 ps
CPU time 1.33 seconds
Started Feb 04 12:43:34 PM PST 24
Finished Feb 04 12:43:36 PM PST 24
Peak memory 197792 kb
Host smart-a51a28d3-673f-4c0f-92f7-9e484086a112
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117867550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1117867550
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3205955688
Short name T944
Test name
Test status
Simulation time 30765221 ps
CPU time 0.93 seconds
Started Feb 04 12:44:26 PM PST 24
Finished Feb 04 12:44:29 PM PST 24
Peak memory 197808 kb
Host smart-ef1bf25e-7b2b-4f45-bf8e-b73f4e5a7cba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205955688 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3205955688
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1783032728
Short name T963
Test name
Test status
Simulation time 76575643 ps
CPU time 0.58 seconds
Started Feb 04 12:43:40 PM PST 24
Finished Feb 04 12:43:42 PM PST 24
Peak memory 193728 kb
Host smart-cee2ed14-006d-4e50-9256-5422c3f11d54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783032728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1783032728
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1341212140
Short name T930
Test name
Test status
Simulation time 128988544 ps
CPU time 0.59 seconds
Started Feb 04 12:44:26 PM PST 24
Finished Feb 04 12:44:27 PM PST 24
Peak memory 194272 kb
Host smart-2ec99fb1-24ed-4df3-9fe2-4df4dd8c5120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341212140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1341212140
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1051269693
Short name T912
Test name
Test status
Simulation time 62291686 ps
CPU time 0.63 seconds
Started Feb 04 12:44:25 PM PST 24
Finished Feb 04 12:44:26 PM PST 24
Peak memory 194592 kb
Host smart-0525facb-1cd6-480f-b684-0f943ea3dfb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051269693 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1051269693
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3433029407
Short name T911
Test name
Test status
Simulation time 298419342 ps
CPU time 1.75 seconds
Started Feb 04 12:44:34 PM PST 24
Finished Feb 04 12:44:40 PM PST 24
Peak memory 197792 kb
Host smart-336342f8-2b2c-4188-be23-1f82369a418e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433029407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3433029407
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.50128725
Short name T39
Test name
Test status
Simulation time 67885580 ps
CPU time 1.16 seconds
Started Feb 04 12:44:25 PM PST 24
Finished Feb 04 12:44:27 PM PST 24
Peak memory 197832 kb
Host smart-e719301f-5759-49b1-8b98-be3113e5f5d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50128725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.gpio_tl_intg_err.50128725
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.194629628
Short name T87
Test name
Test status
Simulation time 209210166 ps
CPU time 0.84 seconds
Started Feb 04 12:42:55 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 196016 kb
Host smart-df0f4587-d12f-4220-92d0-ff94bdf9c42c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194629628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.194629628
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.582890316
Short name T907
Test name
Test status
Simulation time 108454124 ps
CPU time 1.4 seconds
Started Feb 04 12:42:56 PM PST 24
Finished Feb 04 12:42:59 PM PST 24
Peak memory 197616 kb
Host smart-d059d2c7-789e-4cbc-b1e9-2daca12f0842
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582890316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.582890316
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2916194250
Short name T33
Test name
Test status
Simulation time 165036269 ps
CPU time 0.65 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 195040 kb
Host smart-8a4c12b8-7d11-481c-8dff-6e27379526b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916194250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2916194250
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2628512550
Short name T942
Test name
Test status
Simulation time 40007718 ps
CPU time 0.57 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 194428 kb
Host smart-68a83ead-d2a4-4d88-abd8-aada68ffff24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628512550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2628512550
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1712107275
Short name T15
Test name
Test status
Simulation time 26522942 ps
CPU time 0.57 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 194204 kb
Host smart-abde192e-a365-4ef9-9d9c-96f2233e70c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712107275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1712107275
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1842494670
Short name T923
Test name
Test status
Simulation time 76219778 ps
CPU time 0.69 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 196008 kb
Host smart-aab1df96-3efb-42d2-9e07-e1e965b15ac0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842494670 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1842494670
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.202274743
Short name T937
Test name
Test status
Simulation time 63894465 ps
CPU time 1.45 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 197776 kb
Host smart-bc1ceb9b-ac22-485c-aa3d-ee351fee609e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202274743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.202274743
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3798707610
Short name T38
Test name
Test status
Simulation time 82905982 ps
CPU time 1.17 seconds
Started Feb 04 12:43:08 PM PST 24
Finished Feb 04 12:43:10 PM PST 24
Peak memory 197840 kb
Host smart-d87539a9-1f49-40db-94e4-6aa48be166c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798707610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3798707610
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.799130969
Short name T893
Test name
Test status
Simulation time 45697317 ps
CPU time 0.62 seconds
Started Feb 04 12:44:19 PM PST 24
Finished Feb 04 12:44:21 PM PST 24
Peak memory 194328 kb
Host smart-f91d7dc2-cdc9-40d4-9775-fd26fef9614f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799130969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.799130969
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2957368091
Short name T89
Test name
Test status
Simulation time 12416170 ps
CPU time 0.58 seconds
Started Feb 04 12:44:33 PM PST 24
Finished Feb 04 12:44:38 PM PST 24
Peak memory 193536 kb
Host smart-96fcd5e0-3d94-4c9d-83f0-ed690cd5f7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957368091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2957368091
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.977625000
Short name T115
Test name
Test status
Simulation time 78657471 ps
CPU time 0.61 seconds
Started Feb 04 12:44:29 PM PST 24
Finished Feb 04 12:44:31 PM PST 24
Peak memory 194232 kb
Host smart-fc4719a3-8b31-4fdf-939a-6a5fc0352ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977625000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.977625000
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1179498564
Short name T913
Test name
Test status
Simulation time 42533203 ps
CPU time 0.61 seconds
Started Feb 04 12:44:25 PM PST 24
Finished Feb 04 12:44:27 PM PST 24
Peak memory 193572 kb
Host smart-edf76dd4-7f1c-4fdc-b07b-c85b5d9f6233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179498564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1179498564
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3846723237
Short name T123
Test name
Test status
Simulation time 41972805 ps
CPU time 0.59 seconds
Started Feb 04 12:44:32 PM PST 24
Finished Feb 04 12:44:34 PM PST 24
Peak memory 193544 kb
Host smart-c74815b2-cffd-4cfa-babf-2740937f30fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846723237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3846723237
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3916295490
Short name T20
Test name
Test status
Simulation time 31292780 ps
CPU time 0.57 seconds
Started Feb 04 12:44:18 PM PST 24
Finished Feb 04 12:44:20 PM PST 24
Peak memory 194192 kb
Host smart-b40beb57-16e3-4281-8025-178eb2ee2d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916295490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3916295490
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1748792870
Short name T111
Test name
Test status
Simulation time 13336214 ps
CPU time 0.6 seconds
Started Feb 04 12:44:16 PM PST 24
Finished Feb 04 12:44:17 PM PST 24
Peak memory 193624 kb
Host smart-6c48a967-abb4-473a-8c31-1597fbbb3d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748792870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1748792870
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.831822071
Short name T110
Test name
Test status
Simulation time 37477631 ps
CPU time 0.62 seconds
Started Feb 04 12:44:17 PM PST 24
Finished Feb 04 12:44:19 PM PST 24
Peak memory 194164 kb
Host smart-3e21a987-558c-4fbd-9171-0337b239c436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831822071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.831822071
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.99286180
Short name T23
Test name
Test status
Simulation time 15884330 ps
CPU time 0.6 seconds
Started Feb 04 12:44:18 PM PST 24
Finished Feb 04 12:44:20 PM PST 24
Peak memory 193524 kb
Host smart-816f913b-9844-4e99-a375-9b8d18013301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99286180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.99286180
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4174824557
Short name T905
Test name
Test status
Simulation time 38826759 ps
CPU time 0.56 seconds
Started Feb 04 12:44:14 PM PST 24
Finished Feb 04 12:44:17 PM PST 24
Peak memory 193476 kb
Host smart-ed817d69-ad95-4c7c-9e5e-12907d25102f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174824557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4174824557
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4188232443
Short name T90
Test name
Test status
Simulation time 50472086 ps
CPU time 0.76 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 196476 kb
Host smart-c9eafcde-2437-4c88-869d-673210878f9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188232443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4188232443
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1932181634
Short name T947
Test name
Test status
Simulation time 263430405 ps
CPU time 1.61 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 196444 kb
Host smart-06a0322b-3c26-4b5c-a3ba-94baab31f0e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932181634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1932181634
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2096629759
Short name T34
Test name
Test status
Simulation time 16607086 ps
CPU time 0.63 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 195248 kb
Host smart-811cc663-a409-4554-a6d6-5b50db47f17b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096629759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2096629759
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.959357308
Short name T889
Test name
Test status
Simulation time 95779863 ps
CPU time 0.85 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 197804 kb
Host smart-398ee899-0a3f-4d56-92d4-e3fb3a56708a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959357308 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.959357308
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1519385481
Short name T902
Test name
Test status
Simulation time 12174604 ps
CPU time 0.59 seconds
Started Feb 04 12:42:57 PM PST 24
Finished Feb 04 12:42:59 PM PST 24
Peak memory 194716 kb
Host smart-f73f4351-bbf8-4d1f-a098-361c7e3ae838
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519385481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1519385481
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4218463760
Short name T117
Test name
Test status
Simulation time 19157804 ps
CPU time 0.62 seconds
Started Feb 04 12:42:58 PM PST 24
Finished Feb 04 12:43:00 PM PST 24
Peak memory 194208 kb
Host smart-7e1f8bea-157b-48b7-bf66-958e91868d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218463760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4218463760
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.828865010
Short name T78
Test name
Test status
Simulation time 64183249 ps
CPU time 0.72 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 194920 kb
Host smart-4d3f3ef1-b74a-4506-b269-5cc0367a0de2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828865010 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.828865010
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3684440857
Short name T895
Test name
Test status
Simulation time 319716927 ps
CPU time 3.43 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 197948 kb
Host smart-b40c9439-55e3-4c45-94e2-bafac182326e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684440857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3684440857
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3778903925
Short name T31
Test name
Test status
Simulation time 132544569 ps
CPU time 1.42 seconds
Started Feb 04 12:42:58 PM PST 24
Finished Feb 04 12:43:01 PM PST 24
Peak memory 197852 kb
Host smart-1e41cdca-55d1-4d2e-9f8d-bf2a14459d57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778903925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3778903925
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3192805121
Short name T116
Test name
Test status
Simulation time 19987247 ps
CPU time 0.59 seconds
Started Feb 04 12:44:18 PM PST 24
Finished Feb 04 12:44:19 PM PST 24
Peak memory 193680 kb
Host smart-401b2785-d289-418a-9e08-5bede193b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192805121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3192805121
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1991164400
Short name T890
Test name
Test status
Simulation time 91459545 ps
CPU time 0.57 seconds
Started Feb 04 12:44:16 PM PST 24
Finished Feb 04 12:44:18 PM PST 24
Peak memory 193568 kb
Host smart-7b7ebb13-83fd-4f2e-b1a6-6a46f203b695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991164400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1991164400
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.774196163
Short name T899
Test name
Test status
Simulation time 39182135 ps
CPU time 0.64 seconds
Started Feb 04 12:44:22 PM PST 24
Finished Feb 04 12:44:24 PM PST 24
Peak memory 194228 kb
Host smart-e5fc1219-f5bb-4b5d-a24f-141e9a0064b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774196163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.774196163
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.797299390
Short name T21
Test name
Test status
Simulation time 32659900 ps
CPU time 0.64 seconds
Started Feb 04 12:44:22 PM PST 24
Finished Feb 04 12:44:24 PM PST 24
Peak memory 193636 kb
Host smart-10c24456-7287-4aba-997d-229425af5484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797299390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.797299390
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2650320970
Short name T945
Test name
Test status
Simulation time 16987070 ps
CPU time 0.65 seconds
Started Feb 04 12:44:17 PM PST 24
Finished Feb 04 12:44:19 PM PST 24
Peak memory 193576 kb
Host smart-b47a33fe-fd7d-4acf-8c91-7fe503b4a07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650320970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2650320970
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1586868981
Short name T915
Test name
Test status
Simulation time 25121271 ps
CPU time 0.67 seconds
Started Feb 04 12:44:19 PM PST 24
Finished Feb 04 12:44:21 PM PST 24
Peak memory 194272 kb
Host smart-4ed04f0c-b337-4cbf-b60a-4ed7ee20a80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586868981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1586868981
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4087572676
Short name T22
Test name
Test status
Simulation time 37426191 ps
CPU time 0.58 seconds
Started Feb 04 12:44:15 PM PST 24
Finished Feb 04 12:44:17 PM PST 24
Peak memory 194136 kb
Host smart-33dc4adc-0ac6-468c-ae32-bed6b1e43848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087572676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4087572676
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2634391513
Short name T108
Test name
Test status
Simulation time 26698914 ps
CPU time 0.57 seconds
Started Feb 04 12:44:26 PM PST 24
Finished Feb 04 12:44:27 PM PST 24
Peak memory 193580 kb
Host smart-965f5539-ded6-47b8-8fa9-29c25e0755a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634391513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2634391513
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2742956266
Short name T908
Test name
Test status
Simulation time 25929326 ps
CPU time 0.57 seconds
Started Feb 04 12:44:13 PM PST 24
Finished Feb 04 12:44:17 PM PST 24
Peak memory 193608 kb
Host smart-2123e561-cfaa-4d85-a854-b50135b7da25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742956266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2742956266
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.397988134
Short name T934
Test name
Test status
Simulation time 14436182 ps
CPU time 0.6 seconds
Started Feb 04 12:44:25 PM PST 24
Finished Feb 04 12:44:26 PM PST 24
Peak memory 193528 kb
Host smart-30971a3c-47fd-4454-8709-53bb985d2ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397988134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.397988134
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3857855133
Short name T88
Test name
Test status
Simulation time 57401384 ps
CPU time 2.19 seconds
Started Feb 04 12:42:57 PM PST 24
Finished Feb 04 12:43:00 PM PST 24
Peak memory 197848 kb
Host smart-f82bbfde-abf2-440b-80b7-91f8abf9cab2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857855133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3857855133
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4240925943
Short name T932
Test name
Test status
Simulation time 12958051 ps
CPU time 0.63 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:01 PM PST 24
Peak memory 194328 kb
Host smart-35c4d785-61ca-45cb-8a24-af2c5bac8726
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240925943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4240925943
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1308062240
Short name T928
Test name
Test status
Simulation time 78769076 ps
CPU time 1.18 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 197912 kb
Host smart-9c008c3f-2ab9-442e-8c12-09a1d1dd6618
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308062240 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1308062240
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3994672780
Short name T19
Test name
Test status
Simulation time 15291431 ps
CPU time 0.58 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 193812 kb
Host smart-7452f488-64f5-4d11-820a-3ae1dc78c778
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994672780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3994672780
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.889442868
Short name T929
Test name
Test status
Simulation time 17784876 ps
CPU time 0.62 seconds
Started Feb 04 12:42:56 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 193568 kb
Host smart-5a75466d-fba9-4322-bb68-6f67edb62ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889442868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.889442868
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1930373970
Short name T920
Test name
Test status
Simulation time 227205126 ps
CPU time 0.78 seconds
Started Feb 04 12:42:57 PM PST 24
Finished Feb 04 12:43:00 PM PST 24
Peak memory 196224 kb
Host smart-41e5860f-d97b-4237-a8e2-00daa2993829
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930373970 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1930373970
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2211838879
Short name T37
Test name
Test status
Simulation time 26857081 ps
CPU time 1.35 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 197868 kb
Host smart-40b6284c-7b83-44cc-afcb-501c24e9dc66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211838879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2211838879
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3509717156
Short name T25
Test name
Test status
Simulation time 1970702743 ps
CPU time 1.43 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 197876 kb
Host smart-3a73e8d7-c039-43dc-8ce1-da70ca958d7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509717156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3509717156
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.39083192
Short name T122
Test name
Test status
Simulation time 43050212 ps
CPU time 0.66 seconds
Started Feb 04 12:44:15 PM PST 24
Finished Feb 04 12:44:17 PM PST 24
Peak memory 194308 kb
Host smart-cb3530cb-c4fe-4049-aaaf-3e336fc8c19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39083192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.39083192
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2055913557
Short name T961
Test name
Test status
Simulation time 33851301 ps
CPU time 0.61 seconds
Started Feb 04 12:44:24 PM PST 24
Finished Feb 04 12:44:26 PM PST 24
Peak memory 193644 kb
Host smart-9570ef7c-c4da-4d4d-90a8-982060d62be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055913557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2055913557
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2447417782
Short name T897
Test name
Test status
Simulation time 15454615 ps
CPU time 0.62 seconds
Started Feb 04 12:44:17 PM PST 24
Finished Feb 04 12:44:19 PM PST 24
Peak memory 193684 kb
Host smart-5db3df8a-3a0d-4772-a091-26a7215b361c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447417782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2447417782
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3337797352
Short name T967
Test name
Test status
Simulation time 42404681 ps
CPU time 0.6 seconds
Started Feb 04 12:44:32 PM PST 24
Finished Feb 04 12:44:34 PM PST 24
Peak memory 194224 kb
Host smart-939203a9-02cd-4f5d-87a8-0fb1f633491e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337797352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3337797352
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.59425566
Short name T906
Test name
Test status
Simulation time 13864486 ps
CPU time 0.63 seconds
Started Feb 04 12:44:34 PM PST 24
Finished Feb 04 12:44:38 PM PST 24
Peak memory 193576 kb
Host smart-724be014-3d0f-4acb-a3d5-4a0cd31b190c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59425566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.59425566
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2467389043
Short name T81
Test name
Test status
Simulation time 24222951 ps
CPU time 0.62 seconds
Started Feb 04 12:44:22 PM PST 24
Finished Feb 04 12:44:24 PM PST 24
Peak memory 193588 kb
Host smart-697897c1-522a-412d-b19e-c40ca1d56dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467389043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2467389043
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.894531535
Short name T892
Test name
Test status
Simulation time 29648188 ps
CPU time 0.6 seconds
Started Feb 04 12:44:19 PM PST 24
Finished Feb 04 12:44:20 PM PST 24
Peak memory 193688 kb
Host smart-01828cd2-cff0-4710-8728-0a906d0c7238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894531535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.894531535
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1841746195
Short name T99
Test name
Test status
Simulation time 48031941 ps
CPU time 0.62 seconds
Started Feb 04 12:44:29 PM PST 24
Finished Feb 04 12:44:30 PM PST 24
Peak memory 193628 kb
Host smart-200011af-858c-4464-8b94-c4966d0ac6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841746195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1841746195
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.643452658
Short name T891
Test name
Test status
Simulation time 19036726 ps
CPU time 0.59 seconds
Started Feb 04 12:44:21 PM PST 24
Finished Feb 04 12:44:23 PM PST 24
Peak memory 194224 kb
Host smart-b38ecc8b-448d-40a7-b93d-df4db074dcc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643452658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.643452658
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3706622385
Short name T951
Test name
Test status
Simulation time 15123802 ps
CPU time 0.64 seconds
Started Feb 04 12:43:07 PM PST 24
Finished Feb 04 12:43:09 PM PST 24
Peak memory 196732 kb
Host smart-2cadcfe1-f5c6-4544-aad8-32c6068afc98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706622385 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3706622385
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1320548880
Short name T98
Test name
Test status
Simulation time 26220362 ps
CPU time 0.59 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:01 PM PST 24
Peak memory 194780 kb
Host smart-fd2eb50a-232e-455e-a23d-a86933ff14b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320548880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1320548880
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2861249910
Short name T118
Test name
Test status
Simulation time 34998763 ps
CPU time 0.58 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:11 PM PST 24
Peak memory 194244 kb
Host smart-db0f64da-d249-438e-8e8b-6d3c547dbe95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861249910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2861249910
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.776121229
Short name T938
Test name
Test status
Simulation time 68804117 ps
CPU time 0.83 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 197264 kb
Host smart-f060401e-9a99-43e3-b3fc-2f3c441c927d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776121229 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.776121229
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1168024327
Short name T943
Test name
Test status
Simulation time 146110105 ps
CPU time 2.08 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:13 PM PST 24
Peak memory 197864 kb
Host smart-25c6c517-631e-4e1b-b922-e3d968ff8061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168024327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1168024327
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3727562440
Short name T75
Test name
Test status
Simulation time 199949885 ps
CPU time 0.84 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 197380 kb
Host smart-34ad0c12-e1cb-4fd5-b15b-dcef2615ba91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727562440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3727562440
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.928945184
Short name T120
Test name
Test status
Simulation time 85298494 ps
CPU time 0.7 seconds
Started Feb 04 12:43:02 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 196952 kb
Host smart-9cb5c5eb-cb8b-45d2-a317-317706c77f7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928945184 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.928945184
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2920250473
Short name T77
Test name
Test status
Simulation time 17306699 ps
CPU time 0.63 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:10 PM PST 24
Peak memory 194936 kb
Host smart-77188687-b138-4983-a69f-e4680f870d63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920250473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2920250473
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2234134054
Short name T900
Test name
Test status
Simulation time 46070002 ps
CPU time 0.61 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 194228 kb
Host smart-4a2af5a4-f044-47fb-972a-d871f2345ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234134054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2234134054
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2932320345
Short name T97
Test name
Test status
Simulation time 140454822 ps
CPU time 0.85 seconds
Started Feb 04 12:43:09 PM PST 24
Finished Feb 04 12:43:10 PM PST 24
Peak memory 196164 kb
Host smart-37ca5814-25cb-4041-bb10-d267de457816
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932320345 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2932320345
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.921875540
Short name T41
Test name
Test status
Simulation time 53951950 ps
CPU time 1.24 seconds
Started Feb 04 12:42:59 PM PST 24
Finished Feb 04 12:43:02 PM PST 24
Peak memory 197816 kb
Host smart-89b85390-dd84-48ea-961b-a231b230eec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921875540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.921875540
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1921581779
Short name T921
Test name
Test status
Simulation time 221018928 ps
CPU time 1.49 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 197816 kb
Host smart-d8359313-7b65-45ef-ae8e-d77f72de69d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921581779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1921581779
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2949088141
Short name T910
Test name
Test status
Simulation time 35157806 ps
CPU time 0.68 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 197716 kb
Host smart-9bb6815c-48ab-4bff-a0bb-fb8bfe4151ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949088141 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2949088141
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3602905680
Short name T73
Test name
Test status
Simulation time 18495616 ps
CPU time 0.6 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 195176 kb
Host smart-8c3f9993-66ef-4082-8234-e01b8f69b9c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602905680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3602905680
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.125681105
Short name T960
Test name
Test status
Simulation time 16327762 ps
CPU time 0.6 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 194216 kb
Host smart-b9cedb58-627b-4c40-a56c-7f173e53d364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125681105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.125681105
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.410706877
Short name T95
Test name
Test status
Simulation time 34446892 ps
CPU time 0.67 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:03 PM PST 24
Peak memory 194740 kb
Host smart-dd9f9ad6-9e24-4216-9c45-4a0569210032
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410706877 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.410706877
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2298752693
Short name T903
Test name
Test status
Simulation time 38016574 ps
CPU time 1.97 seconds
Started Feb 04 12:43:00 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 197840 kb
Host smart-741267c2-2947-4d86-9bf2-a9559cec103e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298752693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2298752693
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.996315990
Short name T948
Test name
Test status
Simulation time 252507790 ps
CPU time 1.18 seconds
Started Feb 04 12:43:02 PM PST 24
Finished Feb 04 12:43:06 PM PST 24
Peak memory 197808 kb
Host smart-8f667a7a-03a1-4daa-ae43-561e02aa3098
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996315990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.996315990
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3857945892
Short name T18
Test name
Test status
Simulation time 19085194 ps
CPU time 0.64 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:07 PM PST 24
Peak memory 196844 kb
Host smart-4d9480c7-8e04-4932-91b7-a742591ce945
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857945892 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3857945892
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3030764387
Short name T924
Test name
Test status
Simulation time 12867309 ps
CPU time 0.6 seconds
Started Feb 04 12:42:55 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 194580 kb
Host smart-404bc542-76d1-46ba-a1c1-647ac91e4107
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030764387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3030764387
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1978553775
Short name T76
Test name
Test status
Simulation time 14739673 ps
CPU time 0.57 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 193564 kb
Host smart-512a24c2-a3a0-4c3e-9d8a-231cfe554cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978553775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1978553775
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.292008833
Short name T12
Test name
Test status
Simulation time 29260233 ps
CPU time 0.65 seconds
Started Feb 04 12:42:55 PM PST 24
Finished Feb 04 12:42:58 PM PST 24
Peak memory 195532 kb
Host smart-d0d2121a-c6c2-4586-b050-5669a8442e23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292008833 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.292008833
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4194488953
Short name T927
Test name
Test status
Simulation time 49396790 ps
CPU time 1.41 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:09 PM PST 24
Peak memory 197840 kb
Host smart-b77ab50e-eaa3-45d6-ba5f-7d92c16ed5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194488953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4194488953
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4154648493
Short name T918
Test name
Test status
Simulation time 173672374 ps
CPU time 0.87 seconds
Started Feb 04 12:43:01 PM PST 24
Finished Feb 04 12:43:04 PM PST 24
Peak memory 196820 kb
Host smart-ce2cc517-4bde-4bcb-8616-495ee7d95944
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154648493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4154648493
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3609613703
Short name T914
Test name
Test status
Simulation time 160084853 ps
CPU time 1.12 seconds
Started Feb 04 12:43:08 PM PST 24
Finished Feb 04 12:43:10 PM PST 24
Peak memory 197860 kb
Host smart-05d07f7e-1d69-4366-8d77-697a1f9c57c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609613703 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3609613703
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.964011576
Short name T79
Test name
Test status
Simulation time 36023058 ps
CPU time 0.66 seconds
Started Feb 04 12:43:05 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 195420 kb
Host smart-e07d2b80-61dd-47c2-ae50-5ec16723b5e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964011576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.964011576
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2619730879
Short name T941
Test name
Test status
Simulation time 187065270 ps
CPU time 0.64 seconds
Started Feb 04 12:43:15 PM PST 24
Finished Feb 04 12:43:18 PM PST 24
Peak memory 193512 kb
Host smart-1ad59dad-c2aa-4ac6-afcd-fbe880bcc588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619730879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2619730879
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3121622618
Short name T954
Test name
Test status
Simulation time 47830506 ps
CPU time 0.63 seconds
Started Feb 04 12:43:03 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 194552 kb
Host smart-3f6cc601-ab43-46de-9dfb-669c189c7394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121622618 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3121622618
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.911684340
Short name T74
Test name
Test status
Simulation time 120302487 ps
CPU time 2.59 seconds
Started Feb 04 12:43:08 PM PST 24
Finished Feb 04 12:43:12 PM PST 24
Peak memory 197808 kb
Host smart-b0fd60f1-c24f-46d2-8b36-66b97994b539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911684340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.911684340
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.535241773
Short name T940
Test name
Test status
Simulation time 792927527 ps
CPU time 1.48 seconds
Started Feb 04 12:43:04 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 197864 kb
Host smart-4fb6c21d-f519-4f7c-9ad4-23d6ad268884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535241773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.535241773
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2396403421
Short name T749
Test name
Test status
Simulation time 12040314 ps
CPU time 0.56 seconds
Started Feb 04 02:42:07 PM PST 24
Finished Feb 04 02:42:11 PM PST 24
Peak memory 193688 kb
Host smart-89908ce8-a827-486d-8cbf-447ba1bd3ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396403421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2396403421
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3656468739
Short name T322
Test name
Test status
Simulation time 35941486 ps
CPU time 0.63 seconds
Started Feb 04 02:42:15 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 194500 kb
Host smart-3bfe2df7-ce36-467b-865c-5c095e373686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656468739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3656468739
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3162201124
Short name T502
Test name
Test status
Simulation time 997924758 ps
CPU time 16.41 seconds
Started Feb 04 02:42:08 PM PST 24
Finished Feb 04 02:42:27 PM PST 24
Peak memory 195328 kb
Host smart-5a07808f-1279-47be-9ce3-6e7bb79918bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162201124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3162201124
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1025235273
Short name T379
Test name
Test status
Simulation time 183381820 ps
CPU time 0.98 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 195648 kb
Host smart-75b4300f-14be-4628-be74-b7d45fffbb57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025235273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1025235273
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2759043789
Short name T793
Test name
Test status
Simulation time 176211164 ps
CPU time 0.84 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 196180 kb
Host smart-e381db26-4a4e-4ded-bbe0-bc5cd318d857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759043789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2759043789
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.338049588
Short name T368
Test name
Test status
Simulation time 94574253 ps
CPU time 3.79 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 197844 kb
Host smart-259f99f7-eb20-48a3-852a-cb7be3bdf5d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338049588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.338049588
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1680289984
Short name T565
Test name
Test status
Simulation time 95637792 ps
CPU time 1.27 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 197408 kb
Host smart-3c6e4f55-fa5a-4f87-933f-eea62ca9fc86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680289984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1680289984
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1464164289
Short name T631
Test name
Test status
Simulation time 31377255 ps
CPU time 0.84 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 196452 kb
Host smart-9b49cf31-6b4d-4cd9-b28c-f1fb33286609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464164289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1464164289
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4238701133
Short name T663
Test name
Test status
Simulation time 28423675 ps
CPU time 1.1 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 195748 kb
Host smart-33e2c354-14b7-4c10-9aeb-cdfa9f2024fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238701133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4238701133
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.687063373
Short name T457
Test name
Test status
Simulation time 104334025 ps
CPU time 4.54 seconds
Started Feb 04 02:42:05 PM PST 24
Finished Feb 04 02:42:14 PM PST 24
Peak memory 197884 kb
Host smart-75b2b689-37c1-402c-ba50-c6b53d4d6402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687063373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.687063373
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3777427374
Short name T28
Test name
Test status
Simulation time 58971287 ps
CPU time 0.88 seconds
Started Feb 04 02:42:15 PM PST 24
Finished Feb 04 02:42:21 PM PST 24
Peak memory 213264 kb
Host smart-33bb00c7-24ce-4072-8067-8e30b65a6954
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777427374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3777427374
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.644781692
Short name T68
Test name
Test status
Simulation time 30913688 ps
CPU time 0.98 seconds
Started Feb 04 02:42:05 PM PST 24
Finished Feb 04 02:42:10 PM PST 24
Peak memory 195492 kb
Host smart-1c97dce0-b604-4fb1-bada-5a5ad2bb932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644781692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.644781692
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2075876302
Short name T481
Test name
Test status
Simulation time 63206050 ps
CPU time 1.35 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:18 PM PST 24
Peak memory 196616 kb
Host smart-ed26f59b-db4e-4a98-bce5-d7a11a271584
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075876302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2075876302
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.736601048
Short name T450
Test name
Test status
Simulation time 41117533235 ps
CPU time 80.64 seconds
Started Feb 04 02:42:16 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 197896 kb
Host smart-00f076ff-77c2-44b4-bfd7-e2aa753731a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736601048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.736601048
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1298658
Short name T477
Test name
Test status
Simulation time 73287652129 ps
CPU time 1754.01 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 03:11:30 PM PST 24
Peak memory 197980 kb
Host smart-51e0a8d5-8715-48a8-9cc5-3604a479ac65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1298658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1298658
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.310559934
Short name T460
Test name
Test status
Simulation time 34221196 ps
CPU time 0.57 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 193736 kb
Host smart-6ed28f0e-2f84-435c-9972-56dfe13113d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310559934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.310559934
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2643948098
Short name T540
Test name
Test status
Simulation time 27149803 ps
CPU time 0.84 seconds
Started Feb 04 02:42:06 PM PST 24
Finished Feb 04 02:42:11 PM PST 24
Peak memory 196320 kb
Host smart-44064253-6d2a-48c9-bf4c-fe7d6d07c79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643948098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2643948098
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1126924472
Short name T216
Test name
Test status
Simulation time 423034249 ps
CPU time 21.63 seconds
Started Feb 04 02:42:15 PM PST 24
Finished Feb 04 02:42:41 PM PST 24
Peak memory 196700 kb
Host smart-84581ffe-bfeb-48eb-9c88-91b75a8a22e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126924472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1126924472
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.167098269
Short name T664
Test name
Test status
Simulation time 61240461 ps
CPU time 0.88 seconds
Started Feb 04 02:42:11 PM PST 24
Finished Feb 04 02:42:14 PM PST 24
Peak memory 195776 kb
Host smart-127c2ce8-e001-4807-a0f5-489afd3ebed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167098269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.167098269
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2588595991
Short name T497
Test name
Test status
Simulation time 223563591 ps
CPU time 1.09 seconds
Started Feb 04 02:42:08 PM PST 24
Finished Feb 04 02:42:13 PM PST 24
Peak memory 196676 kb
Host smart-48e7760d-08ae-48d6-8b36-dc3a42274967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588595991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2588595991
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.939420268
Short name T773
Test name
Test status
Simulation time 129439914 ps
CPU time 2.83 seconds
Started Feb 04 02:42:17 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 197812 kb
Host smart-48db8107-f1cf-4a5d-8873-6d5d11433b35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939420268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.939420268
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3213443112
Short name T807
Test name
Test status
Simulation time 116788984 ps
CPU time 0.92 seconds
Started Feb 04 02:42:12 PM PST 24
Finished Feb 04 02:42:15 PM PST 24
Peak memory 195268 kb
Host smart-5d9613bb-71e8-4a5a-9eb5-aa5cc98a9f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213443112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3213443112
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2103360991
Short name T329
Test name
Test status
Simulation time 175183077 ps
CPU time 1.05 seconds
Started Feb 04 02:42:11 PM PST 24
Finished Feb 04 02:42:14 PM PST 24
Peak memory 195728 kb
Host smart-f4cd0a1c-699c-4e4e-94dc-ef86d0793276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103360991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2103360991
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.695692500
Short name T835
Test name
Test status
Simulation time 21643554 ps
CPU time 0.83 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:16 PM PST 24
Peak memory 195604 kb
Host smart-82abc82a-9d55-4d24-820f-1f2e5364ed9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695692500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.695692500
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.619874275
Short name T791
Test name
Test status
Simulation time 432281145 ps
CPU time 5.16 seconds
Started Feb 04 02:42:07 PM PST 24
Finished Feb 04 02:42:16 PM PST 24
Peak memory 197736 kb
Host smart-6d0a8807-44b1-4228-9518-e08499fe9234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619874275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.619874275
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.934977140
Short name T61
Test name
Test status
Simulation time 436187720 ps
CPU time 0.97 seconds
Started Feb 04 02:42:15 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 214480 kb
Host smart-1fbbfbae-4664-41ba-a196-a0d96aa94766
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934977140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.934977140
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1515200438
Short name T496
Test name
Test status
Simulation time 152878700 ps
CPU time 1.22 seconds
Started Feb 04 02:42:11 PM PST 24
Finished Feb 04 02:42:15 PM PST 24
Peak memory 195312 kb
Host smart-8906bece-10f3-4b0f-accc-02e674c35191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515200438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1515200438
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1152389220
Short name T812
Test name
Test status
Simulation time 49914029 ps
CPU time 0.69 seconds
Started Feb 04 02:42:06 PM PST 24
Finished Feb 04 02:42:10 PM PST 24
Peak memory 193968 kb
Host smart-f417282f-9d20-4b7c-8c52-13f3ba497fbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152389220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1152389220
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.163247273
Short name T313
Test name
Test status
Simulation time 70021810888 ps
CPU time 179.17 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:45:15 PM PST 24
Peak memory 197928 kb
Host smart-8e367e68-91ad-4c90-845b-cf4ea7f6da6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163247273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.163247273
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1570733277
Short name T72
Test name
Test status
Simulation time 11827011706 ps
CPU time 228.8 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:46:07 PM PST 24
Peak memory 198012 kb
Host smart-fc595330-a955-45b3-8611-49520192c0f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1570733277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1570733277
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.520811341
Short name T661
Test name
Test status
Simulation time 73049921 ps
CPU time 0.57 seconds
Started Feb 04 02:42:49 PM PST 24
Finished Feb 04 02:42:51 PM PST 24
Peak memory 193712 kb
Host smart-41fd307f-c561-4d0e-a7d4-8feecf2ddbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520811341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.520811341
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.203296883
Short name T666
Test name
Test status
Simulation time 201898177 ps
CPU time 0.92 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:55 PM PST 24
Peak memory 195476 kb
Host smart-5ab98b4c-805f-4c83-b817-74a83e2f3533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203296883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.203296883
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2016540867
Short name T780
Test name
Test status
Simulation time 1459956686 ps
CPU time 10.93 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 196704 kb
Host smart-2b9b1b45-d428-40f9-8f7e-1af87deb91bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016540867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2016540867
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3127118850
Short name T528
Test name
Test status
Simulation time 69250235 ps
CPU time 0.94 seconds
Started Feb 04 02:42:49 PM PST 24
Finished Feb 04 02:42:52 PM PST 24
Peak memory 196508 kb
Host smart-e10b21f9-af1d-497e-b7a4-cf9affd62396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127118850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3127118850
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3690319539
Short name T225
Test name
Test status
Simulation time 62963867 ps
CPU time 1.19 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:42:54 PM PST 24
Peak memory 195584 kb
Host smart-32772f92-4453-4e23-9dc2-a9a5be37073e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690319539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3690319539
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.765140559
Short name T774
Test name
Test status
Simulation time 312218908 ps
CPU time 1.12 seconds
Started Feb 04 02:42:49 PM PST 24
Finished Feb 04 02:42:52 PM PST 24
Peak memory 197664 kb
Host smart-c826b629-9131-4f08-8191-25580f4d7806
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765140559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.765140559
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3827481442
Short name T278
Test name
Test status
Simulation time 43274317 ps
CPU time 1.39 seconds
Started Feb 04 02:42:55 PM PST 24
Finished Feb 04 02:43:01 PM PST 24
Peak memory 195512 kb
Host smart-1182d5cf-e999-4cbd-ad07-fb57fd62b4ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827481442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3827481442
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2356300820
Short name T704
Test name
Test status
Simulation time 79083237 ps
CPU time 1.06 seconds
Started Feb 04 02:42:59 PM PST 24
Finished Feb 04 02:43:06 PM PST 24
Peak memory 195684 kb
Host smart-6640d248-cc96-42b7-8d12-79af7581740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356300820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2356300820
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4087516531
Short name T365
Test name
Test status
Simulation time 25919910 ps
CPU time 0.98 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:50 PM PST 24
Peak memory 195740 kb
Host smart-9339da04-00dc-4bbc-a431-d43f0e79d327
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087516531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4087516531
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4067173250
Short name T328
Test name
Test status
Simulation time 129422665 ps
CPU time 2.43 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:42:55 PM PST 24
Peak memory 197576 kb
Host smart-21d043dd-aefe-4397-8aa0-8b6c6cfe5fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067173250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4067173250
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3696509865
Short name T595
Test name
Test status
Simulation time 78359705 ps
CPU time 1.16 seconds
Started Feb 04 02:42:45 PM PST 24
Finished Feb 04 02:42:48 PM PST 24
Peak memory 195516 kb
Host smart-e21fb29f-7839-4408-aa30-8a8c7813fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696509865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3696509865
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2914899373
Short name T745
Test name
Test status
Simulation time 303572308 ps
CPU time 0.76 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:42:54 PM PST 24
Peak memory 194988 kb
Host smart-422c13d7-4c68-4b8e-962f-7e3d1579cea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914899373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2914899373
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1624507274
Short name T859
Test name
Test status
Simulation time 10647155902 ps
CPU time 153.5 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:45:28 PM PST 24
Peak memory 197900 kb
Host smart-18b4d099-77d6-4de7-ae6c-8a6016293f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624507274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1624507274
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1327382312
Short name T492
Test name
Test status
Simulation time 905903416604 ps
CPU time 2238.71 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 03:20:14 PM PST 24
Peak memory 198064 kb
Host smart-52d16c09-f7f1-4fa6-a670-327eb005e334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1327382312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1327382312
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3461564123
Short name T532
Test name
Test status
Simulation time 20796077 ps
CPU time 0.6 seconds
Started Feb 04 02:42:46 PM PST 24
Finished Feb 04 02:42:47 PM PST 24
Peak memory 194844 kb
Host smart-94259dc2-cb14-45ac-aaf3-a958d7351cf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461564123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3461564123
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.350380091
Short name T541
Test name
Test status
Simulation time 21313674 ps
CPU time 0.73 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:42:53 PM PST 24
Peak memory 195016 kb
Host smart-0b82127b-95a9-4dd8-85ad-8f7c9d319dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350380091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.350380091
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2675052108
Short name T229
Test name
Test status
Simulation time 96419138 ps
CPU time 4.79 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:53 PM PST 24
Peak memory 195796 kb
Host smart-6b16f1ca-212c-491f-bfd9-eced1764fb21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675052108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2675052108
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1309976601
Short name T355
Test name
Test status
Simulation time 76680030 ps
CPU time 0.92 seconds
Started Feb 04 02:42:59 PM PST 24
Finished Feb 04 02:43:06 PM PST 24
Peak memory 196888 kb
Host smart-46b4af70-f6d4-44a6-9de2-64a157583fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309976601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1309976601
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1883263132
Short name T680
Test name
Test status
Simulation time 42441921 ps
CPU time 0.91 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:49 PM PST 24
Peak memory 197024 kb
Host smart-03056f2e-b715-48ed-8f4a-80169e272c05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883263132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1883263132
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.295159457
Short name T262
Test name
Test status
Simulation time 44375180 ps
CPU time 1.77 seconds
Started Feb 04 02:42:48 PM PST 24
Finished Feb 04 02:42:52 PM PST 24
Peak memory 197712 kb
Host smart-bef64b67-5d2d-4edc-9ad3-f8f0764e42ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295159457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.295159457
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4193581975
Short name T386
Test name
Test status
Simulation time 31484556 ps
CPU time 0.88 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:49 PM PST 24
Peak memory 194976 kb
Host smart-554b6d75-be0e-4991-9e79-317d55d31eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193581975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4193581975
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3717223217
Short name T493
Test name
Test status
Simulation time 18517404 ps
CPU time 0.82 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:42:54 PM PST 24
Peak memory 195276 kb
Host smart-8050f11b-637f-4d38-8cf5-a73b4364e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717223217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3717223217
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2976500836
Short name T789
Test name
Test status
Simulation time 38357079 ps
CPU time 0.83 seconds
Started Feb 04 02:42:46 PM PST 24
Finished Feb 04 02:42:48 PM PST 24
Peak memory 196452 kb
Host smart-e71f49df-86cd-4ac9-b352-1629ff7bae54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976500836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2976500836
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2543078907
Short name T579
Test name
Test status
Simulation time 248164261 ps
CPU time 2.04 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 197740 kb
Host smart-373f4bd5-7923-4729-b44e-075056f8cb0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543078907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2543078907
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2455271793
Short name T779
Test name
Test status
Simulation time 58906793 ps
CPU time 0.93 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 195876 kb
Host smart-ac39351e-0ec7-4560-8ea9-900950fbb187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455271793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2455271793
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.453031606
Short name T691
Test name
Test status
Simulation time 116046678 ps
CPU time 0.77 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:49 PM PST 24
Peak memory 194940 kb
Host smart-70a847ce-bd53-4e05-93a4-56dc2bed5b63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453031606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.453031606
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1377099557
Short name T338
Test name
Test status
Simulation time 3665657189 ps
CPU time 98.66 seconds
Started Feb 04 02:42:48 PM PST 24
Finished Feb 04 02:44:29 PM PST 24
Peak memory 197916 kb
Host smart-f16a4b72-fefd-45ba-af21-8300c2e895f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377099557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1377099557
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1735549427
Short name T71
Test name
Test status
Simulation time 45994799215 ps
CPU time 313.9 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:48:07 PM PST 24
Peak memory 198056 kb
Host smart-d7c6a329-0f0c-4a4d-a4ca-1c5c1ea261ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1735549427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1735549427
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1716104643
Short name T388
Test name
Test status
Simulation time 11165463 ps
CPU time 0.57 seconds
Started Feb 04 02:42:54 PM PST 24
Finished Feb 04 02:42:58 PM PST 24
Peak memory 193684 kb
Host smart-68263741-bfae-4512-997b-b63d008b3384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716104643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1716104643
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2880962247
Short name T529
Test name
Test status
Simulation time 47248888 ps
CPU time 0.76 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 195164 kb
Host smart-4df3cfa6-e664-4788-8f69-fb2b4d94626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880962247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2880962247
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1624475728
Short name T783
Test name
Test status
Simulation time 925209444 ps
CPU time 22.25 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:43:15 PM PST 24
Peak memory 197760 kb
Host smart-c08b1c70-b206-4228-bc7c-7befaf9996d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624475728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1624475728
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1777440895
Short name T861
Test name
Test status
Simulation time 292078570 ps
CPU time 0.94 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 196188 kb
Host smart-77a7366a-9d9d-4cc5-a53f-fb45bc4eec34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777440895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1777440895
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4179118490
Short name T545
Test name
Test status
Simulation time 60433910 ps
CPU time 0.82 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 196620 kb
Host smart-e5d0b12b-ad8a-4cec-9151-6a26431c3355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179118490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4179118490
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1015293413
Short name T434
Test name
Test status
Simulation time 113464178 ps
CPU time 1.38 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 196768 kb
Host smart-c3a88b2b-b1a3-4d84-bfb6-b2d345a3efc8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015293413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1015293413
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2998032747
Short name T246
Test name
Test status
Simulation time 180331500 ps
CPU time 2.09 seconds
Started Feb 04 02:42:54 PM PST 24
Finished Feb 04 02:43:00 PM PST 24
Peak memory 196752 kb
Host smart-7bc85f20-a566-49ad-8056-dbe7ff71543d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998032747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2998032747
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3665231450
Short name T544
Test name
Test status
Simulation time 26155113 ps
CPU time 0.76 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:42:53 PM PST 24
Peak memory 195220 kb
Host smart-f648d3ec-3e9a-42ec-a8f5-2b76753e4613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665231450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3665231450
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.439436593
Short name T876
Test name
Test status
Simulation time 65406555 ps
CPU time 0.79 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 196412 kb
Host smart-e26cc045-4f74-4fa0-b236-d7353db71931
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439436593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.439436593
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2860485656
Short name T806
Test name
Test status
Simulation time 84469726 ps
CPU time 3.71 seconds
Started Feb 04 02:42:54 PM PST 24
Finished Feb 04 02:43:02 PM PST 24
Peak memory 197752 kb
Host smart-d2961ca7-73af-4e8c-b04d-abbfb8a2de05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860485656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2860485656
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3261856779
Short name T421
Test name
Test status
Simulation time 100733517 ps
CPU time 0.87 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 195180 kb
Host smart-8ee9251b-9a40-4f3c-b67f-622789309bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261856779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3261856779
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2021519008
Short name T638
Test name
Test status
Simulation time 34615633 ps
CPU time 1.02 seconds
Started Feb 04 02:42:49 PM PST 24
Finished Feb 04 02:42:52 PM PST 24
Peak memory 195252 kb
Host smart-b5d7d184-0e17-40c0-ae70-5ed3cab0f7ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021519008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2021519008
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1648745847
Short name T706
Test name
Test status
Simulation time 31778611922 ps
CPU time 196.37 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:46:09 PM PST 24
Peak memory 197880 kb
Host smart-2254f986-cca0-4031-8a97-cccdb0c09ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648745847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1648745847
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.4088058099
Short name T315
Test name
Test status
Simulation time 37575260202 ps
CPU time 512.13 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:51:35 PM PST 24
Peak memory 198132 kb
Host smart-62fe0a4e-33bc-4fbf-88b9-17abcddf2746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4088058099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.4088058099
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3773713267
Short name T802
Test name
Test status
Simulation time 11552364 ps
CPU time 0.58 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:02 PM PST 24
Peak memory 193660 kb
Host smart-5c994e77-7c89-43ae-889f-1237aaa0cd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773713267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3773713267
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3781228794
Short name T725
Test name
Test status
Simulation time 81409448 ps
CPU time 0.71 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:56 PM PST 24
Peak memory 194976 kb
Host smart-3fd0920f-d31b-42f4-8cf1-d4de17a6c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781228794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3781228794
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.926595697
Short name T574
Test name
Test status
Simulation time 3804040750 ps
CPU time 26.27 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:29 PM PST 24
Peak memory 196568 kb
Host smart-087b713f-69cb-4df6-b7b0-c3ca22ebac6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926595697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.926595697
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1420747387
Short name T363
Test name
Test status
Simulation time 65348080 ps
CPU time 0.86 seconds
Started Feb 04 02:42:55 PM PST 24
Finished Feb 04 02:43:01 PM PST 24
Peak memory 195804 kb
Host smart-1935848a-9aeb-408b-95f6-b9130e2d1f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420747387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1420747387
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2827660130
Short name T486
Test name
Test status
Simulation time 223888680 ps
CPU time 1.06 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:55 PM PST 24
Peak memory 196204 kb
Host smart-fe34844d-851a-4e34-984b-cdbaa9166ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827660130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2827660130
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2038494507
Short name T259
Test name
Test status
Simulation time 150227144 ps
CPU time 3.07 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:59 PM PST 24
Peak memory 197836 kb
Host smart-23761a29-4dfb-4aee-9a89-1572e4114e17
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038494507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2038494507
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.213414031
Short name T703
Test name
Test status
Simulation time 297694384 ps
CPU time 3.42 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:59 PM PST 24
Peak memory 196892 kb
Host smart-2c6c6af8-fed2-4b68-aad4-5cd6b815d3bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213414031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
213414031
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.42545096
Short name T413
Test name
Test status
Simulation time 210121621 ps
CPU time 1.33 seconds
Started Feb 04 02:42:55 PM PST 24
Finished Feb 04 02:43:02 PM PST 24
Peak memory 196828 kb
Host smart-916c8880-317d-41ec-be35-f050ce060c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42545096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.42545096
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3357622624
Short name T487
Test name
Test status
Simulation time 32969705 ps
CPU time 0.95 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 195592 kb
Host smart-ae2fd4e9-ad3f-47c1-9c16-ba32d7645a1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357622624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3357622624
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.101555664
Short name T796
Test name
Test status
Simulation time 248114278 ps
CPU time 1.78 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 197684 kb
Host smart-e9689b9f-7dd6-404b-ad0f-754c615cd2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101555664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.101555664
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4143667877
Short name T723
Test name
Test status
Simulation time 34282147 ps
CPU time 0.88 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 195708 kb
Host smart-ea0ac89b-aeb8-4d9e-a41a-04894e578d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143667877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4143667877
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2195789000
Short name T437
Test name
Test status
Simulation time 25326018 ps
CPU time 0.96 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 195448 kb
Host smart-c0aa8f5e-a502-48c3-a8f0-d2ee8b61abb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195789000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2195789000
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3610566942
Short name T877
Test name
Test status
Simulation time 41887756809 ps
CPU time 106.68 seconds
Started Feb 04 02:42:50 PM PST 24
Finished Feb 04 02:44:39 PM PST 24
Peak memory 197936 kb
Host smart-174825a7-5622-4324-a088-94ee05df84cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610566942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3610566942
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3460994237
Short name T546
Test name
Test status
Simulation time 60135496799 ps
CPU time 794.35 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:56:09 PM PST 24
Peak memory 197956 kb
Host smart-084a63d5-d64e-475a-afb2-d07509815edc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3460994237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3460994237
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1768326731
Short name T465
Test name
Test status
Simulation time 21083315 ps
CPU time 0.6 seconds
Started Feb 04 02:43:04 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 194640 kb
Host smart-8020cdab-091f-48fb-ad1a-2d2abf3b1cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768326731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1768326731
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2099186739
Short name T655
Test name
Test status
Simulation time 24016988 ps
CPU time 0.78 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 195968 kb
Host smart-7507a48d-eaeb-49e5-b228-f20cfd1574e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099186739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2099186739
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2831926362
Short name T283
Test name
Test status
Simulation time 393673731 ps
CPU time 21.1 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 195384 kb
Host smart-e448afe3-4458-4dea-a6a0-4233ab3ac36a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831926362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2831926362
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1950434102
Short name T407
Test name
Test status
Simulation time 102629172 ps
CPU time 1.1 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 196352 kb
Host smart-6d4a8755-cbb7-4a30-89b9-cf0bab6fb9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950434102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1950434102
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1483429640
Short name T888
Test name
Test status
Simulation time 164364887 ps
CPU time 0.89 seconds
Started Feb 04 02:42:54 PM PST 24
Finished Feb 04 02:42:59 PM PST 24
Peak memory 195276 kb
Host smart-a9d1bf7f-9225-4ba9-85e3-0ae09c99327b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483429640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1483429640
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.4066982264
Short name T810
Test name
Test status
Simulation time 71429472 ps
CPU time 2.69 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:06 PM PST 24
Peak memory 197816 kb
Host smart-47055505-7584-42ac-b706-b87641003527
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066982264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.4066982264
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1681877492
Short name T400
Test name
Test status
Simulation time 2201598247 ps
CPU time 3.38 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:07 PM PST 24
Peak memory 197128 kb
Host smart-ebb67a9c-95a3-45a0-8e01-a88bb290dc41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681877492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1681877492
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2612350584
Short name T887
Test name
Test status
Simulation time 34355084 ps
CPU time 1.28 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 196336 kb
Host smart-f88df144-7abb-4a89-8dc1-69a2b675e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612350584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2612350584
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3737494152
Short name T767
Test name
Test status
Simulation time 79014918 ps
CPU time 0.73 seconds
Started Feb 04 02:42:56 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 194824 kb
Host smart-04217fff-7532-46c5-a1eb-651b1f33c108
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737494152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3737494152
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2106084701
Short name T446
Test name
Test status
Simulation time 59924467 ps
CPU time 1.29 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:10 PM PST 24
Peak memory 197644 kb
Host smart-3a784244-d491-4196-953c-c842ee189ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106084701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2106084701
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3925203107
Short name T870
Test name
Test status
Simulation time 249283428 ps
CPU time 1.12 seconds
Started Feb 04 02:42:57 PM PST 24
Finished Feb 04 02:43:04 PM PST 24
Peak memory 195592 kb
Host smart-bbf00360-2f8b-48f3-895f-aa4682c37b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925203107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3925203107
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.430999299
Short name T473
Test name
Test status
Simulation time 308412418 ps
CPU time 1.28 seconds
Started Feb 04 02:42:53 PM PST 24
Finished Feb 04 02:42:58 PM PST 24
Peak memory 196444 kb
Host smart-21d18e0f-e8c3-4736-aced-981368c2ff81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430999299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.430999299
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.255238522
Short name T616
Test name
Test status
Simulation time 22411255197 ps
CPU time 70.17 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:44:21 PM PST 24
Peak memory 197892 kb
Host smart-10651335-9160-4ef1-ab3a-a1030bc6aab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255238522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.255238522
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2752978213
Short name T537
Test name
Test status
Simulation time 119169168500 ps
CPU time 2052.99 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 03:17:33 PM PST 24
Peak memory 198004 kb
Host smart-38949959-235b-4cca-b2b6-e31b52ded09a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2752978213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2752978213
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3196740541
Short name T716
Test name
Test status
Simulation time 13637282 ps
CPU time 0.55 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 193784 kb
Host smart-c84a4fa0-bf1b-44e6-8ca6-213743da76e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196740541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3196740541
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1349420439
Short name T589
Test name
Test status
Simulation time 43621891 ps
CPU time 0.71 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:11 PM PST 24
Peak memory 193948 kb
Host smart-091fe08a-f79b-4f96-a3f5-1883764b8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349420439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1349420439
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.536287318
Short name T507
Test name
Test status
Simulation time 2051755670 ps
CPU time 25.3 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 196332 kb
Host smart-57ed2ec6-7cff-4021-a90a-d9a1a22fd264
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536287318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.536287318
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.573770342
Short name T221
Test name
Test status
Simulation time 223007898 ps
CPU time 0.83 seconds
Started Feb 04 02:43:00 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 195852 kb
Host smart-e3f18cb4-87c9-4d43-920f-c5c83be734a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573770342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.573770342
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1021399692
Short name T698
Test name
Test status
Simulation time 36216223 ps
CPU time 0.68 seconds
Started Feb 04 02:43:04 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 194792 kb
Host smart-c11b89cd-f56a-4a8a-8055-8c8884ee2080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021399692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1021399692
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.888312255
Short name T335
Test name
Test status
Simulation time 330559460 ps
CPU time 2.58 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 196208 kb
Host smart-81a664df-9b27-4bc2-bc61-2fe0237246d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888312255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.888312255
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.593044004
Short name T627
Test name
Test status
Simulation time 54759534 ps
CPU time 1.78 seconds
Started Feb 04 02:42:59 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 196696 kb
Host smart-3af2a289-0798-424b-b955-e862fe89d045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593044004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
593044004
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1568565264
Short name T659
Test name
Test status
Simulation time 28361027 ps
CPU time 0.97 seconds
Started Feb 04 02:43:00 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 195996 kb
Host smart-3d8d08b0-af00-477e-ad69-53f6af9de156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568565264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1568565264
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3707812662
Short name T395
Test name
Test status
Simulation time 14302726 ps
CPU time 0.64 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 194144 kb
Host smart-455652fa-cb85-484a-9e60-09296fe1ce18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707812662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3707812662
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.253695294
Short name T249
Test name
Test status
Simulation time 333857423 ps
CPU time 3.87 seconds
Started Feb 04 02:43:04 PM PST 24
Finished Feb 04 02:43:15 PM PST 24
Peak memory 197628 kb
Host smart-9be1fe78-ce23-439f-9851-a1ea3709231f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253695294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.253695294
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.863857543
Short name T501
Test name
Test status
Simulation time 28583792 ps
CPU time 0.86 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 196184 kb
Host smart-767d4817-7e1b-4fe9-8a6f-d09c1df55e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863857543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.863857543
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3203700876
Short name T735
Test name
Test status
Simulation time 57508209 ps
CPU time 1.13 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:10 PM PST 24
Peak memory 195472 kb
Host smart-19d52dab-aee2-4043-9206-2f0fb5de39d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203700876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3203700876
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2720836135
Short name T508
Test name
Test status
Simulation time 4233884893 ps
CPU time 83.9 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:44:33 PM PST 24
Peak memory 197940 kb
Host smart-0da45b56-f621-4cce-bf04-6f5392ba5b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720836135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2720836135
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3859084265
Short name T832
Test name
Test status
Simulation time 68603642039 ps
CPU time 1836.11 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 03:13:46 PM PST 24
Peak memory 198076 kb
Host smart-0bb48ffb-fddc-4f32-a474-71ee5ad98380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3859084265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3859084265
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2093990553
Short name T369
Test name
Test status
Simulation time 96213657 ps
CPU time 0.58 seconds
Started Feb 04 02:43:01 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 193804 kb
Host smart-2a6baabe-d9dc-4d9e-bd95-49d333e090ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093990553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2093990553
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2194520154
Short name T620
Test name
Test status
Simulation time 72416450 ps
CPU time 0.91 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195764 kb
Host smart-3fd1a117-42d4-4d16-bcc1-0237d3d8e029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194520154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2194520154
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3276124111
Short name T695
Test name
Test status
Simulation time 1435482402 ps
CPU time 20.24 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:43:31 PM PST 24
Peak memory 196688 kb
Host smart-d7190732-9c7b-4599-8057-165b560ccdc4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276124111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3276124111
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2742762218
Short name T427
Test name
Test status
Simulation time 125168534 ps
CPU time 0.7 seconds
Started Feb 04 02:43:01 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 194588 kb
Host smart-8e7e35b7-6c32-4671-9eca-1cd90331ecb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742762218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2742762218
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.8419055
Short name T719
Test name
Test status
Simulation time 15314613 ps
CPU time 0.63 seconds
Started Feb 04 02:43:01 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 194028 kb
Host smart-f8d3360c-8c24-481d-bc97-2936ec7b3c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8419055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.8419055
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2829038282
Short name T461
Test name
Test status
Simulation time 393393878 ps
CPU time 2.8 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 196688 kb
Host smart-e3b1f7f0-cf2d-44e1-9457-1985f8abf88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829038282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2829038282
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2134418335
Short name T549
Test name
Test status
Simulation time 26099052 ps
CPU time 0.81 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:43:11 PM PST 24
Peak memory 196032 kb
Host smart-1932084f-93e3-41e8-9356-317153018fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134418335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2134418335
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.538525048
Short name T581
Test name
Test status
Simulation time 36997693 ps
CPU time 1.04 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 196276 kb
Host smart-5000adbf-1e60-41c5-bcba-0ea1ccdcd004
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538525048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.538525048
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4292924169
Short name T514
Test name
Test status
Simulation time 51444657 ps
CPU time 2.24 seconds
Started Feb 04 02:43:06 PM PST 24
Finished Feb 04 02:43:15 PM PST 24
Peak memory 197672 kb
Host smart-d65347ed-a18e-4e4c-8950-8092b64e10e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292924169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4292924169
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1986229369
Short name T458
Test name
Test status
Simulation time 133946544 ps
CPU time 1.35 seconds
Started Feb 04 02:42:59 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 195996 kb
Host smart-e1aa4b1c-ba6b-400a-9b4e-a3d3c050b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986229369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1986229369
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3485894760
Short name T741
Test name
Test status
Simulation time 43672458 ps
CPU time 1.32 seconds
Started Feb 04 02:43:00 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 196660 kb
Host smart-e5587c0c-c914-4841-b0ee-6fd680d5906b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485894760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3485894760
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3836072544
Short name T569
Test name
Test status
Simulation time 23478158807 ps
CPU time 182.81 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:46:13 PM PST 24
Peak memory 197928 kb
Host smart-71561a22-8447-49b5-ba27-767ebac80816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836072544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3836072544
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.675896226
Short name T485
Test name
Test status
Simulation time 78714539855 ps
CPU time 1938.17 seconds
Started Feb 04 02:43:00 PM PST 24
Finished Feb 04 03:15:26 PM PST 24
Peak memory 197988 kb
Host smart-794c6885-1f0e-4f63-afa6-7d93e8f9d931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=675896226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.675896226
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.303329262
Short name T594
Test name
Test status
Simulation time 20661835 ps
CPU time 0.56 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 193688 kb
Host smart-dfbb4d0f-bc9c-4d01-abd3-c13ea8bef5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303329262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.303329262
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3262102161
Short name T727
Test name
Test status
Simulation time 27113567 ps
CPU time 0.77 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 195248 kb
Host smart-e8807749-3cb7-4de0-9c1c-e5d433f23233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262102161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3262102161
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2240949508
Short name T720
Test name
Test status
Simulation time 327577104 ps
CPU time 9.35 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:30 PM PST 24
Peak memory 196708 kb
Host smart-435b6faa-e28a-4a95-b793-196495de50ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240949508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2240949508
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.588576097
Short name T300
Test name
Test status
Simulation time 192952075 ps
CPU time 1.08 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 196372 kb
Host smart-042b3593-3536-4fa4-960a-dfe6ca24472b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588576097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.588576097
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3972011891
Short name T572
Test name
Test status
Simulation time 44401045 ps
CPU time 0.92 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:23 PM PST 24
Peak memory 196580 kb
Host smart-37725730-3edb-4349-8f73-c531a51f606d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972011891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3972011891
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1069034618
Short name T670
Test name
Test status
Simulation time 60906459 ps
CPU time 2.33 seconds
Started Feb 04 02:43:05 PM PST 24
Finished Feb 04 02:43:14 PM PST 24
Peak memory 197756 kb
Host smart-c5dd571f-301c-4b2b-9518-50b82bc16735
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069034618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1069034618
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1385868081
Short name T578
Test name
Test status
Simulation time 134939778 ps
CPU time 2.62 seconds
Started Feb 04 02:42:59 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 196708 kb
Host smart-ffb43c3b-49bd-4b73-961b-727cff8c5307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385868081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1385868081
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.834255904
Short name T872
Test name
Test status
Simulation time 121214182 ps
CPU time 0.69 seconds
Started Feb 04 02:43:01 PM PST 24
Finished Feb 04 02:43:10 PM PST 24
Peak memory 194236 kb
Host smart-48ede8b4-ce88-4a1b-abf2-b3a38a3f9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834255904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.834255904
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1656388236
Short name T410
Test name
Test status
Simulation time 41183593 ps
CPU time 1.04 seconds
Started Feb 04 02:43:02 PM PST 24
Finished Feb 04 02:43:10 PM PST 24
Peak memory 196384 kb
Host smart-8c1776d5-2057-4f2d-871e-6a2af82a926d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656388236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1656388236
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1816977065
Short name T539
Test name
Test status
Simulation time 1841617252 ps
CPU time 6.29 seconds
Started Feb 04 02:43:07 PM PST 24
Finished Feb 04 02:43:19 PM PST 24
Peak memory 197756 kb
Host smart-c22e1330-f170-4396-911f-e2b10ae545d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816977065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1816977065
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.4135091025
Short name T547
Test name
Test status
Simulation time 402038223 ps
CPU time 0.98 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 195652 kb
Host smart-3669efce-84af-412f-b062-9617b5b8edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135091025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4135091025
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3078880175
Short name T788
Test name
Test status
Simulation time 49751579 ps
CPU time 1.39 seconds
Started Feb 04 02:43:03 PM PST 24
Finished Feb 04 02:43:12 PM PST 24
Peak memory 195240 kb
Host smart-a3ad36ff-3c90-4fda-b1a2-33a5ffc36a5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078880175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3078880175
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1678004310
Short name T292
Test name
Test status
Simulation time 68193369625 ps
CPU time 192.57 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:46:33 PM PST 24
Peak memory 197900 kb
Host smart-4da8a032-7d5c-42f5-9ed1-5842879c3aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678004310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1678004310
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.4150394100
Short name T662
Test name
Test status
Simulation time 20505587246 ps
CPU time 637.87 seconds
Started Feb 04 02:43:00 PM PST 24
Finished Feb 04 02:53:46 PM PST 24
Peak memory 198132 kb
Host smart-f47675d6-215a-4ced-b8f4-a8310aacfb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4150394100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.4150394100
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4287811032
Short name T561
Test name
Test status
Simulation time 19631594 ps
CPU time 0.58 seconds
Started Feb 04 02:43:17 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 192556 kb
Host smart-21377af2-f7d1-4c7b-b49e-651c2819300a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287811032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4287811032
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3666217533
Short name T232
Test name
Test status
Simulation time 21875941 ps
CPU time 0.65 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 193848 kb
Host smart-13538429-4a8e-4788-8637-329059391b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666217533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3666217533
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2153100881
Short name T818
Test name
Test status
Simulation time 687615991 ps
CPU time 23 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 196512 kb
Host smart-92a7577c-4808-468a-86fb-c1e8cf390bbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153100881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2153100881
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.693508067
Short name T509
Test name
Test status
Simulation time 309687224 ps
CPU time 1.21 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 196352 kb
Host smart-87d2ea19-9962-48ae-b43a-574daca04c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693508067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.693508067
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2399899657
Short name T340
Test name
Test status
Simulation time 73210497 ps
CPU time 1.37 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:25 PM PST 24
Peak memory 196612 kb
Host smart-f83317e5-3108-41e3-9233-610aca25688c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399899657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2399899657
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.202539608
Short name T679
Test name
Test status
Simulation time 93076128 ps
CPU time 3.24 seconds
Started Feb 04 02:43:08 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 196116 kb
Host smart-f915a6c1-525c-4166-85dc-9f202903b357
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202539608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.202539608
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3662906031
Short name T320
Test name
Test status
Simulation time 461546318 ps
CPU time 3.58 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 196596 kb
Host smart-6d0e917a-99be-4819-aba1-0898dc86bfd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662906031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3662906031
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3991108186
Short name T224
Test name
Test status
Simulation time 60489877 ps
CPU time 0.79 seconds
Started Feb 04 02:42:58 PM PST 24
Finished Feb 04 02:43:06 PM PST 24
Peak memory 195252 kb
Host smart-7b7268ab-2598-4b11-a73e-0dd35bfd2263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991108186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3991108186
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3242182625
Short name T879
Test name
Test status
Simulation time 113655330 ps
CPU time 0.9 seconds
Started Feb 04 02:43:01 PM PST 24
Finished Feb 04 02:43:09 PM PST 24
Peak memory 195736 kb
Host smart-268004dd-0a42-4315-bc9f-3b30c8a5b366
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242182625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3242182625
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.679627266
Short name T786
Test name
Test status
Simulation time 400519459 ps
CPU time 4.89 seconds
Started Feb 04 02:43:09 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 197760 kb
Host smart-8ab97964-98cc-4da1-93f5-67bf8bd0a39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679627266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.679627266
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1176572678
Short name T729
Test name
Test status
Simulation time 210573962 ps
CPU time 0.86 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195012 kb
Host smart-e12af43d-a79e-4d37-b94e-c2e0b5b45d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176572678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1176572678
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1895618583
Short name T343
Test name
Test status
Simulation time 374202810 ps
CPU time 1.17 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195472 kb
Host smart-53da5f66-91a5-4a5b-8256-5f4bc30b0400
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895618583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1895618583
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3421296624
Short name T261
Test name
Test status
Simulation time 6797428527 ps
CPU time 90.23 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:44:51 PM PST 24
Peak memory 197940 kb
Host smart-5e4d29d3-b7b4-4112-9ff6-1b2972cfdae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421296624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3421296624
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2518807921
Short name T84
Test name
Test status
Simulation time 114790909034 ps
CPU time 1688.46 seconds
Started Feb 04 02:43:07 PM PST 24
Finished Feb 04 03:11:21 PM PST 24
Peak memory 198032 kb
Host smart-6ec43f6c-95ad-4b64-847e-8d48e353c1c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2518807921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2518807921
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1920714733
Short name T853
Test name
Test status
Simulation time 12863509 ps
CPU time 0.57 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 193308 kb
Host smart-3055f2b5-c4f7-4d3f-b19d-ede31b32183b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920714733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1920714733
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.485182445
Short name T498
Test name
Test status
Simulation time 28835687 ps
CPU time 0.73 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 192760 kb
Host smart-cb316b8a-67bc-429b-a19d-9a03f1fa499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485182445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.485182445
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3321543941
Short name T785
Test name
Test status
Simulation time 770980930 ps
CPU time 20.83 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 197468 kb
Host smart-85286ea9-ba3c-4670-9863-ecba2a40096d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321543941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3321543941
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1109254524
Short name T748
Test name
Test status
Simulation time 29014709 ps
CPU time 0.68 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 195116 kb
Host smart-e70cc24f-8359-43be-b0c8-b76f075c7e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109254524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1109254524
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4086877284
Short name T701
Test name
Test status
Simulation time 48716764 ps
CPU time 1.35 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195524 kb
Host smart-cf83a8ca-8b27-4f3d-88cb-c5369e2b600a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086877284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4086877284
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3494617232
Short name T519
Test name
Test status
Simulation time 81478566 ps
CPU time 3.09 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:23 PM PST 24
Peak memory 197912 kb
Host smart-8a5437f0-c6f7-415f-b273-9d92f10916f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494617232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3494617232
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1601380476
Short name T705
Test name
Test status
Simulation time 77151089 ps
CPU time 2.59 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:28 PM PST 24
Peak memory 197700 kb
Host smart-d308dd7b-538a-4098-9ac7-82c8faafc115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601380476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1601380476
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2904267739
Short name T435
Test name
Test status
Simulation time 23633730 ps
CPU time 0.96 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 195768 kb
Host smart-be56a6c6-92b6-4212-abe1-6e5b35609217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904267739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2904267739
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2421627301
Short name T744
Test name
Test status
Simulation time 30678842 ps
CPU time 1.14 seconds
Started Feb 04 02:43:18 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 196584 kb
Host smart-04053ec3-5451-4b73-9688-a5027e1a7fb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421627301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2421627301
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3433066824
Short name T438
Test name
Test status
Simulation time 332987074 ps
CPU time 2.42 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:28 PM PST 24
Peak memory 197628 kb
Host smart-0f2c59a6-f184-4cbd-8c1c-ff0f14a0c4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433066824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3433066824
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3095722752
Short name T860
Test name
Test status
Simulation time 93032689 ps
CPU time 0.93 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 195252 kb
Host smart-173dfcb1-76f4-42a3-a0e2-08f1defb5492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095722752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3095722752
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1481734952
Short name T867
Test name
Test status
Simulation time 79473997 ps
CPU time 1.07 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 195444 kb
Host smart-e392659c-c24d-4378-ac1f-d6ee532afef3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481734952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1481734952
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.592561570
Short name T842
Test name
Test status
Simulation time 35152448042 ps
CPU time 100.14 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:45:03 PM PST 24
Peak memory 197600 kb
Host smart-4c6ebb08-d2b0-4d73-8473-61bc66c7445e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592561570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.592561570
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4013255589
Short name T393
Test name
Test status
Simulation time 65286292518 ps
CPU time 791.48 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:56:33 PM PST 24
Peak memory 197988 kb
Host smart-7dc2fe2f-c242-412b-822f-d550be7c8319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4013255589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4013255589
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2671082108
Short name T830
Test name
Test status
Simulation time 27030246 ps
CPU time 0.58 seconds
Started Feb 04 02:42:21 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 194388 kb
Host smart-5814104c-950a-4b46-813c-761305175b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671082108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2671082108
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1347843459
Short name T475
Test name
Test status
Simulation time 38811542 ps
CPU time 0.64 seconds
Started Feb 04 02:42:12 PM PST 24
Finished Feb 04 02:42:15 PM PST 24
Peak memory 194632 kb
Host smart-f4567826-91d7-4702-a3f4-a511864a6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347843459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1347843459
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1541281804
Short name T310
Test name
Test status
Simulation time 10559358965 ps
CPU time 26.85 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:53 PM PST 24
Peak memory 197712 kb
Host smart-1b8af0cf-3b49-41e7-841c-3e0ddd63624c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541281804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1541281804
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2871668361
Short name T334
Test name
Test status
Simulation time 127787499 ps
CPU time 0.95 seconds
Started Feb 04 02:42:12 PM PST 24
Finished Feb 04 02:42:16 PM PST 24
Peak memory 196332 kb
Host smart-29b4fd3d-8aca-4b6a-80b2-b3840ed34772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871668361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2871668361
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1409879324
Short name T700
Test name
Test status
Simulation time 71559067 ps
CPU time 0.81 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 195320 kb
Host smart-1d0d5ee2-01e6-424b-aa52-0a8e777419fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409879324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1409879324
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4165003204
Short name T799
Test name
Test status
Simulation time 139361920 ps
CPU time 1.23 seconds
Started Feb 04 02:42:16 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 196448 kb
Host smart-d7d5d1f0-b617-4dcb-a5cb-d80bba9106a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165003204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4165003204
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.415197315
Short name T721
Test name
Test status
Simulation time 571217815 ps
CPU time 3.26 seconds
Started Feb 04 02:42:23 PM PST 24
Finished Feb 04 02:42:31 PM PST 24
Peak memory 196800 kb
Host smart-fc4d0a00-4e4c-4fa7-8cae-cb156eead72d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415197315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.415197315
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4199302569
Short name T510
Test name
Test status
Simulation time 128559605 ps
CPU time 0.8 seconds
Started Feb 04 02:42:13 PM PST 24
Finished Feb 04 02:42:17 PM PST 24
Peak memory 196256 kb
Host smart-51a975cb-74ae-4a61-8e85-6210bd9170cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199302569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4199302569
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.112755774
Short name T775
Test name
Test status
Simulation time 60780229 ps
CPU time 0.88 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 195956 kb
Host smart-9e7a2977-49b2-469d-bc44-fa40286426a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112755774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.112755774
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3489367667
Short name T560
Test name
Test status
Simulation time 120862084 ps
CPU time 2.39 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:29 PM PST 24
Peak memory 197696 kb
Host smart-277970e6-71d0-407c-8b35-81678bc5563e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489367667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3489367667
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4079335272
Short name T62
Test name
Test status
Simulation time 35418351 ps
CPU time 0.77 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 213316 kb
Host smart-d8604f9d-874d-4363-9774-5280a2c01026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079335272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4079335272
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2383904557
Short name T801
Test name
Test status
Simulation time 405397468 ps
CPU time 1.13 seconds
Started Feb 04 02:42:12 PM PST 24
Finished Feb 04 02:42:16 PM PST 24
Peak memory 195316 kb
Host smart-56a92453-f70c-4812-bf6b-70f0fb816caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383904557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2383904557
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.373878697
Short name T231
Test name
Test status
Simulation time 105215160 ps
CPU time 1.24 seconds
Started Feb 04 02:42:14 PM PST 24
Finished Feb 04 02:42:19 PM PST 24
Peak memory 196572 kb
Host smart-9f46ad9d-e062-48ed-b508-ef1a65b52d05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373878697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.373878697
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3705217342
Short name T342
Test name
Test status
Simulation time 14858915937 ps
CPU time 150.01 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:44:56 PM PST 24
Peak memory 197892 kb
Host smart-09f04ba3-9eb1-4c68-a039-706d5c8853ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705217342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3705217342
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2259917870
Short name T732
Test name
Test status
Simulation time 1616905310774 ps
CPU time 1528.26 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 03:07:55 PM PST 24
Peak memory 197956 kb
Host smart-342caa0f-b170-48d3-ad6f-3f5b0b13fcf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2259917870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2259917870
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3526420160
Short name T471
Test name
Test status
Simulation time 46156558 ps
CPU time 0.71 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 194696 kb
Host smart-e080b60a-1e8a-4fd8-b463-87d8abfebccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526420160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3526420160
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2938660543
Short name T290
Test name
Test status
Simulation time 183231291 ps
CPU time 6.16 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:29 PM PST 24
Peak memory 196700 kb
Host smart-9e0bf339-1950-4abc-b485-f4c6fad3e8e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938660543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2938660543
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1438393881
Short name T237
Test name
Test status
Simulation time 209090843 ps
CPU time 0.94 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 197028 kb
Host smart-42b84638-b2ba-47e5-9fd9-feb24ac6af3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438393881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1438393881
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1997025492
Short name T602
Test name
Test status
Simulation time 43794846 ps
CPU time 0.78 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 195416 kb
Host smart-4dff9b8d-af95-4084-b46a-894244cc88fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997025492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1997025492
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2768447341
Short name T308
Test name
Test status
Simulation time 77101630 ps
CPU time 3.01 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 196996 kb
Host smart-853512d9-2b4f-4328-b046-628e235f05cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768447341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2768447341
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3631432584
Short name T869
Test name
Test status
Simulation time 85261543 ps
CPU time 2.37 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:23 PM PST 24
Peak memory 196976 kb
Host smart-79e9f949-3c1d-45e2-8cbe-b6c55257bc1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631432584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3631432584
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.400584800
Short name T856
Test name
Test status
Simulation time 30706206 ps
CPU time 1.13 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 196460 kb
Host smart-fe3bb626-81a9-474b-ab81-460456543e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400584800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.400584800
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4280665521
Short name T337
Test name
Test status
Simulation time 48460446 ps
CPU time 0.94 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 195748 kb
Host smart-5b1f3c08-7625-49df-aff0-18288a7af7d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280665521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4280665521
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3134936207
Short name T324
Test name
Test status
Simulation time 212436950 ps
CPU time 2.84 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:28 PM PST 24
Peak memory 197804 kb
Host smart-d70e2097-dbfb-4cbd-8dd3-1ec6b80aae72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134936207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3134936207
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.810585960
Short name T448
Test name
Test status
Simulation time 108426013 ps
CPU time 1 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:21 PM PST 24
Peak memory 196188 kb
Host smart-75092c9e-0074-41ad-bdc8-1bddf824fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810585960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.810585960
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.448428926
Short name T275
Test name
Test status
Simulation time 54261400 ps
CPU time 1.16 seconds
Started Feb 04 02:43:15 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 195268 kb
Host smart-f943850a-50dc-4018-8d0f-d18cf48f95b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448428926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.448428926
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.285929343
Short name T817
Test name
Test status
Simulation time 21357762058 ps
CPU time 126.22 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:45:26 PM PST 24
Peak memory 197908 kb
Host smart-59de47e7-e4ea-4879-9d66-537ec0d78a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285929343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.285929343
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2543319397
Short name T750
Test name
Test status
Simulation time 26916860567 ps
CPU time 392.19 seconds
Started Feb 04 02:43:16 PM PST 24
Finished Feb 04 02:49:58 PM PST 24
Peak memory 197984 kb
Host smart-18918204-e0bc-4e75-9978-748d900cd371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2543319397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2543319397
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3797459191
Short name T646
Test name
Test status
Simulation time 20014948 ps
CPU time 0.58 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 194444 kb
Host smart-72a64502-866d-4acb-aea0-ac729fb28341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797459191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3797459191
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.24731285
Short name T630
Test name
Test status
Simulation time 39328917 ps
CPU time 0.85 seconds
Started Feb 04 02:43:09 PM PST 24
Finished Feb 04 02:43:20 PM PST 24
Peak memory 195012 kb
Host smart-82abeb2b-b40f-41c0-97d1-0866759439b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24731285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.24731285
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.110908688
Short name T827
Test name
Test status
Simulation time 1293248227 ps
CPU time 9.34 seconds
Started Feb 04 02:43:09 PM PST 24
Finished Feb 04 02:43:28 PM PST 24
Peak memory 195324 kb
Host smart-b8348463-686a-454b-993a-c1bb7aae020a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110908688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.110908688
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.401353935
Short name T794
Test name
Test status
Simulation time 129312760 ps
CPU time 0.72 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195280 kb
Host smart-4777034b-2b18-4a10-a4e2-f29c4b61ed43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401353935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.401353935
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.217803450
Short name T382
Test name
Test status
Simulation time 177030180 ps
CPU time 0.78 seconds
Started Feb 04 02:43:08 PM PST 24
Finished Feb 04 02:43:19 PM PST 24
Peak memory 196080 kb
Host smart-2439c9b4-2130-49de-9ecd-b1c370be622c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217803450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.217803450
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4197438913
Short name T399
Test name
Test status
Simulation time 112742257 ps
CPU time 2.32 seconds
Started Feb 04 02:43:12 PM PST 24
Finished Feb 04 02:43:25 PM PST 24
Peak memory 196248 kb
Host smart-4405fb46-0dae-4123-8dd3-0970952fa08c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197438913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4197438913
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1942339407
Short name T747
Test name
Test status
Simulation time 138930267 ps
CPU time 2.21 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 196920 kb
Host smart-f78bb7d0-89c9-42e0-b39c-51fb560e0114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942339407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1942339407
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3017958758
Short name T657
Test name
Test status
Simulation time 78618911 ps
CPU time 1.21 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 195800 kb
Host smart-947ae218-a994-4e1f-a9e5-be39da8a11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017958758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3017958758
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1545826926
Short name T344
Test name
Test status
Simulation time 39128242 ps
CPU time 0.89 seconds
Started Feb 04 02:43:09 PM PST 24
Finished Feb 04 02:43:20 PM PST 24
Peak memory 196424 kb
Host smart-06524b7c-559f-47b6-a099-8c8a699af1d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545826926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1545826926
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.330094312
Short name T709
Test name
Test status
Simulation time 112790858 ps
CPU time 5.15 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:29 PM PST 24
Peak memory 197784 kb
Host smart-56f9251a-a9b6-4393-a8bd-0e6dfd2c6a7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330094312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.330094312
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1226177505
Short name T736
Test name
Test status
Simulation time 34506647 ps
CPU time 0.93 seconds
Started Feb 04 02:43:08 PM PST 24
Finished Feb 04 02:43:20 PM PST 24
Peak memory 195320 kb
Host smart-2646c452-010a-4c0d-a965-d7a749ef7af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226177505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1226177505
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.249500812
Short name T668
Test name
Test status
Simulation time 75072571 ps
CPU time 1.27 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 197740 kb
Host smart-f0bcd1f7-b6de-4cfa-bbec-d62cbc33cf14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249500812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.249500812
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3250682787
Short name T295
Test name
Test status
Simulation time 4195599920 ps
CPU time 29.44 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:55 PM PST 24
Peak memory 197940 kb
Host smart-709b7b86-21ce-4a7f-9641-b7c22048e4b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250682787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3250682787
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1689346424
Short name T809
Test name
Test status
Simulation time 287117485765 ps
CPU time 1946.8 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 03:15:52 PM PST 24
Peak memory 198048 kb
Host smart-80443a9a-067a-4ff6-a08f-1fd4dc5e48ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1689346424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1689346424
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2695313897
Short name T51
Test name
Test status
Simulation time 39612521 ps
CPU time 0.59 seconds
Started Feb 04 02:43:15 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 193724 kb
Host smart-02dee145-74f9-4fd5-a6d1-f792d08ebae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695313897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2695313897
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1386957598
Short name T242
Test name
Test status
Simulation time 120310907 ps
CPU time 0.8 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 195928 kb
Host smart-e87f30e3-e5c6-4df9-af1c-e7b9f34da100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386957598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1386957598
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4176015426
Short name T603
Test name
Test status
Simulation time 323122431 ps
CPU time 8.07 seconds
Started Feb 04 02:43:16 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 196748 kb
Host smart-79e966ec-c019-4f84-b6d2-d5717a2f30dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176015426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4176015426
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2258984268
Short name T426
Test name
Test status
Simulation time 403746470 ps
CPU time 1.04 seconds
Started Feb 04 02:43:11 PM PST 24
Finished Feb 04 02:43:22 PM PST 24
Peak memory 196356 kb
Host smart-7236846b-805b-4c6f-a0bd-f7e7ae94414e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258984268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2258984268
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1957958341
Short name T658
Test name
Test status
Simulation time 274526711 ps
CPU time 1.37 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 197128 kb
Host smart-fe865fd9-9ccb-4614-8261-485e1201b7d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957958341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1957958341
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2888916271
Short name T559
Test name
Test status
Simulation time 217603287 ps
CPU time 2.38 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 197876 kb
Host smart-9e4a890d-7eda-4626-8583-54e523344713
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888916271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2888916271
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2409587380
Short name T439
Test name
Test status
Simulation time 300652863 ps
CPU time 3.42 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:24 PM PST 24
Peak memory 196280 kb
Host smart-adbd8ae4-9979-48fe-943c-8fc4e5cb85ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409587380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2409587380
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.383788823
Short name T367
Test name
Test status
Simulation time 81205262 ps
CPU time 1.01 seconds
Started Feb 04 02:43:15 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 195556 kb
Host smart-ef49b32f-4f5c-4c25-9031-e66e28f77752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383788823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.383788823
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.379336423
Short name T648
Test name
Test status
Simulation time 16188353 ps
CPU time 0.67 seconds
Started Feb 04 02:43:17 PM PST 24
Finished Feb 04 02:43:26 PM PST 24
Peak memory 194052 kb
Host smart-5e9f5c50-6ad5-498c-94f9-89f760c245b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379336423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.379336423
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2222691160
Short name T414
Test name
Test status
Simulation time 454782328 ps
CPU time 5.5 seconds
Started Feb 04 02:43:10 PM PST 24
Finished Feb 04 02:43:25 PM PST 24
Peak memory 197688 kb
Host smart-5936f820-b5a5-4b5f-bc45-3fafa0b1f937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222691160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2222691160
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.975770883
Short name T612
Test name
Test status
Simulation time 199921088 ps
CPU time 1 seconds
Started Feb 04 02:43:14 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 194180 kb
Host smart-ab264789-01d3-4854-beb4-00497af49a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975770883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.975770883
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.574337206
Short name T819
Test name
Test status
Simulation time 251473882 ps
CPU time 1.23 seconds
Started Feb 04 02:43:16 PM PST 24
Finished Feb 04 02:43:27 PM PST 24
Peak memory 195288 kb
Host smart-a5c0795a-77f2-4cf0-84ba-2134b4cb04f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574337206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.574337206
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2106181341
Short name T387
Test name
Test status
Simulation time 56794954879 ps
CPU time 168.37 seconds
Started Feb 04 02:43:17 PM PST 24
Finished Feb 04 02:46:14 PM PST 24
Peak memory 197916 kb
Host smart-ba392cc4-b3a1-4dff-a921-900065283986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106181341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2106181341
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2520591579
Short name T291
Test name
Test status
Simulation time 111313811088 ps
CPU time 437.97 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:50:42 PM PST 24
Peak memory 198060 kb
Host smart-45379630-6f0f-4e0c-8cc8-4be86a5737ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2520591579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2520591579
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4185513554
Short name T845
Test name
Test status
Simulation time 14669612 ps
CPU time 0.6 seconds
Started Feb 04 02:43:27 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 194636 kb
Host smart-235d785f-27b7-4d70-9071-f2efbc370d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185513554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4185513554
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1345946670
Short name T764
Test name
Test status
Simulation time 37116379 ps
CPU time 0.78 seconds
Started Feb 04 02:43:34 PM PST 24
Finished Feb 04 02:43:38 PM PST 24
Peak memory 195752 kb
Host smart-dba0fa0e-fe51-4100-91c0-9d1a8c0959f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345946670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1345946670
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3032610790
Short name T746
Test name
Test status
Simulation time 3076440494 ps
CPU time 21.22 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:54 PM PST 24
Peak memory 196836 kb
Host smart-805e8954-91c2-4bc9-ab98-b00cba941e48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032610790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3032610790
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3765919041
Short name T252
Test name
Test status
Simulation time 88003228 ps
CPU time 0.65 seconds
Started Feb 04 02:43:33 PM PST 24
Finished Feb 04 02:43:37 PM PST 24
Peak memory 195240 kb
Host smart-6ea1ed0e-1e3e-4f07-8a1b-0d89d821f7b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765919041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3765919041
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3039780009
Short name T825
Test name
Test status
Simulation time 180945544 ps
CPU time 1.29 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 196652 kb
Host smart-ef4ff03c-76ab-4fad-9c8f-ee6dbc8d6c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039780009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3039780009
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2031523505
Short name T784
Test name
Test status
Simulation time 319213374 ps
CPU time 3.3 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:43:37 PM PST 24
Peak memory 197752 kb
Host smart-2c42441d-e65b-42cc-b96b-d8af1bcb89d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031523505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2031523505
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3888459475
Short name T739
Test name
Test status
Simulation time 470353262 ps
CPU time 3.54 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:35 PM PST 24
Peak memory 197800 kb
Host smart-e70e2797-0c97-49e1-8e68-1bb0fb2843b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888459475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3888459475
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3572840399
Short name T651
Test name
Test status
Simulation time 81974556 ps
CPU time 1.09 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:43:35 PM PST 24
Peak memory 195596 kb
Host smart-57bbc978-a6b9-4bff-9daf-2053d2b98726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572840399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3572840399
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3633113734
Short name T562
Test name
Test status
Simulation time 30103561 ps
CPU time 1.04 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 195784 kb
Host smart-9b328d11-303e-4b96-bd80-64a19408765b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633113734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3633113734
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1357702488
Short name T265
Test name
Test status
Simulation time 262307580 ps
CPU time 1.2 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 197580 kb
Host smart-2fe6a3e8-ed50-4973-8417-bf3a5e5ce07e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357702488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1357702488
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1484455526
Short name T505
Test name
Test status
Simulation time 318927166 ps
CPU time 1.23 seconds
Started Feb 04 02:43:13 PM PST 24
Finished Feb 04 02:43:25 PM PST 24
Peak memory 195488 kb
Host smart-66b12f40-268a-48f7-851f-bfaefc919d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484455526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1484455526
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1885997194
Short name T389
Test name
Test status
Simulation time 44281867 ps
CPU time 1.3 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 196492 kb
Host smart-e3ba455d-2a2b-4006-b72a-6c7cfc8dff3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885997194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1885997194
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2720135031
Short name T607
Test name
Test status
Simulation time 6058297063 ps
CPU time 149.2 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:46:02 PM PST 24
Peak memory 197856 kb
Host smart-46cba3d7-4ba5-48af-b36b-ecf3c0f5aec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720135031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2720135031
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2155029072
Short name T294
Test name
Test status
Simulation time 114623067478 ps
CPU time 1351.2 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 03:06:11 PM PST 24
Peak memory 197908 kb
Host smart-2732332c-7652-498a-a73a-d9aeca1c8a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2155029072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2155029072
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.500940808
Short name T48
Test name
Test status
Simulation time 31234591 ps
CPU time 0.62 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 193952 kb
Host smart-95aeb24a-12c6-43ab-bf9b-14eaf6d05231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500940808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.500940808
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3402094969
Short name T354
Test name
Test status
Simulation time 35138378 ps
CPU time 0.71 seconds
Started Feb 04 02:43:23 PM PST 24
Finished Feb 04 02:43:31 PM PST 24
Peak memory 194728 kb
Host smart-5edf767a-d993-4088-b884-06a9bb08a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402094969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3402094969
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1759295150
Short name T874
Test name
Test status
Simulation time 11843544624 ps
CPU time 24.31 seconds
Started Feb 04 02:43:30 PM PST 24
Finished Feb 04 02:43:59 PM PST 24
Peak memory 197232 kb
Host smart-b1b9d44c-115e-42ff-94cd-c9dfa3dcb59c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759295150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1759295150
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3512830300
Short name T880
Test name
Test status
Simulation time 54910462 ps
CPU time 0.84 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 195776 kb
Host smart-55cedcaf-7b50-4de6-b53e-674ea1815e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512830300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3512830300
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3751804516
Short name T429
Test name
Test status
Simulation time 255590339 ps
CPU time 1.14 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 195696 kb
Host smart-2582b770-4aec-4d49-9749-ad10c80884c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751804516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3751804516
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2576340164
Short name T715
Test name
Test status
Simulation time 232050193 ps
CPU time 2.47 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 197700 kb
Host smart-31d3299d-027b-4892-9457-6c2d8ba73930
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576340164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2576340164
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1063617622
Short name T660
Test name
Test status
Simulation time 89182986 ps
CPU time 2.69 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 197196 kb
Host smart-b631b2e1-2c70-460b-8458-3d72f95afc38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063617622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1063617622
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2111252490
Short name T358
Test name
Test status
Simulation time 102028921 ps
CPU time 1.22 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 196280 kb
Host smart-9d7d495a-7e98-44e9-8cfb-3e4c636bcd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111252490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2111252490
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2263186068
Short name T243
Test name
Test status
Simulation time 540144858 ps
CPU time 1.09 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 195844 kb
Host smart-09e61068-f4af-4b54-902d-eb531e7ba95b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263186068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2263186068
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3444721405
Short name T244
Test name
Test status
Simulation time 1313050612 ps
CPU time 5.13 seconds
Started Feb 04 02:43:33 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 197756 kb
Host smart-93f66f62-ee2d-485d-b451-0a30317bce36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444721405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3444721405
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.944170279
Short name T577
Test name
Test status
Simulation time 87083265 ps
CPU time 0.88 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 194980 kb
Host smart-b2056fec-edab-47e7-9777-a624769d3b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944170279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.944170279
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3781607796
Short name T404
Test name
Test status
Simulation time 55710356 ps
CPU time 1.17 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 196180 kb
Host smart-976f6c2e-d7f7-47fe-9a35-5c36c781739f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781607796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3781607796
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1887072314
Short name T503
Test name
Test status
Simulation time 36752778572 ps
CPU time 142.98 seconds
Started Feb 04 02:43:34 PM PST 24
Finished Feb 04 02:46:00 PM PST 24
Peak memory 197940 kb
Host smart-8f1a49f4-c01d-4b07-8063-307c267ff00f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887072314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1887072314
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2700212389
Short name T408
Test name
Test status
Simulation time 292457827184 ps
CPU time 1679.12 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 03:11:39 PM PST 24
Peak memory 197908 kb
Host smart-0c8239c2-397e-4a80-b1bf-5dc7642db271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2700212389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2700212389
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2917350573
Short name T645
Test name
Test status
Simulation time 15078190 ps
CPU time 0.59 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:31 PM PST 24
Peak memory 194420 kb
Host smart-21149864-f1e3-40da-90e4-c5c71e7bbff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917350573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2917350573
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1387231146
Short name T452
Test name
Test status
Simulation time 62028811 ps
CPU time 0.69 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 193756 kb
Host smart-f472c872-3a37-4bba-93fb-a3d87592542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387231146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1387231146
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2088123579
Short name T838
Test name
Test status
Simulation time 1778055259 ps
CPU time 23.89 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:57 PM PST 24
Peak memory 196784 kb
Host smart-293e7bdd-9923-4446-b064-8d344c6d1be5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088123579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2088123579
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.404970539
Short name T444
Test name
Test status
Simulation time 134435361 ps
CPU time 0.97 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:40 PM PST 24
Peak memory 196036 kb
Host smart-bf0bf904-6a8e-4d4a-a7dd-cc45c1aacda2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404970539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.404970539
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3895632099
Short name T279
Test name
Test status
Simulation time 261153554 ps
CPU time 1.32 seconds
Started Feb 04 02:43:27 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 196656 kb
Host smart-e03d0806-6d51-4a81-883c-df863b5e08ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895632099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3895632099
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2032656214
Short name T768
Test name
Test status
Simulation time 358600226 ps
CPU time 1.44 seconds
Started Feb 04 02:43:25 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 197800 kb
Host smart-205920f4-0332-47cb-aee4-2be18e5645b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032656214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2032656214
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1982711819
Short name T63
Test name
Test status
Simulation time 107734066 ps
CPU time 3.11 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 196732 kb
Host smart-5f00a315-3265-44f5-90c0-a6f8f706d20a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982711819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1982711819
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.952880891
Short name T416
Test name
Test status
Simulation time 19624419 ps
CPU time 0.66 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 194116 kb
Host smart-6de3bdc9-427a-4cfa-a0f3-1daee047e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952880891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.952880891
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4124787139
Short name T226
Test name
Test status
Simulation time 39996213 ps
CPU time 0.96 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 196324 kb
Host smart-f87c91ed-058c-4296-ac92-ce3368bd3e5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124787139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4124787139
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4161535320
Short name T605
Test name
Test status
Simulation time 489470007 ps
CPU time 2.17 seconds
Started Feb 04 02:43:30 PM PST 24
Finished Feb 04 02:43:37 PM PST 24
Peak memory 197772 kb
Host smart-f6c1f702-44fc-4f89-a9d4-1d31c9300b77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161535320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4161535320
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.942612759
Short name T639
Test name
Test status
Simulation time 87933778 ps
CPU time 1.26 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 195328 kb
Host smart-4228f5cd-ec4b-4d9f-8164-c5246d868666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942612759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.942612759
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3409673759
Short name T654
Test name
Test status
Simulation time 63864217 ps
CPU time 1.16 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 195424 kb
Host smart-ccf4f55a-8aa6-4b3b-b79f-f2c6f1d3eb79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409673759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3409673759
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1906827926
Short name T604
Test name
Test status
Simulation time 20076138016 ps
CPU time 140.3 seconds
Started Feb 04 02:43:32 PM PST 24
Finished Feb 04 02:45:56 PM PST 24
Peak memory 197896 kb
Host smart-de7e503a-2ae0-4643-bcb3-4fbd6415a2b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906827926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1906827926
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3125327334
Short name T558
Test name
Test status
Simulation time 23605352432 ps
CPU time 659.17 seconds
Started Feb 04 02:43:35 PM PST 24
Finished Feb 04 02:54:38 PM PST 24
Peak memory 197880 kb
Host smart-1587a496-3f7a-4760-8659-20a04900b739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3125327334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3125327334
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1751707540
Short name T396
Test name
Test status
Simulation time 15639298 ps
CPU time 0.65 seconds
Started Feb 04 02:43:25 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 193108 kb
Host smart-8368f8e0-0e0f-43d1-8b91-5fa68529212f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751707540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1751707540
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.218387879
Short name T234
Test name
Test status
Simulation time 29310552 ps
CPU time 0.91 seconds
Started Feb 04 02:43:25 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 195528 kb
Host smart-cef587ba-94e8-46f8-9a93-90461c556792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218387879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.218387879
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1602613871
Short name T555
Test name
Test status
Simulation time 656381736 ps
CPU time 15.99 seconds
Started Feb 04 02:43:33 PM PST 24
Finished Feb 04 02:43:53 PM PST 24
Peak memory 196040 kb
Host smart-a7f8e6cf-bf4f-4505-9804-cde8c3d14b72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602613871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1602613871
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3928651233
Short name T743
Test name
Test status
Simulation time 134828087 ps
CPU time 0.73 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 194608 kb
Host smart-05008cfe-5b63-403e-80ac-98bfe4f812da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928651233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3928651233
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2423638292
Short name T220
Test name
Test status
Simulation time 59646659 ps
CPU time 1.03 seconds
Started Feb 04 02:43:30 PM PST 24
Finished Feb 04 02:43:36 PM PST 24
Peak memory 196492 kb
Host smart-7d1fc4cc-55a2-49f2-8071-92bf1e944f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423638292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2423638292
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.580267976
Short name T734
Test name
Test status
Simulation time 1219916946 ps
CPU time 3.02 seconds
Started Feb 04 02:43:31 PM PST 24
Finished Feb 04 02:43:39 PM PST 24
Peak memory 197832 kb
Host smart-0181f726-6e2f-4e5b-a2b4-a3c7e4d77ee6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580267976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.580267976
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2849546240
Short name T417
Test name
Test status
Simulation time 52162560 ps
CPU time 0.89 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:40 PM PST 24
Peak memory 195224 kb
Host smart-97c7175a-f6c7-42b5-b15b-2840853b4f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849546240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2849546240
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.768832486
Short name T737
Test name
Test status
Simulation time 26621930 ps
CPU time 0.99 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:34 PM PST 24
Peak memory 195636 kb
Host smart-01fcf187-8233-499b-a335-73b0ac5d1ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768832486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.768832486
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3049220208
Short name T728
Test name
Test status
Simulation time 45978209 ps
CPU time 0.98 seconds
Started Feb 04 02:43:31 PM PST 24
Finished Feb 04 02:43:36 PM PST 24
Peak memory 196340 kb
Host smart-d6b8e07e-4ce7-4beb-83f0-fca95fb636f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049220208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3049220208
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3737010732
Short name T697
Test name
Test status
Simulation time 287819633 ps
CPU time 3.65 seconds
Started Feb 04 02:43:33 PM PST 24
Finished Feb 04 02:43:40 PM PST 24
Peak memory 197584 kb
Host smart-92180390-572a-4d5d-ac74-b27cbd81ab65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737010732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3737010732
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.260525917
Short name T772
Test name
Test status
Simulation time 48547439 ps
CPU time 1.05 seconds
Started Feb 04 02:43:26 PM PST 24
Finished Feb 04 02:43:33 PM PST 24
Peak memory 195576 kb
Host smart-eefb882d-aa14-4f62-bbfb-477d72f165f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260525917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.260525917
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2409123996
Short name T466
Test name
Test status
Simulation time 208599233 ps
CPU time 1.05 seconds
Started Feb 04 02:43:33 PM PST 24
Finished Feb 04 02:43:38 PM PST 24
Peak memory 195464 kb
Host smart-749318f7-45bc-48ec-b03e-08ba0d35880e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409123996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2409123996
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2678005260
Short name T352
Test name
Test status
Simulation time 183674694906 ps
CPU time 233.65 seconds
Started Feb 04 02:43:29 PM PST 24
Finished Feb 04 02:47:27 PM PST 24
Peak memory 197936 kb
Host smart-5c3313be-c2ec-4989-bcb9-d2f8ec2d767c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678005260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2678005260
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2727949803
Short name T346
Test name
Test status
Simulation time 64643409078 ps
CPU time 1018.59 seconds
Started Feb 04 02:43:25 PM PST 24
Finished Feb 04 03:00:30 PM PST 24
Peak memory 198032 kb
Host smart-423854a6-8024-4a31-aa18-066aeca7885b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2727949803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2727949803
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2063929852
Short name T274
Test name
Test status
Simulation time 12584976 ps
CPU time 0.55 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 193612 kb
Host smart-9c893856-3a79-4dd2-b351-a2b78ffe49fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063929852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2063929852
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2602393431
Short name T852
Test name
Test status
Simulation time 40776638 ps
CPU time 0.8 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:43:50 PM PST 24
Peak memory 195836 kb
Host smart-9b6f6ef4-962d-4423-8bca-3f17366bce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602393431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2602393431
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1270235230
Short name T864
Test name
Test status
Simulation time 800045395 ps
CPU time 7.83 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:54 PM PST 24
Peak memory 196804 kb
Host smart-d7c62b36-052c-4bae-9b12-62a81ee3f4eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270235230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1270235230
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.51994911
Short name T710
Test name
Test status
Simulation time 63800992 ps
CPU time 0.77 seconds
Started Feb 04 02:43:41 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 196416 kb
Host smart-d17faefe-493d-4f07-bcc3-b63bf41ce3e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51994911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.51994911
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1361655428
Short name T405
Test name
Test status
Simulation time 93605122 ps
CPU time 1.4 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 195700 kb
Host smart-bd8a8f42-f4de-4dce-a7df-70683600888b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361655428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1361655428
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1978980942
Short name T228
Test name
Test status
Simulation time 78072843 ps
CPU time 1.65 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:49 PM PST 24
Peak memory 196656 kb
Host smart-aa28de3e-3600-4485-96bb-9832b9882dfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978980942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1978980942
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4263790953
Short name T771
Test name
Test status
Simulation time 57844359 ps
CPU time 1.46 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 195556 kb
Host smart-faf320ea-e11d-4cba-9a59-6669fed18d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263790953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4263790953
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1082064023
Short name T591
Test name
Test status
Simulation time 45105862 ps
CPU time 0.76 seconds
Started Feb 04 02:43:40 PM PST 24
Finished Feb 04 02:43:43 PM PST 24
Peak memory 195300 kb
Host smart-1af33244-90dc-485c-931c-1c1efcf0769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082064023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1082064023
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2022003688
Short name T330
Test name
Test status
Simulation time 116601571 ps
CPU time 0.91 seconds
Started Feb 04 02:43:32 PM PST 24
Finished Feb 04 02:43:37 PM PST 24
Peak memory 196468 kb
Host smart-10da6bd1-86c4-43ac-bf02-283d0b7925f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022003688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2022003688
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.40923290
Short name T584
Test name
Test status
Simulation time 478949092 ps
CPU time 5.34 seconds
Started Feb 04 02:43:40 PM PST 24
Finished Feb 04 02:43:49 PM PST 24
Peak memory 197736 kb
Host smart-dfdbcfeb-f6db-4488-85ee-e6cbb23e3d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40923290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand
om_long_reg_writes_reg_reads.40923290
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.644974862
Short name T814
Test name
Test status
Simulation time 870387613 ps
CPU time 1.31 seconds
Started Feb 04 02:43:24 PM PST 24
Finished Feb 04 02:43:32 PM PST 24
Peak memory 197724 kb
Host smart-974109f1-c272-4e54-beac-d7596a40b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644974862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.644974862
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4247405229
Short name T800
Test name
Test status
Simulation time 307763211 ps
CPU time 1.56 seconds
Started Feb 04 02:43:28 PM PST 24
Finished Feb 04 02:43:35 PM PST 24
Peak memory 197748 kb
Host smart-9d68f543-64d8-4f8f-b694-b24a7c71b814
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247405229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4247405229
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4219633485
Short name T64
Test name
Test status
Simulation time 4828271707 ps
CPU time 120.93 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:45:41 PM PST 24
Peak memory 197932 kb
Host smart-2e7458ae-b345-4edc-82d5-846ac0a82eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219633485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4219633485
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1638340236
Short name T752
Test name
Test status
Simulation time 26211018971 ps
CPU time 840.32 seconds
Started Feb 04 02:43:40 PM PST 24
Finished Feb 04 02:57:43 PM PST 24
Peak memory 197988 kb
Host smart-bad9b4ec-b45c-4480-84e7-5193ebfb9b01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1638340236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1638340236
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.143115403
Short name T319
Test name
Test status
Simulation time 11557290 ps
CPU time 0.57 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:40 PM PST 24
Peak memory 192600 kb
Host smart-a0936f07-177b-4016-bde2-4c1bd0a11b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143115403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.143115403
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.106733307
Short name T357
Test name
Test status
Simulation time 22270886 ps
CPU time 0.65 seconds
Started Feb 04 02:43:35 PM PST 24
Finished Feb 04 02:43:39 PM PST 24
Peak memory 194548 kb
Host smart-421a88cf-d7b8-4137-a0eb-2aae5602e1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106733307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.106733307
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1751271209
Short name T536
Test name
Test status
Simulation time 2626905491 ps
CPU time 9.29 seconds
Started Feb 04 02:43:38 PM PST 24
Finished Feb 04 02:43:50 PM PST 24
Peak memory 196544 kb
Host smart-4fec2916-5708-457f-87b5-e4a3b34ef1da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751271209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1751271209
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2515092842
Short name T100
Test name
Test status
Simulation time 173940678 ps
CPU time 1.16 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 196352 kb
Host smart-03343bcb-66fe-443a-82bc-146a1cc2004b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515092842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2515092842
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.234471944
Short name T360
Test name
Test status
Simulation time 41480597 ps
CPU time 1.12 seconds
Started Feb 04 02:43:34 PM PST 24
Finished Feb 04 02:43:39 PM PST 24
Peak memory 195892 kb
Host smart-7c7ad8eb-b04a-4e84-b28c-fdb42412b41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234471944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.234471944
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3453416680
Short name T873
Test name
Test status
Simulation time 35351097 ps
CPU time 1.4 seconds
Started Feb 04 02:43:41 PM PST 24
Finished Feb 04 02:43:45 PM PST 24
Peak memory 196032 kb
Host smart-df908711-ae6e-471e-8778-47e8d57c3a35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453416680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3453416680
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2028028074
Short name T254
Test name
Test status
Simulation time 121062851 ps
CPU time 1.12 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 196180 kb
Host smart-145f61f1-d973-44ec-88d3-7484e10767b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028028074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2028028074
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1414482380
Short name T260
Test name
Test status
Simulation time 18884009 ps
CPU time 0.81 seconds
Started Feb 04 02:43:43 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 194844 kb
Host smart-82b7fce2-cf1b-44e8-bd0d-978b053d3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414482380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1414482380
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2469668245
Short name T472
Test name
Test status
Simulation time 182466596 ps
CPU time 0.99 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 195868 kb
Host smart-cb1f1829-6202-43e7-80d9-ac6210a74106
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469668245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2469668245
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.437788334
Short name T378
Test name
Test status
Simulation time 347069074 ps
CPU time 4.61 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 197760 kb
Host smart-e1b54f4d-75e9-4077-b118-df3a199fb197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437788334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.437788334
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2870498570
Short name T455
Test name
Test status
Simulation time 45197216 ps
CPU time 0.95 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 195284 kb
Host smart-2ae4d1bf-92f7-42d2-baa1-f60548432011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870498570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2870498570
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2677694837
Short name T297
Test name
Test status
Simulation time 40690628 ps
CPU time 1.18 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 196348 kb
Host smart-cb4f236b-c7e8-41ce-859b-9e48a52f5682
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677694837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2677694837
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2058408367
Short name T828
Test name
Test status
Simulation time 1656848894 ps
CPU time 24.48 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:44:12 PM PST 24
Peak memory 197840 kb
Host smart-59820ac6-31b7-47c0-b5f7-699f297d15a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058408367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2058408367
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2812446926
Short name T316
Test name
Test status
Simulation time 67733021716 ps
CPU time 1079.64 seconds
Started Feb 04 02:43:38 PM PST 24
Finished Feb 04 03:01:41 PM PST 24
Peak memory 197824 kb
Host smart-95b1b8f0-c653-4261-a33c-8a3efdc759e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2812446926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2812446926
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2589866366
Short name T623
Test name
Test status
Simulation time 20009378 ps
CPU time 0.57 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:43:55 PM PST 24
Peak memory 193736 kb
Host smart-f5f086b4-0840-4508-a147-623a5545a6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589866366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2589866366
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1973806967
Short name T868
Test name
Test status
Simulation time 96922904 ps
CPU time 0.87 seconds
Started Feb 04 02:43:42 PM PST 24
Finished Feb 04 02:43:45 PM PST 24
Peak memory 197088 kb
Host smart-82240bec-4b6c-4cc9-8c0a-eb1451cb430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973806967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1973806967
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4286447464
Short name T770
Test name
Test status
Simulation time 8116523622 ps
CPU time 27.2 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:44:22 PM PST 24
Peak memory 196692 kb
Host smart-93fa9231-054c-464a-a6c6-9650525c5d90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286447464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4286447464
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2058891806
Short name T787
Test name
Test status
Simulation time 76037413 ps
CPU time 0.61 seconds
Started Feb 04 02:43:41 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 194044 kb
Host smart-b47a7f95-abed-4165-bb17-a31436f27f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058891806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2058891806
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.905704598
Short name T488
Test name
Test status
Simulation time 46110447 ps
CPU time 0.96 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 195604 kb
Host smart-d90c8e9f-48e4-40bf-88a5-d08e7b9de096
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905704598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.905704598
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1318259162
Short name T392
Test name
Test status
Simulation time 29799623 ps
CPU time 1.21 seconds
Started Feb 04 02:43:40 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 197292 kb
Host smart-abe61e78-bcd4-4b97-904c-3e77d5230cad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318259162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1318259162
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1429197617
Short name T644
Test name
Test status
Simulation time 410041173 ps
CPU time 3.1 seconds
Started Feb 04 02:43:43 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 196480 kb
Host smart-05e213aa-ef2c-4d4a-831c-bf7ef4b0101d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429197617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1429197617
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1694477511
Short name T653
Test name
Test status
Simulation time 228409297 ps
CPU time 1.09 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 196592 kb
Host smart-c35ae2e9-4f7b-4d6c-bfa8-e0bb383b5182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694477511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1694477511
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2013898082
Short name T227
Test name
Test status
Simulation time 291643564 ps
CPU time 1.02 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 195732 kb
Host smart-b4220e36-2689-47ad-9bdd-5f283334159a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013898082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2013898082
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4104252194
Short name T628
Test name
Test status
Simulation time 1491576068 ps
CPU time 6.02 seconds
Started Feb 04 02:43:47 PM PST 24
Finished Feb 04 02:43:58 PM PST 24
Peak memory 197628 kb
Host smart-9efaea9b-2b06-40f6-92b8-45b46265f564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104252194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4104252194
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2178968096
Short name T214
Test name
Test status
Simulation time 234253078 ps
CPU time 1.01 seconds
Started Feb 04 02:43:37 PM PST 24
Finished Feb 04 02:43:42 PM PST 24
Peak memory 196176 kb
Host smart-bd94ef0b-71be-419b-bad0-526424f01714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178968096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2178968096
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3467932269
Short name T480
Test name
Test status
Simulation time 61157726 ps
CPU time 1.24 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 196232 kb
Host smart-c7dda84c-ea7d-4af2-81b5-56f3b8eb4d35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467932269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3467932269
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2323323797
Short name T687
Test name
Test status
Simulation time 6537692469 ps
CPU time 80.54 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:45:14 PM PST 24
Peak memory 197908 kb
Host smart-041288c5-275e-412c-898c-68b8200db35f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323323797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2323323797
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1320869735
Short name T441
Test name
Test status
Simulation time 62788095635 ps
CPU time 1708.99 seconds
Started Feb 04 02:43:43 PM PST 24
Finished Feb 04 03:12:15 PM PST 24
Peak memory 198032 kb
Host smart-3eb86d9e-8c12-45e5-9a76-b66e4c2a39e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1320869735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1320869735
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3182437208
Short name T464
Test name
Test status
Simulation time 13617005 ps
CPU time 0.64 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 193920 kb
Host smart-da2530ab-3cf6-4450-bdbe-96eb5431648f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182437208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3182437208
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2680900463
Short name T440
Test name
Test status
Simulation time 61013060 ps
CPU time 0.78 seconds
Started Feb 04 02:42:24 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 195040 kb
Host smart-36f074b8-8b66-496d-afac-62c0139a6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680900463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2680900463
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.908873172
Short name T233
Test name
Test status
Simulation time 2672298153 ps
CPU time 18.85 seconds
Started Feb 04 02:42:21 PM PST 24
Finished Feb 04 02:42:43 PM PST 24
Peak memory 197940 kb
Host smart-600d2169-7616-4766-b46d-d3e92c50d31b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908873172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.908873172
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1325442325
Short name T597
Test name
Test status
Simulation time 232394195 ps
CPU time 0.89 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 196344 kb
Host smart-b60f23f9-a094-4fa1-a686-11ab454e795c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325442325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1325442325
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.466063123
Short name T326
Test name
Test status
Simulation time 72694233 ps
CPU time 0.83 seconds
Started Feb 04 02:42:17 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 196196 kb
Host smart-d83eab9c-5194-48c1-8b9c-d17f8dfcc2bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466063123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.466063123
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1173194400
Short name T531
Test name
Test status
Simulation time 42853359 ps
CPU time 1.42 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 196520 kb
Host smart-679bb054-e848-409b-97d4-e61787310303
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173194400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1173194400
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3648007751
Short name T271
Test name
Test status
Simulation time 226762630 ps
CPU time 3.72 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 197872 kb
Host smart-e66688a2-26a3-4d90-8b0a-20728459f741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648007751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3648007751
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2097715804
Short name T685
Test name
Test status
Simulation time 124763572 ps
CPU time 1.23 seconds
Started Feb 04 02:42:16 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 197064 kb
Host smart-c0358078-12e6-4bb6-80a8-c501bb4b9845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097715804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2097715804
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3773773026
Short name T606
Test name
Test status
Simulation time 29447090 ps
CPU time 0.77 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 195920 kb
Host smart-fb22258e-ff8d-4be5-bf57-76e551ace1cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773773026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3773773026
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3913150277
Short name T349
Test name
Test status
Simulation time 43579801 ps
CPU time 1.13 seconds
Started Feb 04 02:42:23 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 196040 kb
Host smart-3fb145de-1ff6-440d-bc33-108594f23746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913150277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3913150277
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.2819180862
Short name T601
Test name
Test status
Simulation time 329034105 ps
CPU time 1.15 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 195096 kb
Host smart-af1877fd-4f1c-4a2f-9919-ab6bf841dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819180862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2819180862
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1841881742
Short name T499
Test name
Test status
Simulation time 66101652 ps
CPU time 1.05 seconds
Started Feb 04 02:42:16 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 195308 kb
Host smart-40355d08-436f-4a21-9d20-03c188d35962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841881742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1841881742
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.602791513
Short name T693
Test name
Test status
Simulation time 174335099559 ps
CPU time 222.87 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:46:09 PM PST 24
Peak memory 197892 kb
Host smart-da6641f2-b887-492c-96a3-d13e0e9b1a12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602791513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.602791513
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.69407565
Short name T617
Test name
Test status
Simulation time 299362831202 ps
CPU time 656.16 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:53:18 PM PST 24
Peak memory 198020 kb
Host smart-3b6f368e-7f4f-4d45-bc10-7e40d471cea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=69407565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.69407565
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.857276562
Short name T504
Test name
Test status
Simulation time 51382725 ps
CPU time 0.57 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 193792 kb
Host smart-222c12ad-6fca-4ace-a757-6bc79015c286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857276562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.857276562
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3614970860
Short name T600
Test name
Test status
Simulation time 200164702 ps
CPU time 0.85 seconds
Started Feb 04 02:43:42 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 195504 kb
Host smart-43962e1c-9d5b-431e-9fda-36f23ef213d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614970860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3614970860
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.332831784
Short name T803
Test name
Test status
Simulation time 6619840175 ps
CPU time 28.92 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:44:27 PM PST 24
Peak memory 196832 kb
Host smart-431fda05-7c79-4f55-ad17-5722b81271f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332831784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.332831784
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2963693966
Short name T412
Test name
Test status
Simulation time 382212727 ps
CPU time 0.75 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:43:58 PM PST 24
Peak memory 194556 kb
Host smart-d5c4618a-6f25-49fa-b8d4-367a15400a81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963693966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2963693966
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1125911057
Short name T347
Test name
Test status
Simulation time 32706227 ps
CPU time 0.74 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:43:55 PM PST 24
Peak memory 195192 kb
Host smart-0fffd37c-1722-4e10-92eb-106642572e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125911057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1125911057
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1136881395
Short name T479
Test name
Test status
Simulation time 166727498 ps
CPU time 3.67 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 197844 kb
Host smart-e8f4c4ba-756a-4143-8ca8-60642adffe37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136881395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1136881395
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1443226066
Short name T454
Test name
Test status
Simulation time 1333109949 ps
CPU time 2.84 seconds
Started Feb 04 02:43:51 PM PST 24
Finished Feb 04 02:44:02 PM PST 24
Peak memory 196712 kb
Host smart-86aba8cb-0695-480b-b5ed-d5d7668a5711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443226066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1443226066
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1891613300
Short name T618
Test name
Test status
Simulation time 37250693 ps
CPU time 0.82 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:47 PM PST 24
Peak memory 196372 kb
Host smart-7e443eb4-530f-4d33-82d2-8863a4bf39f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891613300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1891613300
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2322658301
Short name T312
Test name
Test status
Simulation time 54299100 ps
CPU time 1.14 seconds
Started Feb 04 02:43:39 PM PST 24
Finished Feb 04 02:43:44 PM PST 24
Peak memory 195628 kb
Host smart-d8c597ae-3351-4f9b-af74-7fd6fb053e18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322658301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2322658301
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2489974118
Short name T678
Test name
Test status
Simulation time 230751285 ps
CPU time 1.4 seconds
Started Feb 04 02:43:47 PM PST 24
Finished Feb 04 02:43:53 PM PST 24
Peak memory 197700 kb
Host smart-50592940-bf6c-4f29-b1a6-fc104a29b6f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489974118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2489974118
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2915841661
Short name T442
Test name
Test status
Simulation time 125886117 ps
CPU time 0.97 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:43:50 PM PST 24
Peak memory 195936 kb
Host smart-f5182a3f-cfe1-4755-bbef-a1e8e0693a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915841661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2915841661
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2765234936
Short name T258
Test name
Test status
Simulation time 589948893 ps
CPU time 1.18 seconds
Started Feb 04 02:43:51 PM PST 24
Finished Feb 04 02:44:00 PM PST 24
Peak memory 195964 kb
Host smart-1e38edd7-2119-462d-84fc-eb6324646ec2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765234936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2765234936
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2691170699
Short name T401
Test name
Test status
Simulation time 28130839524 ps
CPU time 150.92 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:46:22 PM PST 24
Peak memory 197960 kb
Host smart-ff641a98-f6a8-4c36-a53d-36c8c5549c4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691170699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2691170699
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.4213519842
Short name T422
Test name
Test status
Simulation time 98212024897 ps
CPU time 2174.64 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 03:20:06 PM PST 24
Peak memory 197956 kb
Host smart-0e0c93bb-c320-4784-a476-f08c594a4557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4213519842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.4213519842
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3174544699
Short name T554
Test name
Test status
Simulation time 12280577 ps
CPU time 0.54 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 193708 kb
Host smart-c648dd59-b9e2-46e2-9fa6-7015a49bddd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174544699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3174544699
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.769569607
Short name T688
Test name
Test status
Simulation time 24161965 ps
CPU time 0.72 seconds
Started Feb 04 02:43:43 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 195716 kb
Host smart-9e81261d-8a4b-48f1-b0b6-bffe8a9c81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769569607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.769569607
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2295370454
Short name T656
Test name
Test status
Simulation time 860943986 ps
CPU time 25.25 seconds
Started Feb 04 02:43:47 PM PST 24
Finished Feb 04 02:44:17 PM PST 24
Peak memory 196484 kb
Host smart-82af6b47-6f12-4993-acda-4ec75fd62b4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295370454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2295370454
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.878694067
Short name T251
Test name
Test status
Simulation time 242594805 ps
CPU time 0.92 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:43:50 PM PST 24
Peak memory 196396 kb
Host smart-7442cf06-9162-487e-9628-13bdb7ca4045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878694067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.878694067
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4205147211
Short name T289
Test name
Test status
Simulation time 72160941 ps
CPU time 1.21 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 195668 kb
Host smart-4bc8c7bd-77f6-442f-bdb7-37d81578a15e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205147211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4205147211
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.466105021
Short name T415
Test name
Test status
Simulation time 34961382 ps
CPU time 1.43 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:43:56 PM PST 24
Peak memory 196304 kb
Host smart-450bf636-cd8b-4c0a-bc00-57e4cccf8074
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466105021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.466105021
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2187220274
Short name T633
Test name
Test status
Simulation time 546799812 ps
CPU time 2.73 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:53 PM PST 24
Peak memory 196872 kb
Host smart-ce8fb5a6-26de-4200-8f32-214df6b9cb88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187220274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2187220274
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2020590643
Short name T851
Test name
Test status
Simulation time 34526078 ps
CPU time 1.2 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 196384 kb
Host smart-c97a09c8-0017-43f4-8550-9170ef9f7402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020590643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2020590643
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3510347088
Short name T797
Test name
Test status
Simulation time 34141585 ps
CPU time 0.86 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 195420 kb
Host smart-c5e2e6d1-a89d-42a2-a839-c657668fc503
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510347088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3510347088
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3762941720
Short name T692
Test name
Test status
Simulation time 1192775772 ps
CPU time 5 seconds
Started Feb 04 02:43:47 PM PST 24
Finished Feb 04 02:43:58 PM PST 24
Peak memory 197732 kb
Host smart-7d91c273-f5ad-419a-8c15-3c73539c6932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762941720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3762941720
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3593442428
Short name T398
Test name
Test status
Simulation time 63811019 ps
CPU time 1.09 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:48 PM PST 24
Peak memory 196232 kb
Host smart-99e8bbac-3527-498e-9cc3-1d9eec30f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593442428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3593442428
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2479112145
Short name T518
Test name
Test status
Simulation time 86511191 ps
CPU time 1.27 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:49 PM PST 24
Peak memory 196188 kb
Host smart-96479448-4b52-40a4-883e-d88f9ead1a57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479112145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2479112145
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1627940574
Short name T348
Test name
Test status
Simulation time 3840576780 ps
CPU time 51.76 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:44:46 PM PST 24
Peak memory 197948 kb
Host smart-cdc5a8ca-65f1-4148-af92-76c843d2dd4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627940574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1627940574
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.4221904488
Short name T331
Test name
Test status
Simulation time 44007651301 ps
CPU time 335.47 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:49:25 PM PST 24
Peak memory 198004 kb
Host smart-40a8a0e2-0b26-415f-a7f7-2f298f38eb68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4221904488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.4221904488
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3609649701
Short name T359
Test name
Test status
Simulation time 14735531 ps
CPU time 0.56 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 193644 kb
Host smart-8d1b443a-b71b-4443-823d-bb7af7c4d86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609649701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3609649701
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2539923489
Short name T855
Test name
Test status
Simulation time 32488392 ps
CPU time 0.84 seconds
Started Feb 04 02:43:42 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 196972 kb
Host smart-ee30a49e-5385-49b7-be0e-7c669a23adf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539923489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2539923489
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.974708329
Short name T782
Test name
Test status
Simulation time 4965749564 ps
CPU time 22.43 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 196720 kb
Host smart-5e28ee4e-19ef-45a3-8d4c-cdd70bc1e979
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974708329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.974708329
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2471211978
Short name T305
Test name
Test status
Simulation time 719050123 ps
CPU time 0.75 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 195488 kb
Host smart-36bdd8fb-fb6e-4496-a964-e79590e4da7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471211978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2471211978
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1204482043
Short name T470
Test name
Test status
Simulation time 68339011 ps
CPU time 1.23 seconds
Started Feb 04 02:43:43 PM PST 24
Finished Feb 04 02:43:47 PM PST 24
Peak memory 195948 kb
Host smart-4cd6f016-9de2-4c12-a141-7f77769fba25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204482043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1204482043
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.6141977
Short name T669
Test name
Test status
Simulation time 158383714 ps
CPU time 3.32 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:51 PM PST 24
Peak memory 197800 kb
Host smart-e7825aef-8193-41ec-83f8-c4e8360eb7a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6141977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.gpio_intr_with_filter_rand_intr_event.6141977
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1150451542
Short name T394
Test name
Test status
Simulation time 52991035 ps
CPU time 1.37 seconds
Started Feb 04 02:43:44 PM PST 24
Finished Feb 04 02:43:49 PM PST 24
Peak memory 195492 kb
Host smart-ecd71891-6d1f-442c-aa04-8e879b36b24d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150451542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1150451542
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.167890905
Short name T831
Test name
Test status
Simulation time 82620211 ps
CPU time 1.08 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:52 PM PST 24
Peak memory 195712 kb
Host smart-7a527c40-e176-41db-8eaf-f9f35116dadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167890905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.167890905
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2138708367
Short name T266
Test name
Test status
Simulation time 210513904 ps
CPU time 1.04 seconds
Started Feb 04 02:43:46 PM PST 24
Finished Feb 04 02:43:52 PM PST 24
Peak memory 195636 kb
Host smart-b8249b7b-0c08-41cb-8983-ca54570a3c8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138708367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2138708367
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2870353821
Short name T384
Test name
Test status
Simulation time 106287357 ps
CPU time 4.67 seconds
Started Feb 04 02:43:45 PM PST 24
Finished Feb 04 02:43:54 PM PST 24
Peak memory 197676 kb
Host smart-9d8c2373-1105-4d4c-8b38-4e64591ba988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870353821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2870353821
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1485865494
Short name T66
Test name
Test status
Simulation time 76480504 ps
CPU time 1.21 seconds
Started Feb 04 02:43:36 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 195308 kb
Host smart-c21f42a1-809b-4301-840b-8d495aee6e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485865494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1485865494
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.448465174
Short name T506
Test name
Test status
Simulation time 236350661 ps
CPU time 1.18 seconds
Started Feb 04 02:43:42 PM PST 24
Finished Feb 04 02:43:46 PM PST 24
Peak memory 196148 kb
Host smart-dcce978a-1c99-41e8-a24b-f8963b1d2a12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448465174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.448465174
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1406900738
Short name T854
Test name
Test status
Simulation time 3532479078 ps
CPU time 20.08 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:44:40 PM PST 24
Peak memory 197728 kb
Host smart-ee113b4b-3441-45e0-a9f8-d076abd50f1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406900738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1406900738
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1289204959
Short name T625
Test name
Test status
Simulation time 86777634408 ps
CPU time 1979.33 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 03:17:17 PM PST 24
Peak memory 197780 kb
Host smart-65985a90-7b41-4f8a-af73-140804b7a8dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1289204959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1289204959
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2692342336
Short name T428
Test name
Test status
Simulation time 36499021 ps
CPU time 0.59 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:43:56 PM PST 24
Peak memory 192524 kb
Host smart-c247f03f-1eaa-4be8-aa6c-8e65a82f6f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692342336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2692342336
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4152304173
Short name T447
Test name
Test status
Simulation time 13258797 ps
CPU time 0.6 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 193708 kb
Host smart-87a4ddb8-9000-4826-9c6a-7dbed3695859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152304173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4152304173
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3052607514
Short name T478
Test name
Test status
Simulation time 2198476769 ps
CPU time 28.36 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 195284 kb
Host smart-ae3540f8-fc84-4aaf-b3ff-427006f0a998
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052607514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3052607514
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1860123297
Short name T69
Test name
Test status
Simulation time 158104048 ps
CPU time 0.73 seconds
Started Feb 04 02:43:52 PM PST 24
Finished Feb 04 02:44:01 PM PST 24
Peak memory 195488 kb
Host smart-1b66cab9-eb97-44c6-9ce5-8a91914f3eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860123297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1860123297
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1185671865
Short name T551
Test name
Test status
Simulation time 30149118 ps
CPU time 0.7 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:43:59 PM PST 24
Peak memory 194204 kb
Host smart-ac020221-1437-4e47-b42a-0f29b300fbba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185671865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1185671865
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1964713759
Short name T632
Test name
Test status
Simulation time 229672550 ps
CPU time 1.21 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 196472 kb
Host smart-e185592d-3716-4249-b2d2-fa0490ef9a55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964713759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1964713759
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3621666493
Short name T419
Test name
Test status
Simulation time 297793620 ps
CPU time 0.94 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:43:56 PM PST 24
Peak memory 195400 kb
Host smart-9247e9b5-b72a-415b-876a-a83947a1fa9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621666493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3621666493
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1164525145
Short name T327
Test name
Test status
Simulation time 40799986 ps
CPU time 0.98 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 196420 kb
Host smart-da9d95f3-0f55-480a-bb46-4fd612d7c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164525145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1164525145
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1426684601
Short name T553
Test name
Test status
Simulation time 33987069 ps
CPU time 1.23 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:44:22 PM PST 24
Peak memory 196292 kb
Host smart-7c953754-d79b-44e3-a355-6a744264f567
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426684601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1426684601
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.862505762
Short name T766
Test name
Test status
Simulation time 106778050 ps
CPU time 4.5 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:23 PM PST 24
Peak memory 197460 kb
Host smart-12af7dfe-e1cb-41ef-a348-6c6d88536f1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862505762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.862505762
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.451666035
Short name T557
Test name
Test status
Simulation time 227195332 ps
CPU time 0.94 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:43:57 PM PST 24
Peak memory 195296 kb
Host smart-32e3981e-becd-4c11-9677-db592296ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451666035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.451666035
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3316518847
Short name T815
Test name
Test status
Simulation time 93764831 ps
CPU time 1.05 seconds
Started Feb 04 02:43:58 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 195300 kb
Host smart-d57ed94c-f7bf-43f0-9adb-089bf1a3e1c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316518847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3316518847
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2722911674
Short name T712
Test name
Test status
Simulation time 11328748560 ps
CPU time 74.03 seconds
Started Feb 04 02:44:05 PM PST 24
Finished Feb 04 02:45:34 PM PST 24
Peak memory 197792 kb
Host smart-65cf5633-e6bd-42c6-9587-3e6f5d2c1444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722911674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2722911674
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2733756204
Short name T751
Test name
Test status
Simulation time 27651166527 ps
CPU time 293.74 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:48:52 PM PST 24
Peak memory 206208 kb
Host smart-a798d3dc-ee26-4d8f-a648-e5f13b4d3919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2733756204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2733756204
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3269143954
Short name T611
Test name
Test status
Simulation time 27317720 ps
CPU time 0.57 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:44:21 PM PST 24
Peak memory 193764 kb
Host smart-98da6af6-c737-4637-ade2-0d37ab57d87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269143954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3269143954
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3157227671
Short name T598
Test name
Test status
Simulation time 93631432 ps
CPU time 0.69 seconds
Started Feb 04 02:43:58 PM PST 24
Finished Feb 04 02:44:10 PM PST 24
Peak memory 194708 kb
Host smart-82ae3f6d-94e7-45a3-9133-f95b881f2ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157227671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3157227671
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.412750869
Short name T476
Test name
Test status
Simulation time 1259875513 ps
CPU time 8.7 seconds
Started Feb 04 02:43:48 PM PST 24
Finished Feb 04 02:44:03 PM PST 24
Peak memory 196772 kb
Host smart-8ca96496-55c2-4f20-ab58-64e60ecedf22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412750869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.412750869
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.127051694
Short name T777
Test name
Test status
Simulation time 112349927 ps
CPU time 0.78 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:44:00 PM PST 24
Peak memory 195764 kb
Host smart-f55d1ac9-0404-40b8-b418-8bb0a87a13fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127051694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.127051694
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.804712156
Short name T576
Test name
Test status
Simulation time 163477963 ps
CPU time 1.26 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:43:59 PM PST 24
Peak memory 197188 kb
Host smart-07bfa496-eb9a-427d-a8ac-a50d6b0add9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804712156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.804712156
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3368628574
Short name T650
Test name
Test status
Simulation time 176252969 ps
CPU time 3.53 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:44:00 PM PST 24
Peak memory 197816 kb
Host smart-c720a925-264b-4e4b-af19-063610479173
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368628574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3368628574
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3204607810
Short name T482
Test name
Test status
Simulation time 60002729 ps
CPU time 1.47 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 195296 kb
Host smart-3ee71dc9-f482-4ed3-8721-e34ff2aa94e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204607810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3204607810
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.780513576
Short name T652
Test name
Test status
Simulation time 41872845 ps
CPU time 0.86 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:05 PM PST 24
Peak memory 195732 kb
Host smart-1009c68e-fc2c-4368-9996-d8c76fc61c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780513576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.780513576
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3610976182
Short name T833
Test name
Test status
Simulation time 26171516 ps
CPU time 0.93 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 195640 kb
Host smart-e635d788-5fdc-4f82-a5a8-d09eb67bcfe0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610976182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3610976182
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2509044998
Short name T306
Test name
Test status
Simulation time 726040926 ps
CPU time 5.63 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:44:01 PM PST 24
Peak memory 197828 kb
Host smart-597dbc9f-fded-4284-b8b2-12b1c5630b12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509044998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2509044998
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.718853762
Short name T582
Test name
Test status
Simulation time 146949624 ps
CPU time 0.71 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:18 PM PST 24
Peak memory 194728 kb
Host smart-42785aae-0862-41f0-8191-2463282c2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718853762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.718853762
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2825428349
Short name T371
Test name
Test status
Simulation time 709296926 ps
CPU time 0.9 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:43:57 PM PST 24
Peak memory 196860 kb
Host smart-951abd62-eb05-4867-b064-bc3ae0925563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825428349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2825428349
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4239891503
Short name T323
Test name
Test status
Simulation time 71774357930 ps
CPU time 195.28 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:47:34 PM PST 24
Peak memory 197644 kb
Host smart-4fd472f8-f92f-4c82-9b6a-7f833bdbdb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239891503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4239891503
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4027877352
Short name T694
Test name
Test status
Simulation time 225375876649 ps
CPU time 823.81 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:57:47 PM PST 24
Peak memory 197980 kb
Host smart-68ae46dd-9548-4b42-b7ea-96c4ef7a182d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4027877352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.4027877352
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1169722340
Short name T689
Test name
Test status
Simulation time 14402799 ps
CPU time 0.56 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 193448 kb
Host smart-c4113104-1477-4c85-b0e9-b5c34d4a2748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169722340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1169722340
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1923850489
Short name T758
Test name
Test status
Simulation time 177849585 ps
CPU time 0.6 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 193480 kb
Host smart-6879c4ef-3c66-4c8e-8043-f44450296e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923850489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1923850489
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.898072838
Short name T257
Test name
Test status
Simulation time 341541039 ps
CPU time 10.64 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 196232 kb
Host smart-4fdb2b15-0615-44e3-a9b2-e24746887d19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898072838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.898072838
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.797379243
Short name T263
Test name
Test status
Simulation time 42602582 ps
CPU time 0.79 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:07 PM PST 24
Peak memory 194556 kb
Host smart-b46b563e-801a-46cb-b21c-eeaa9d246863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797379243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.797379243
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1033786967
Short name T865
Test name
Test status
Simulation time 164850377 ps
CPU time 1.34 seconds
Started Feb 04 02:43:50 PM PST 24
Finished Feb 04 02:43:59 PM PST 24
Peak memory 196680 kb
Host smart-6f600127-2de1-46d9-83e1-1b185cdb041c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033786967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1033786967
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2165650698
Short name T740
Test name
Test status
Simulation time 101835550 ps
CPU time 2.24 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 197820 kb
Host smart-5746b4ad-2586-4cc8-b9be-feb0a81397c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165650698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2165650698
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1454884430
Short name T311
Test name
Test status
Simulation time 479394169 ps
CPU time 3.65 seconds
Started Feb 04 02:43:52 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 195548 kb
Host smart-f3eb6cf5-0c09-4f4b-8dfc-9cdb624b7006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454884430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1454884430
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3255165988
Short name T742
Test name
Test status
Simulation time 54093131 ps
CPU time 0.83 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 195272 kb
Host smart-45bcb7bf-e9f0-4d88-9194-9c8b5f546052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255165988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3255165988
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4145124681
Short name T681
Test name
Test status
Simulation time 136420916 ps
CPU time 1.29 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 197524 kb
Host smart-f43d4d7a-d796-459b-b5fa-f4cc6fcae99c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145124681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4145124681
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.835922529
Short name T383
Test name
Test status
Simulation time 160897142 ps
CPU time 3.89 seconds
Started Feb 04 02:43:53 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 197748 kb
Host smart-3a41c9e4-a1b4-4c12-b508-59a5151247a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835922529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.835922529
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.428162832
Short name T351
Test name
Test status
Simulation time 42172865 ps
CPU time 1.2 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:43:58 PM PST 24
Peak memory 196940 kb
Host smart-0244c105-c791-4056-bac0-a7ba29e1fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428162832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.428162832
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.70209924
Short name T321
Test name
Test status
Simulation time 58231692 ps
CPU time 0.75 seconds
Started Feb 04 02:43:52 PM PST 24
Finished Feb 04 02:44:01 PM PST 24
Peak memory 195044 kb
Host smart-cce059e9-e62d-44a7-85c1-a5423722037b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70209924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.70209924
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3181124828
Short name T726
Test name
Test status
Simulation time 3387967287 ps
CPU time 89.08 seconds
Started Feb 04 02:43:49 PM PST 24
Finished Feb 04 02:45:25 PM PST 24
Peak memory 197868 kb
Host smart-0207f184-bdbe-49d6-bb6e-c63b8ec42f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181124828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3181124828
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2294643466
Short name T575
Test name
Test status
Simulation time 69854882846 ps
CPU time 1136.86 seconds
Started Feb 04 02:43:53 PM PST 24
Finished Feb 04 03:02:59 PM PST 24
Peak memory 198012 kb
Host smart-73885d07-dc21-48d1-bfb7-befe39c379b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2294643466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2294643466
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.295076311
Short name T760
Test name
Test status
Simulation time 18291645 ps
CPU time 0.57 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 193696 kb
Host smart-8e684925-2b42-430e-9caa-1deb6767f208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295076311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.295076311
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3209840631
Short name T517
Test name
Test status
Simulation time 74843509 ps
CPU time 0.79 seconds
Started Feb 04 02:44:05 PM PST 24
Finished Feb 04 02:44:21 PM PST 24
Peak memory 195116 kb
Host smart-d68b6d81-2199-4865-9e0d-9dd03f22a7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209840631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3209840631
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3170875473
Short name T813
Test name
Test status
Simulation time 515356781 ps
CPU time 6.13 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:24 PM PST 24
Peak memory 196784 kb
Host smart-68b0c5a6-4297-4ded-913a-9bad953ba659
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170875473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3170875473
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1721240248
Short name T456
Test name
Test status
Simulation time 230483484 ps
CPU time 0.94 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 197556 kb
Host smart-26fa0109-6782-4867-9913-a8125021cb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721240248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1721240248
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1299301519
Short name T467
Test name
Test status
Simulation time 56414816 ps
CPU time 1.1 seconds
Started Feb 04 02:43:59 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 196524 kb
Host smart-98dcebbd-979f-447d-8310-7d0226613a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299301519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1299301519
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3112685164
Short name T489
Test name
Test status
Simulation time 253722619 ps
CPU time 2.49 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:08 PM PST 24
Peak memory 197864 kb
Host smart-6d47567f-35d9-4aa8-b45f-8e4b809a8be1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112685164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3112685164
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.881402907
Short name T759
Test name
Test status
Simulation time 138569917 ps
CPU time 0.98 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:21 PM PST 24
Peak memory 195680 kb
Host smart-33441427-a9c0-40f2-a1c1-f928806f5c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881402907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
881402907
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3271775243
Short name T711
Test name
Test status
Simulation time 69202675 ps
CPU time 1.26 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:12 PM PST 24
Peak memory 196708 kb
Host smart-469f67d6-2ef4-4b6b-aeb4-b5c5d98819e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271775243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3271775243
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.809647274
Short name T755
Test name
Test status
Simulation time 35707034 ps
CPU time 1.29 seconds
Started Feb 04 02:43:59 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 197720 kb
Host smart-81984dd9-1a3e-437f-a7d8-e45142371b20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809647274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.809647274
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1575863238
Short name T724
Test name
Test status
Simulation time 255533906 ps
CPU time 2.34 seconds
Started Feb 04 02:44:01 PM PST 24
Finished Feb 04 02:44:18 PM PST 24
Peak memory 197796 kb
Host smart-ce1c0ea6-c656-4ae9-9009-652c9461e84e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575863238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1575863238
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.260938805
Short name T525
Test name
Test status
Simulation time 127175819 ps
CPU time 1.2 seconds
Started Feb 04 02:43:53 PM PST 24
Finished Feb 04 02:44:03 PM PST 24
Peak memory 195492 kb
Host smart-2f03f763-da3a-4429-9c6e-82e034d676ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260938805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.260938805
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1474671676
Short name T376
Test name
Test status
Simulation time 37837760 ps
CPU time 1.21 seconds
Started Feb 04 02:43:58 PM PST 24
Finished Feb 04 02:44:10 PM PST 24
Peak memory 195556 kb
Host smart-75c70f55-36aa-4cf3-a452-7f81247841cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474671676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1474671676
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1744209651
Short name T35
Test name
Test status
Simulation time 8911428139 ps
CPU time 101.72 seconds
Started Feb 04 02:44:01 PM PST 24
Finished Feb 04 02:45:59 PM PST 24
Peak memory 197892 kb
Host smart-87c2609c-8157-42a6-b9c3-b48f67ee8b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744209651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1744209651
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.479336972
Short name T583
Test name
Test status
Simulation time 32632394 ps
CPU time 0.56 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:05 PM PST 24
Peak memory 194400 kb
Host smart-6ea8797f-f71f-4aa3-9afd-53306b06e321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479336972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.479336972
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2240754773
Short name T790
Test name
Test status
Simulation time 57255704 ps
CPU time 1 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 196988 kb
Host smart-d5d62e5c-89ca-42b6-a4ab-0b0dca48c4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240754773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2240754773
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.97783764
Short name T47
Test name
Test status
Simulation time 205922086 ps
CPU time 6.79 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:13 PM PST 24
Peak memory 195332 kb
Host smart-e318df46-b504-49cb-a0fb-84e5fe1461c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97783764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.97783764
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3799796689
Short name T671
Test name
Test status
Simulation time 185340903 ps
CPU time 0.88 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 196296 kb
Host smart-d730856d-8407-410e-bad4-4d4972afb67c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799796689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3799796689
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.415424568
Short name T765
Test name
Test status
Simulation time 198372954 ps
CPU time 0.75 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:05 PM PST 24
Peak memory 195188 kb
Host smart-a547b101-dd7e-4b74-a0a3-c0988860854e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415424568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.415424568
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2496815504
Short name T665
Test name
Test status
Simulation time 27341034 ps
CPU time 1.39 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:16 PM PST 24
Peak memory 197676 kb
Host smart-c7650967-fc02-457e-afc0-0e27dafb6168
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496815504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2496815504
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1791840803
Short name T538
Test name
Test status
Simulation time 172534039 ps
CPU time 3.54 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:10 PM PST 24
Peak memory 196300 kb
Host smart-f2cfc72b-d14c-489b-84b9-7ebb0eec980d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791840803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1791840803
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2112086786
Short name T882
Test name
Test status
Simulation time 22196455 ps
CPU time 0.81 seconds
Started Feb 04 02:43:58 PM PST 24
Finished Feb 04 02:44:09 PM PST 24
Peak memory 195428 kb
Host smart-1b2e9373-e667-40bf-8b74-6e8d704e3b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112086786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2112086786
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1660040715
Short name T707
Test name
Test status
Simulation time 32191289 ps
CPU time 0.71 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:07 PM PST 24
Peak memory 196024 kb
Host smart-e71e2cce-b7bb-433e-850a-e3f4b56f7a75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660040715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1660040715
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.184303317
Short name T881
Test name
Test status
Simulation time 1355555621 ps
CPU time 4.84 seconds
Started Feb 04 02:44:05 PM PST 24
Finished Feb 04 02:44:25 PM PST 24
Peak memory 197636 kb
Host smart-089a87e4-aa7c-4c33-bb94-95509fdd06fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184303317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.184303317
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2461913076
Short name T468
Test name
Test status
Simulation time 67600915 ps
CPU time 1.11 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:21 PM PST 24
Peak memory 196232 kb
Host smart-86b84c73-7405-4336-8dd0-fe43c91cd987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461913076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2461913076
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1537452309
Short name T491
Test name
Test status
Simulation time 129056064 ps
CPU time 1 seconds
Started Feb 04 02:43:55 PM PST 24
Finished Feb 04 02:44:04 PM PST 24
Peak memory 195344 kb
Host smart-9897c619-1a7c-4c55-aac4-0dc6c1c0462a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537452309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1537452309
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.965435240
Short name T844
Test name
Test status
Simulation time 14872306856 ps
CPU time 164.55 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:47:05 PM PST 24
Peak memory 197796 kb
Host smart-60c44a9e-c2a6-4d69-b031-bd45a9f04668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965435240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.965435240
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1835213942
Short name T424
Test name
Test status
Simulation time 120412681276 ps
CPU time 952.1 seconds
Started Feb 04 02:43:59 PM PST 24
Finished Feb 04 03:00:02 PM PST 24
Peak memory 198040 kb
Host smart-2286b345-40e7-4a36-a7bc-99720859fb18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1835213942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1835213942
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.104266089
Short name T862
Test name
Test status
Simulation time 17104102 ps
CPU time 0.57 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 193684 kb
Host smart-6ccbcb09-3320-42c2-8c63-3a84391942bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104266089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.104266089
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4091718205
Short name T236
Test name
Test status
Simulation time 94304306 ps
CPU time 0.78 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 194600 kb
Host smart-db96c008-d4ef-4d07-bca0-a779b877bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091718205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4091718205
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2772614777
Short name T684
Test name
Test status
Simulation time 985806550 ps
CPU time 25.37 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:43 PM PST 24
Peak memory 196584 kb
Host smart-61ce4bc7-eeac-41e7-9565-83ab87562590
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772614777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2772614777
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3083288402
Short name T494
Test name
Test status
Simulation time 409367105 ps
CPU time 0.86 seconds
Started Feb 04 02:44:03 PM PST 24
Finished Feb 04 02:44:20 PM PST 24
Peak memory 195768 kb
Host smart-c481703c-c857-4968-b533-a076801fa64b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083288402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3083288402
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3874968755
Short name T377
Test name
Test status
Simulation time 137225310 ps
CPU time 0.77 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 196112 kb
Host smart-8a572254-2680-48f4-ab19-e5a9ca6c620b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874968755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3874968755
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2124993498
Short name T593
Test name
Test status
Simulation time 58526891 ps
CPU time 2.16 seconds
Started Feb 04 02:43:57 PM PST 24
Finished Feb 04 02:44:07 PM PST 24
Peak memory 197788 kb
Host smart-2f7f5e88-653b-4cf9-a0bd-8fc9e8c60da5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124993498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2124993498
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1257253481
Short name T304
Test name
Test status
Simulation time 98530866 ps
CPU time 1.63 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:16 PM PST 24
Peak memory 195552 kb
Host smart-ea57c150-1e78-4cfc-8b88-0f69bce6ef16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257253481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1257253481
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.242836675
Short name T840
Test name
Test status
Simulation time 126162437 ps
CPU time 0.68 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 194248 kb
Host smart-9016f783-5c7b-4cf6-a4d1-92d83041b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242836675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.242836675
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.353065701
Short name T373
Test name
Test status
Simulation time 49503072 ps
CPU time 0.79 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:18 PM PST 24
Peak memory 195280 kb
Host smart-2102a536-a02d-405c-aca7-8a9f45dfc694
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353065701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.353065701
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.274792699
Short name T217
Test name
Test status
Simulation time 359264931 ps
CPU time 4.09 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:15 PM PST 24
Peak memory 197720 kb
Host smart-d37e116c-5982-4405-8058-168f4bd948e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274792699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.274792699
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.349795150
Short name T374
Test name
Test status
Simulation time 157396331 ps
CPU time 0.94 seconds
Started Feb 04 02:44:01 PM PST 24
Finished Feb 04 02:44:17 PM PST 24
Peak memory 195360 kb
Host smart-d2d67ef8-214d-451c-b0a2-67ce8146290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349795150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.349795150
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.901488193
Short name T808
Test name
Test status
Simulation time 64122690 ps
CPU time 1.24 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 195460 kb
Host smart-59e5af48-1f43-44ec-82b9-de96e395f715
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901488193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.901488193
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2182504726
Short name T317
Test name
Test status
Simulation time 80510099365 ps
CPU time 153.32 seconds
Started Feb 04 02:44:01 PM PST 24
Finished Feb 04 02:46:50 PM PST 24
Peak memory 197860 kb
Host smart-411734f9-ba8d-4980-8239-852a43335676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182504726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2182504726
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1033615367
Short name T511
Test name
Test status
Simulation time 238483555816 ps
CPU time 1690.91 seconds
Started Feb 04 02:43:59 PM PST 24
Finished Feb 04 03:12:21 PM PST 24
Peak memory 198024 kb
Host smart-24e0b210-0ac3-4074-9813-3111f36fc8a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1033615367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1033615367
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2030030452
Short name T50
Test name
Test status
Simulation time 98515026 ps
CPU time 0.57 seconds
Started Feb 04 02:44:25 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 194376 kb
Host smart-4b76acfb-cbe2-49ae-b331-699969573d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030030452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2030030452
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2700654624
Short name T451
Test name
Test status
Simulation time 77653584 ps
CPU time 0.84 seconds
Started Feb 04 02:44:02 PM PST 24
Finished Feb 04 02:44:19 PM PST 24
Peak memory 194996 kb
Host smart-da86eb7c-8c12-414c-89b4-876276c43d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700654624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2700654624
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4149729734
Short name T241
Test name
Test status
Simulation time 990480940 ps
CPU time 24.53 seconds
Started Feb 04 02:44:17 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 196744 kb
Host smart-94de8426-143d-4c84-8d4c-806cecb3ea22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149729734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4149729734
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1913362662
Short name T622
Test name
Test status
Simulation time 58273081 ps
CPU time 0.63 seconds
Started Feb 04 02:44:16 PM PST 24
Finished Feb 04 02:44:23 PM PST 24
Peak memory 194444 kb
Host smart-08461bfe-861a-428c-a6a9-a61909ef1cf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913362662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1913362662
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.788731556
Short name T730
Test name
Test status
Simulation time 101334882 ps
CPU time 1.38 seconds
Started Feb 04 02:44:04 PM PST 24
Finished Feb 04 02:44:22 PM PST 24
Peak memory 196872 kb
Host smart-0c3d182c-12b2-40de-ba75-5e6793877e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788731556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.788731556
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1555607557
Short name T375
Test name
Test status
Simulation time 302632961 ps
CPU time 3.37 seconds
Started Feb 04 02:44:25 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 196060 kb
Host smart-4e76b155-5b7f-4080-9a63-8b74041c3063
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555607557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1555607557
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4286975419
Short name T411
Test name
Test status
Simulation time 110491651 ps
CPU time 1.44 seconds
Started Feb 04 02:44:16 PM PST 24
Finished Feb 04 02:44:24 PM PST 24
Peak memory 196592 kb
Host smart-dd6c53ab-9d18-4dfb-bfa1-c6f4c201779b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286975419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4286975419
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4112111931
Short name T816
Test name
Test status
Simulation time 120888358 ps
CPU time 1.25 seconds
Started Feb 04 02:43:59 PM PST 24
Finished Feb 04 02:44:11 PM PST 24
Peak memory 196732 kb
Host smart-287ee9fa-73bd-4d3c-8288-0195d77efdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112111931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4112111931
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1366273194
Short name T608
Test name
Test status
Simulation time 69410804 ps
CPU time 1.34 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:07 PM PST 24
Peak memory 196408 kb
Host smart-e33f7fd4-23c9-404b-a985-4bb5f5391499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366273194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1366273194
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1220852843
Short name T763
Test name
Test status
Simulation time 95413649 ps
CPU time 3.99 seconds
Started Feb 04 02:44:18 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 197716 kb
Host smart-27253682-ecf9-4e6a-b7ae-a661d43e63a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220852843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1220852843
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2733508097
Short name T573
Test name
Test status
Simulation time 650737874 ps
CPU time 1.13 seconds
Started Feb 04 02:44:00 PM PST 24
Finished Feb 04 02:44:12 PM PST 24
Peak memory 196048 kb
Host smart-2c814031-e46b-42be-b0b7-a56fd905c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733508097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2733508097
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1799630785
Short name T474
Test name
Test status
Simulation time 154638134 ps
CPU time 1.05 seconds
Started Feb 04 02:43:56 PM PST 24
Finished Feb 04 02:44:06 PM PST 24
Peak memory 195392 kb
Host smart-9cda389d-f414-4411-a297-3f12306d0826
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799630785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1799630785
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4258482638
Short name T336
Test name
Test status
Simulation time 9680808051 ps
CPU time 133.26 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:46:53 PM PST 24
Peak memory 197856 kb
Host smart-16602a96-8d98-4cfc-a155-438d28610750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258482638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4258482638
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1837799632
Short name T847
Test name
Test status
Simulation time 92508145663 ps
CPU time 873.87 seconds
Started Feb 04 02:44:20 PM PST 24
Finished Feb 04 02:58:59 PM PST 24
Peak memory 198028 kb
Host smart-918a040d-fb00-4e0f-972b-4d29daa5acd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1837799632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1837799632
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1911115185
Short name T626
Test name
Test status
Simulation time 21866919 ps
CPU time 0.58 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 193664 kb
Host smart-f1f6219b-66ae-41d9-9ec2-63b075efe3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911115185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1911115185
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.454985018
Short name T676
Test name
Test status
Simulation time 113208903 ps
CPU time 0.97 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 196396 kb
Host smart-1127136b-76d8-49c2-b80d-a571321ddb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454985018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.454985018
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1531766812
Short name T522
Test name
Test status
Simulation time 483230246 ps
CPU time 6.48 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 195340 kb
Host smart-bf22bb5d-5b81-4da9-a6d6-4f6be3364dba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531766812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1531766812
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3208833682
Short name T276
Test name
Test status
Simulation time 230484636 ps
CPU time 1.09 seconds
Started Feb 04 02:42:23 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 197796 kb
Host smart-2e0839d2-d25a-4298-a3d8-296b437d122f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208833682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3208833682
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.267323306
Short name T733
Test name
Test status
Simulation time 124651676 ps
CPU time 1.11 seconds
Started Feb 04 02:42:18 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 195784 kb
Host smart-0ba8b865-932d-4b21-870e-70a13690d72a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267323306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.267323306
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2594580316
Short name T836
Test name
Test status
Simulation time 145845311 ps
CPU time 3.07 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:26 PM PST 24
Peak memory 197668 kb
Host smart-6899e3ec-88ac-47d4-96ce-41447e66b176
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594580316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2594580316
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2689316032
Short name T418
Test name
Test status
Simulation time 142155872 ps
CPU time 2.87 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:42:26 PM PST 24
Peak memory 197848 kb
Host smart-e64059a4-498d-4965-9153-a50b4ebaca81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689316032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2689316032
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1210804334
Short name T738
Test name
Test status
Simulation time 33725863 ps
CPU time 0.95 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 196300 kb
Host smart-0ecafa23-9a27-4e8f-9612-bae8a487b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210804334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1210804334
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.568165966
Short name T823
Test name
Test status
Simulation time 92460800 ps
CPU time 1.1 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 195884 kb
Host smart-91555175-e9d0-4855-ba13-151c41484f1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568165966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.568165966
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.257844674
Short name T524
Test name
Test status
Simulation time 68093949 ps
CPU time 1.24 seconds
Started Feb 04 02:42:17 PM PST 24
Finished Feb 04 02:42:22 PM PST 24
Peak memory 196268 kb
Host smart-80740e49-de6a-41ff-9215-6d2ec3bc72a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257844674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.257844674
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3361591355
Short name T27
Test name
Test status
Simulation time 174169758 ps
CPU time 0.81 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 213280 kb
Host smart-452c3f98-6ffd-4f34-9368-f1e37950e9a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361591355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3361591355
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3593396730
Short name T690
Test name
Test status
Simulation time 31196504 ps
CPU time 0.98 seconds
Started Feb 04 02:42:21 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 195564 kb
Host smart-1a9d9d3d-8625-46ef-ba13-a68858ba26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593396730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3593396730
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1615516052
Short name T390
Test name
Test status
Simulation time 32082674 ps
CPU time 0.67 seconds
Started Feb 04 02:42:23 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 193872 kb
Host smart-d32915a7-426e-4923-8ff4-c8b893c16f93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615516052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1615516052
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1516997147
Short name T443
Test name
Test status
Simulation time 25078710548 ps
CPU time 166.2 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:45:09 PM PST 24
Peak memory 197908 kb
Host smart-74ef96de-caf7-4d83-bbe3-0022ec0c3b36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516997147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1516997147
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3847059249
Short name T610
Test name
Test status
Simulation time 95345780872 ps
CPU time 217.86 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:46:15 PM PST 24
Peak memory 206224 kb
Host smart-e90fff9d-52e0-40ec-85c3-a4be4fca449a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3847059249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3847059249
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.420014161
Short name T49
Test name
Test status
Simulation time 30908505 ps
CPU time 0.55 seconds
Started Feb 04 02:44:19 PM PST 24
Finished Feb 04 02:44:25 PM PST 24
Peak memory 193404 kb
Host smart-af156990-9763-450a-8749-04b2cbb40c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420014161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.420014161
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.904951587
Short name T391
Test name
Test status
Simulation time 30335850 ps
CPU time 0.91 seconds
Started Feb 04 02:44:17 PM PST 24
Finished Feb 04 02:44:24 PM PST 24
Peak memory 196332 kb
Host smart-4ab053ee-f700-4b7b-9135-f06fd32b78d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904951587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.904951587
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.8278556
Short name T647
Test name
Test status
Simulation time 1410869250 ps
CPU time 16.65 seconds
Started Feb 04 02:44:21 PM PST 24
Finished Feb 04 02:44:42 PM PST 24
Peak memory 196648 kb
Host smart-6c0a8790-8e9e-45e7-b28b-0619ff987c37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8278556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress.8278556
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2433568177
Short name T431
Test name
Test status
Simulation time 303162295 ps
CPU time 0.66 seconds
Started Feb 04 02:44:20 PM PST 24
Finished Feb 04 02:44:26 PM PST 24
Peak memory 194340 kb
Host smart-3655128f-db3c-4a15-b073-407f3a1f1139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433568177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2433568177
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1668264922
Short name T353
Test name
Test status
Simulation time 75259474 ps
CPU time 1.39 seconds
Started Feb 04 02:44:24 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 196576 kb
Host smart-29a5cf0c-7dcf-464d-a779-3eeb945eaf07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668264922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1668264922
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.639391292
Short name T717
Test name
Test status
Simulation time 134901508 ps
CPU time 2.23 seconds
Started Feb 04 02:44:31 PM PST 24
Finished Feb 04 02:44:35 PM PST 24
Peak memory 197748 kb
Host smart-5d327815-ab6b-441f-bca8-362d028aa627
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639391292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.639391292
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2473973312
Short name T580
Test name
Test status
Simulation time 236464638 ps
CPU time 2.11 seconds
Started Feb 04 02:44:20 PM PST 24
Finished Feb 04 02:44:27 PM PST 24
Peak memory 196624 kb
Host smart-cde5e50b-8f28-402b-81b8-8a78620e7eb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473973312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2473973312
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1778929192
Short name T287
Test name
Test status
Simulation time 48435690 ps
CPU time 1.05 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:44:39 PM PST 24
Peak memory 195616 kb
Host smart-12814994-b3c4-4a12-a479-45a6b41100d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778929192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1778929192
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1115254712
Short name T533
Test name
Test status
Simulation time 71976842 ps
CPU time 0.9 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:30 PM PST 24
Peak memory 195752 kb
Host smart-4cc03379-5318-42f7-abdb-91a1c5c37034
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115254712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1115254712
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1003385577
Short name T824
Test name
Test status
Simulation time 135681597 ps
CPU time 6.2 seconds
Started Feb 04 02:44:15 PM PST 24
Finished Feb 04 02:44:29 PM PST 24
Peak memory 197736 kb
Host smart-a83fb614-0aa7-4998-9e5c-3e2620bfcd5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003385577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1003385577
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.119309054
Short name T280
Test name
Test status
Simulation time 251787233 ps
CPU time 1.3 seconds
Started Feb 04 02:44:18 PM PST 24
Finished Feb 04 02:44:25 PM PST 24
Peak memory 197696 kb
Host smart-255c0dac-353c-4553-a04f-6338c946fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119309054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.119309054
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2188744413
Short name T683
Test name
Test status
Simulation time 828666693 ps
CPU time 0.99 seconds
Started Feb 04 02:44:18 PM PST 24
Finished Feb 04 02:44:25 PM PST 24
Peak memory 196168 kb
Host smart-68446acf-48ee-4018-ad5a-ed54c418a5e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188744413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2188744413
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2055145211
Short name T599
Test name
Test status
Simulation time 109590297502 ps
CPU time 92.46 seconds
Started Feb 04 02:44:26 PM PST 24
Finished Feb 04 02:46:01 PM PST 24
Peak memory 197820 kb
Host smart-d30f4030-e67f-470a-b866-42c15a9c311c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055145211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2055145211
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1153092529
Short name T552
Test name
Test status
Simulation time 178183515198 ps
CPU time 1882.63 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 03:15:53 PM PST 24
Peak memory 198012 kb
Host smart-1d09866c-7d33-4360-8e64-666cb6feaeab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1153092529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1153092529
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3662662835
Short name T756
Test name
Test status
Simulation time 79590170 ps
CPU time 0.57 seconds
Started Feb 04 02:44:25 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 194380 kb
Host smart-e1d08737-843d-4453-ab05-a521a62a660f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662662835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3662662835
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1186101317
Short name T512
Test name
Test status
Simulation time 97725313 ps
CPU time 0.76 seconds
Started Feb 04 02:44:18 PM PST 24
Finished Feb 04 02:44:24 PM PST 24
Peak memory 195100 kb
Host smart-3e75e5c3-1a06-4ae9-9964-d14dd2a101f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186101317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1186101317
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1579565698
Short name T215
Test name
Test status
Simulation time 132377571 ps
CPU time 4.79 seconds
Started Feb 04 02:44:19 PM PST 24
Finished Feb 04 02:44:29 PM PST 24
Peak memory 195980 kb
Host smart-3ee36c82-83b5-45c8-8a00-d668a5038310
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579565698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1579565698
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1239556451
Short name T309
Test name
Test status
Simulation time 30461068 ps
CPU time 0.69 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 195144 kb
Host smart-6df7aacc-a14f-467b-a68b-e7c4682d18eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239556451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1239556451
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2971175587
Short name T268
Test name
Test status
Simulation time 240844576 ps
CPU time 1.34 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 196668 kb
Host smart-899f19ab-f290-45b9-a4fe-34b094c01f6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971175587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2971175587
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.557115298
Short name T430
Test name
Test status
Simulation time 136538426 ps
CPU time 1.51 seconds
Started Feb 04 02:44:23 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 196544 kb
Host smart-e26f48d4-f8f8-4503-86a7-e69dbde100b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557115298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.557115298
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3153219585
Short name T543
Test name
Test status
Simulation time 1220577834 ps
CPU time 1.85 seconds
Started Feb 04 02:44:23 PM PST 24
Finished Feb 04 02:44:29 PM PST 24
Peak memory 195936 kb
Host smart-e63eaa0f-f3cd-4435-b80a-0ecbbba24621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153219585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3153219585
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3253478377
Short name T778
Test name
Test status
Simulation time 338300072 ps
CPU time 1.24 seconds
Started Feb 04 02:44:16 PM PST 24
Finished Feb 04 02:44:24 PM PST 24
Peak memory 196836 kb
Host smart-d40e2261-90fc-413e-9bcc-83cd13c53549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253478377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3253478377
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.159433481
Short name T637
Test name
Test status
Simulation time 242537223 ps
CPU time 1.11 seconds
Started Feb 04 02:44:23 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 195728 kb
Host smart-a1476d0b-bb29-4491-8cd2-6ce767fe9aeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159433481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.159433481
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2772517261
Short name T272
Test name
Test status
Simulation time 421919795 ps
CPU time 2.08 seconds
Started Feb 04 02:44:52 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 197800 kb
Host smart-afb290bf-0075-4b10-ade5-2150c2550a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772517261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2772517261
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4164492454
Short name T318
Test name
Test status
Simulation time 36647898 ps
CPU time 1.05 seconds
Started Feb 04 02:44:20 PM PST 24
Finished Feb 04 02:44:26 PM PST 24
Peak memory 195528 kb
Host smart-7d847a64-025c-4ef2-a638-103affc9698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164492454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4164492454
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1307313076
Short name T267
Test name
Test status
Simulation time 34485099 ps
CPU time 0.97 seconds
Started Feb 04 02:44:13 PM PST 24
Finished Feb 04 02:44:23 PM PST 24
Peak memory 195620 kb
Host smart-4d021d0d-5f06-4d07-b366-6b00dafbbf2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307313076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1307313076
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3376324342
Short name T307
Test name
Test status
Simulation time 18649923841 ps
CPU time 61.36 seconds
Started Feb 04 02:44:48 PM PST 24
Finished Feb 04 02:46:06 PM PST 24
Peak memory 197952 kb
Host smart-3ddb8af9-aa1b-4d27-bc4a-a275739f3b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376324342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3376324342
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3415295119
Short name T858
Test name
Test status
Simulation time 97884836784 ps
CPU time 1371.9 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 03:07:40 PM PST 24
Peak memory 197984 kb
Host smart-8434128f-f548-4688-a26f-2c1861a793f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3415295119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3415295119
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1207741527
Short name T820
Test name
Test status
Simulation time 12608206 ps
CPU time 0.59 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:44:40 PM PST 24
Peak memory 194828 kb
Host smart-02d69830-98d7-407b-8511-ee12819e6fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207741527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1207741527
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.933101384
Short name T277
Test name
Test status
Simulation time 22242563 ps
CPU time 0.69 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:44:41 PM PST 24
Peak memory 194804 kb
Host smart-05f4fc8a-8962-4de1-911f-7658305eed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933101384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.933101384
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3124279760
Short name T636
Test name
Test status
Simulation time 966476424 ps
CPU time 7.01 seconds
Started Feb 04 02:44:39 PM PST 24
Finished Feb 04 02:44:53 PM PST 24
Peak memory 196724 kb
Host smart-120f6020-c1aa-41c7-bcdf-02397d7996a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124279760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3124279760
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3809781961
Short name T370
Test name
Test status
Simulation time 99320447 ps
CPU time 0.67 seconds
Started Feb 04 02:44:57 PM PST 24
Finished Feb 04 02:45:19 PM PST 24
Peak memory 194416 kb
Host smart-7721f31d-0443-478c-9f44-eb7520ce9c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809781961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3809781961
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1737808202
Short name T235
Test name
Test status
Simulation time 195419652 ps
CPU time 0.97 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 196364 kb
Host smart-356f6814-1dcf-45a9-9ebf-ca02aea74db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737808202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1737808202
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.700815888
Short name T406
Test name
Test status
Simulation time 78034276 ps
CPU time 3.15 seconds
Started Feb 04 02:44:25 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 197836 kb
Host smart-72df4c0c-290b-4a5b-8cb4-486376e52c24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700815888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.700815888
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.768486204
Short name T804
Test name
Test status
Simulation time 527477433 ps
CPU time 3.4 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:50 PM PST 24
Peak memory 197824 kb
Host smart-e30d22ca-f5ab-4d0b-8811-a6b56db01c2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768486204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
768486204
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4268906340
Short name T298
Test name
Test status
Simulation time 109985752 ps
CPU time 1.24 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 196636 kb
Host smart-6b84a7fb-766b-4818-8860-b351d9a3959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268906340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4268906340
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3065616743
Short name T829
Test name
Test status
Simulation time 299372770 ps
CPU time 1.25 seconds
Started Feb 04 02:44:23 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 196860 kb
Host smart-cefd2177-ac0e-4b07-abc1-13d965d7f8d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065616743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3065616743
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1175052797
Short name T516
Test name
Test status
Simulation time 1887883719 ps
CPU time 5.57 seconds
Started Feb 04 02:44:25 PM PST 24
Finished Feb 04 02:44:34 PM PST 24
Peak memory 197752 kb
Host smart-e2ed4e0b-852c-408a-8144-ae33812b56ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175052797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1175052797
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2602135779
Short name T563
Test name
Test status
Simulation time 643875707 ps
CPU time 0.99 seconds
Started Feb 04 02:44:23 PM PST 24
Finished Feb 04 02:44:28 PM PST 24
Peak memory 195332 kb
Host smart-533baac9-8511-483f-920f-b48c209b432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602135779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2602135779
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3389037622
Short name T566
Test name
Test status
Simulation time 82070684 ps
CPU time 1.05 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 02:44:32 PM PST 24
Peak memory 195360 kb
Host smart-b6049187-aba5-4194-aa9d-13ce922d5c73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389037622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3389037622
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3386499433
Short name T449
Test name
Test status
Simulation time 13817101638 ps
CPU time 120.07 seconds
Started Feb 04 02:44:35 PM PST 24
Finished Feb 04 02:46:36 PM PST 24
Peak memory 197888 kb
Host smart-967af022-f3aa-4cfe-b9f3-4747c932b796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386499433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3386499433
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2912160030
Short name T548
Test name
Test status
Simulation time 153586199014 ps
CPU time 744 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:56:54 PM PST 24
Peak memory 198060 kb
Host smart-604c9889-6ef7-4418-885c-d9bb0678afa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2912160030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2912160030
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2449490344
Short name T590
Test name
Test status
Simulation time 25683776 ps
CPU time 0.58 seconds
Started Feb 04 02:44:53 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 193920 kb
Host smart-bb641c39-5161-475b-92d3-d8856d8c2594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449490344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2449490344
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.596618180
Short name T641
Test name
Test status
Simulation time 20206090 ps
CPU time 0.66 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:44:41 PM PST 24
Peak memory 193900 kb
Host smart-34cf9560-3111-43e2-afef-e2f1806d8d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596618180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.596618180
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1347392611
Short name T223
Test name
Test status
Simulation time 805528587 ps
CPU time 10.52 seconds
Started Feb 04 02:44:46 PM PST 24
Finished Feb 04 02:45:11 PM PST 24
Peak memory 196752 kb
Host smart-62eccf21-700c-412e-a148-ed169c3aac9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347392611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1347392611
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.99796707
Short name T883
Test name
Test status
Simulation time 64085352 ps
CPU time 0.84 seconds
Started Feb 04 02:44:49 PM PST 24
Finished Feb 04 02:45:10 PM PST 24
Peak memory 195648 kb
Host smart-d1e2efbb-68d2-42f0-822e-9b64f1edc629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99796707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.99796707
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2530207536
Short name T643
Test name
Test status
Simulation time 691366432 ps
CPU time 1.24 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 196604 kb
Host smart-d194d159-6d1f-4fd4-b9a9-b3426a7336e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530207536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2530207536
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3021634790
Short name T596
Test name
Test status
Simulation time 99391237 ps
CPU time 1.19 seconds
Started Feb 04 02:44:49 PM PST 24
Finished Feb 04 02:45:09 PM PST 24
Peak memory 197424 kb
Host smart-080f71b9-689a-4138-a841-37318a63b8cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021634790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3021634790
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3956098581
Short name T425
Test name
Test status
Simulation time 55705056 ps
CPU time 0.94 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 194312 kb
Host smart-4220ffb1-2ad4-47ed-b75e-d425e8860345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956098581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3956098581
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.613839633
Short name T483
Test name
Test status
Simulation time 72125103 ps
CPU time 0.84 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 195364 kb
Host smart-4c9c1f88-f224-46e8-8cc8-8d7e689884ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613839633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.613839633
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1113621655
Short name T423
Test name
Test status
Simulation time 85202309 ps
CPU time 1 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 02:44:32 PM PST 24
Peak memory 195548 kb
Host smart-5885c14b-9fdb-4af1-b7d2-fdff8e2c4a79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113621655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1113621655
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.671251821
Short name T686
Test name
Test status
Simulation time 211850899 ps
CPU time 3.4 seconds
Started Feb 04 02:44:58 PM PST 24
Finished Feb 04 02:45:25 PM PST 24
Peak memory 197440 kb
Host smart-639869c9-f56d-454a-9419-4613a8e81907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671251821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.671251821
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3377963365
Short name T834
Test name
Test status
Simulation time 236178799 ps
CPU time 1.31 seconds
Started Feb 04 02:44:19 PM PST 24
Finished Feb 04 02:44:26 PM PST 24
Peak memory 196516 kb
Host smart-f2a97dab-1505-4eae-b70a-c974e3d1cacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377963365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3377963365
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3484225594
Short name T839
Test name
Test status
Simulation time 179335465 ps
CPU time 0.97 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:03 PM PST 24
Peak memory 196372 kb
Host smart-489dc5a7-f336-4e15-b639-00c498a81517
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484225594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3484225594
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3596923590
Short name T614
Test name
Test status
Simulation time 249183049079 ps
CPU time 216.53 seconds
Started Feb 04 02:44:51 PM PST 24
Finished Feb 04 02:48:51 PM PST 24
Peak memory 197832 kb
Host smart-3ae0286c-42f9-4b5d-8b9e-0a8637640cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596923590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3596923590
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.379197052
Short name T792
Test name
Test status
Simulation time 11549017418 ps
CPU time 307.28 seconds
Started Feb 04 02:44:59 PM PST 24
Finished Feb 04 02:50:30 PM PST 24
Peak memory 197952 kb
Host smart-8fad00b6-13f2-43bb-8ae4-b1cc643d858a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=379197052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.379197052
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1470283431
Short name T364
Test name
Test status
Simulation time 15460910 ps
CPU time 0.6 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 193668 kb
Host smart-5f6d690d-a475-4ab8-9d39-31709b193928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470283431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1470283431
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2964610727
Short name T722
Test name
Test status
Simulation time 39365576 ps
CPU time 0.91 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 196804 kb
Host smart-47112c7f-3a9d-440e-9911-564095d330e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964610727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2964610727
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1746019112
Short name T302
Test name
Test status
Simulation time 608152615 ps
CPU time 20.11 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:37 PM PST 24
Peak memory 197788 kb
Host smart-dae5d6cc-5c2f-4c3e-a3cd-2d95d55ca99a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746019112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1746019112
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2636583841
Short name T380
Test name
Test status
Simulation time 43813837 ps
CPU time 0.65 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:24 PM PST 24
Peak memory 194312 kb
Host smart-37151595-51bf-4efd-ae23-ce1476e8a81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636583841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2636583841
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4031229871
Short name T255
Test name
Test status
Simulation time 22527048 ps
CPU time 0.66 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 194132 kb
Host smart-51991206-6c48-459f-a16f-c02f442a479b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031229871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4031229871
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1144518825
Short name T621
Test name
Test status
Simulation time 115159588 ps
CPU time 1.47 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 197788 kb
Host smart-d601f022-e9df-4da2-ad9a-08ce001c16ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144518825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1144518825
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4107007569
Short name T886
Test name
Test status
Simulation time 212960905 ps
CPU time 3.14 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:45:19 PM PST 24
Peak memory 195576 kb
Host smart-62c3531c-f4cb-44c4-9153-1b58ba299a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107007569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4107007569
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1652351048
Short name T238
Test name
Test status
Simulation time 116491760 ps
CPU time 1.3 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:25 PM PST 24
Peak memory 197832 kb
Host smart-457e2435-2045-4303-b254-e96f822454de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652351048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1652351048
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3453740688
Short name T500
Test name
Test status
Simulation time 26448448 ps
CPU time 1.02 seconds
Started Feb 04 02:44:51 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 196388 kb
Host smart-923a079b-82bb-4219-8e15-529f5aaf07c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453740688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3453740688
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1830470337
Short name T592
Test name
Test status
Simulation time 428458417 ps
CPU time 1.98 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:25 PM PST 24
Peak memory 197708 kb
Host smart-5c9bfe03-15dc-490f-8cf4-9c9a9f969ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830470337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1830470337
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1571666600
Short name T490
Test name
Test status
Simulation time 51369012 ps
CPU time 0.72 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 195040 kb
Host smart-d1c91b37-a721-4c47-abc5-f6b56c078c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571666600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1571666600
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2742607325
Short name T515
Test name
Test status
Simulation time 163606936 ps
CPU time 1.13 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195384 kb
Host smart-19bd47a6-9b71-4d22-b23f-fc64f9e67c46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742607325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2742607325
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.138480792
Short name T102
Test name
Test status
Simulation time 4252578162 ps
CPU time 26.16 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:43 PM PST 24
Peak memory 197872 kb
Host smart-f88af5fc-0430-4755-8630-214c7ea08591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138480792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.138480792
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1198170087
Short name T821
Test name
Test status
Simulation time 315724317325 ps
CPU time 1469.98 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 03:09:47 PM PST 24
Peak memory 198020 kb
Host smart-c26d7eed-69e9-45bd-a562-3d16fc2a7b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1198170087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1198170087
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1598450155
Short name T270
Test name
Test status
Simulation time 42230475 ps
CPU time 0.57 seconds
Started Feb 04 02:44:52 PM PST 24
Finished Feb 04 02:45:15 PM PST 24
Peak memory 193668 kb
Host smart-6b5c3a7f-3072-4eee-9608-c2b569d2c82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598450155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1598450155
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2120174831
Short name T846
Test name
Test status
Simulation time 48146026 ps
CPU time 0.81 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:24 PM PST 24
Peak memory 196944 kb
Host smart-8b6a8a8e-1731-4b91-accf-533fd515ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120174831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2120174831
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.518787505
Short name T356
Test name
Test status
Simulation time 17898995456 ps
CPU time 26.65 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:43 PM PST 24
Peak memory 196796 kb
Host smart-111e6ef5-39e9-495a-ad42-0df871860ad5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518787505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.518787505
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3266910062
Short name T822
Test name
Test status
Simulation time 187333505 ps
CPU time 1.01 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 196124 kb
Host smart-204cfae6-4b65-4146-800e-6b040ace5bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266910062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3266910062
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2047543296
Short name T250
Test name
Test status
Simulation time 29373780 ps
CPU time 0.88 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 196336 kb
Host smart-c24cb9e9-a35c-4b46-8634-076e7d26ef2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047543296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2047543296
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.72100795
Short name T107
Test name
Test status
Simulation time 168976974 ps
CPU time 3.47 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:20 PM PST 24
Peak memory 197856 kb
Host smart-92bfbadd-a20d-4792-9fa1-c148405ad732
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72100795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.gpio_intr_with_filter_rand_intr_event.72100795
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.230044816
Short name T245
Test name
Test status
Simulation time 79413389 ps
CPU time 1.86 seconds
Started Feb 04 02:44:48 PM PST 24
Finished Feb 04 02:45:08 PM PST 24
Peak memory 195796 kb
Host smart-f0324844-87ce-4988-aebf-2c5d76e41fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230044816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
230044816
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3552271706
Short name T795
Test name
Test status
Simulation time 37502869 ps
CPU time 0.84 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 196912 kb
Host smart-362e5b35-ca2e-4584-8748-e6a1610ae0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552271706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3552271706
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2254397215
Short name T826
Test name
Test status
Simulation time 618038242 ps
CPU time 0.9 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195716 kb
Host smart-c7a4d0e9-9a48-4c4d-812e-b14dc146a149
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254397215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2254397215
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3054747165
Short name T527
Test name
Test status
Simulation time 373713500 ps
CPU time 4.65 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:28 PM PST 24
Peak memory 197672 kb
Host smart-2ab652a9-0c39-4700-8b3b-debd20e093ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054747165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3054747165
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2780427732
Short name T696
Test name
Test status
Simulation time 58474785 ps
CPU time 1.14 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195560 kb
Host smart-697ab53f-bab0-4dbc-a4eb-37d5594fe55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780427732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2780427732
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.874719980
Short name T253
Test name
Test status
Simulation time 178440620 ps
CPU time 1.32 seconds
Started Feb 04 02:45:00 PM PST 24
Finished Feb 04 02:45:25 PM PST 24
Peak memory 196500 kb
Host smart-0158b7d6-3104-4923-b339-73c79df33426
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874719980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.874719980
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2990530273
Short name T296
Test name
Test status
Simulation time 3708973107 ps
CPU time 62.48 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:46:18 PM PST 24
Peak memory 197908 kb
Host smart-00ada059-7108-412f-a75e-c9d0188660cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990530273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2990530273
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2871281172
Short name T495
Test name
Test status
Simulation time 59063740241 ps
CPU time 466.16 seconds
Started Feb 04 02:44:53 PM PST 24
Finished Feb 04 02:53:01 PM PST 24
Peak memory 206268 kb
Host smart-7c59e959-18c6-4597-ab42-e6dbe3398dd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2871281172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2871281172
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.518285307
Short name T530
Test name
Test status
Simulation time 14103578 ps
CPU time 0.56 seconds
Started Feb 04 02:44:30 PM PST 24
Finished Feb 04 02:44:33 PM PST 24
Peak memory 193704 kb
Host smart-20b2df96-1451-4bbb-9601-ac064104e3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518285307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.518285307
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.176402263
Short name T462
Test name
Test status
Simulation time 26110363 ps
CPU time 0.6 seconds
Started Feb 04 02:44:20 PM PST 24
Finished Feb 04 02:44:25 PM PST 24
Peak memory 193636 kb
Host smart-aba3a1f0-04d4-4c99-84af-7f1f8d57900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176402263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.176402263
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2375912892
Short name T526
Test name
Test status
Simulation time 5858553123 ps
CPU time 25.99 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:56 PM PST 24
Peak memory 195696 kb
Host smart-9f47931a-0f7f-41f5-b31d-d49aba29bf66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375912892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2375912892
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.189322383
Short name T571
Test name
Test status
Simulation time 74100001 ps
CPU time 0.78 seconds
Started Feb 04 02:44:42 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 195844 kb
Host smart-dd16e0cb-8089-4014-bbc4-60802d70b18a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189322383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.189322383
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1991854193
Short name T248
Test name
Test status
Simulation time 206788310 ps
CPU time 1.45 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 02:44:32 PM PST 24
Peak memory 196848 kb
Host smart-de2b385f-b37f-44ed-9387-e6ec1b7dab69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991854193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1991854193
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.756462157
Short name T65
Test name
Test status
Simulation time 68205282 ps
CPU time 2.63 seconds
Started Feb 04 02:44:39 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 197740 kb
Host smart-3efe638b-29a0-47d2-9ae1-e82274ce6d6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756462157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.756462157
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2172241187
Short name T350
Test name
Test status
Simulation time 58406927 ps
CPU time 1.08 seconds
Started Feb 04 02:44:49 PM PST 24
Finished Feb 04 02:45:09 PM PST 24
Peak memory 196032 kb
Host smart-98e0f7ae-7749-485d-8ffa-e3cb7fef359c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172241187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2172241187
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2742627824
Short name T333
Test name
Test status
Simulation time 193313563 ps
CPU time 1.09 seconds
Started Feb 04 02:44:53 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 195836 kb
Host smart-5bbb97b7-f4a1-4c61-b020-22826a39b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742627824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2742627824
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.830073134
Short name T781
Test name
Test status
Simulation time 78456618 ps
CPU time 0.91 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 196360 kb
Host smart-bd638054-fc58-4c02-8b3f-9234f862e820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830073134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.830073134
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2775936838
Short name T757
Test name
Test status
Simulation time 290547708 ps
CPU time 3.85 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:07 PM PST 24
Peak memory 197788 kb
Host smart-153cb4c0-f2f7-497b-b2c0-540e1e141d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775936838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2775936838
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1710013049
Short name T837
Test name
Test status
Simulation time 70057867 ps
CPU time 1.18 seconds
Started Feb 04 02:44:56 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195320 kb
Host smart-775f89d4-af16-4da2-9239-fd9fe4cce0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710013049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1710013049
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3225547009
Short name T409
Test name
Test status
Simulation time 22602103 ps
CPU time 0.72 seconds
Started Feb 04 02:44:53 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 193940 kb
Host smart-9aaf6530-85af-4fa3-bf11-06da95a4c20b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225547009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3225547009
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3160879141
Short name T863
Test name
Test status
Simulation time 2277035161 ps
CPU time 18.75 seconds
Started Feb 04 02:44:29 PM PST 24
Finished Feb 04 02:44:50 PM PST 24
Peak memory 197848 kb
Host smart-4d9b3bfb-0181-4493-9389-8f164ed4c4b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160879141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3160879141
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3025190954
Short name T850
Test name
Test status
Simulation time 77545326115 ps
CPU time 948.89 seconds
Started Feb 04 02:44:29 PM PST 24
Finished Feb 04 03:00:21 PM PST 24
Peak memory 197980 kb
Host smart-99f6ad53-97a2-43af-ad72-be69199c054e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3025190954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3025190954
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1866204964
Short name T303
Test name
Test status
Simulation time 13605538 ps
CPU time 0.57 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 193920 kb
Host smart-e27aa1cf-7439-461b-8f12-e300dec73d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866204964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1866204964
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1796561612
Short name T362
Test name
Test status
Simulation time 291300336 ps
CPU time 0.64 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:47 PM PST 24
Peak memory 194636 kb
Host smart-78d9198b-ad37-4118-a2dc-6ce843268e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796561612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1796561612
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.240357937
Short name T46
Test name
Test status
Simulation time 815831754 ps
CPU time 27.09 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:45:15 PM PST 24
Peak memory 197800 kb
Host smart-d705b886-8ea3-46d0-ba3d-b38fd1548baf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240357937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.240357937
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3007073820
Short name T667
Test name
Test status
Simulation time 114299759 ps
CPU time 0.7 seconds
Started Feb 04 02:44:38 PM PST 24
Finished Feb 04 02:44:43 PM PST 24
Peak memory 194592 kb
Host smart-789cda87-b5ce-4ec8-9e05-2e7f7036ef44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007073820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3007073820
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3848950181
Short name T866
Test name
Test status
Simulation time 55406819 ps
CPU time 1.41 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 196740 kb
Host smart-bd6bb07e-6a12-4441-9556-3cc6c96a28ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848950181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3848950181
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.625459078
Short name T332
Test name
Test status
Simulation time 164994237 ps
CPU time 3.34 seconds
Started Feb 04 02:44:38 PM PST 24
Finished Feb 04 02:44:46 PM PST 24
Peak memory 197996 kb
Host smart-d8061cd5-56eb-4645-ab05-b685a8a86f80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625459078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.625459078
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1044308078
Short name T256
Test name
Test status
Simulation time 308178225 ps
CPU time 1.76 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 196452 kb
Host smart-595d97d0-62bf-4ab7-ba07-dbbe82e0bd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044308078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1044308078
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3275909559
Short name T53
Test name
Test status
Simulation time 62143399 ps
CPU time 0.65 seconds
Started Feb 04 02:44:36 PM PST 24
Finished Feb 04 02:44:39 PM PST 24
Peak memory 194844 kb
Host smart-c1572522-a845-49b9-a3b7-dd301f00fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275909559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3275909559
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3245730187
Short name T70
Test name
Test status
Simulation time 37867909 ps
CPU time 1.02 seconds
Started Feb 04 02:44:49 PM PST 24
Finished Feb 04 02:45:10 PM PST 24
Peak memory 196512 kb
Host smart-76edb7bc-2268-4d44-b739-8657b55d0b96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245730187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3245730187
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.341349186
Short name T634
Test name
Test status
Simulation time 301602717 ps
CPU time 5.12 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:52 PM PST 24
Peak memory 197732 kb
Host smart-df8872de-a9b9-4d56-9d8e-e2aa0e1736a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341349186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.341349186
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.478209075
Short name T848
Test name
Test status
Simulation time 265220670 ps
CPU time 1.28 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 196196 kb
Host smart-a0774821-5da2-4480-bd50-351d1dd6482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478209075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.478209075
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1890677526
Short name T213
Test name
Test status
Simulation time 39479168 ps
CPU time 0.75 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 195712 kb
Host smart-91363cc0-0d2d-45f5-986e-8be2691adefb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890677526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1890677526
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2427489676
Short name T293
Test name
Test status
Simulation time 11215008864 ps
CPU time 125.56 seconds
Started Feb 04 02:44:29 PM PST 24
Finished Feb 04 02:46:37 PM PST 24
Peak memory 197920 kb
Host smart-b5e89318-cdda-4aa4-b891-93f12cc88eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427489676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2427489676
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2377547094
Short name T753
Test name
Test status
Simulation time 62432879260 ps
CPU time 735.96 seconds
Started Feb 04 02:44:57 PM PST 24
Finished Feb 04 02:57:34 PM PST 24
Peak memory 198028 kb
Host smart-6f63634b-4ae9-4fdb-8945-5e66c470e9a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2377547094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2377547094
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3057505518
Short name T534
Test name
Test status
Simulation time 24542176 ps
CPU time 0.59 seconds
Started Feb 04 02:44:32 PM PST 24
Finished Feb 04 02:44:34 PM PST 24
Peak memory 193756 kb
Host smart-d55a2f37-abe0-44aa-9f53-6968431d5024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057505518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3057505518
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2193907818
Short name T282
Test name
Test status
Simulation time 27372074 ps
CPU time 0.96 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:17 PM PST 24
Peak memory 195580 kb
Host smart-ca2a2dfd-fb11-4daf-a67c-dcbfcb856ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193907818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2193907818
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3375428692
Short name T463
Test name
Test status
Simulation time 605833732 ps
CPU time 16.04 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:45:02 PM PST 24
Peak memory 196716 kb
Host smart-e6e42e4c-08af-4093-83b8-691f5526c3b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375428692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3375428692
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2385029459
Short name T535
Test name
Test status
Simulation time 58992470 ps
CPU time 0.91 seconds
Started Feb 04 02:44:27 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 196540 kb
Host smart-fec116f9-d9a2-42da-b78b-7f8227678255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385029459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2385029459
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.197093357
Short name T453
Test name
Test status
Simulation time 40643425 ps
CPU time 0.88 seconds
Started Feb 04 02:44:31 PM PST 24
Finished Feb 04 02:44:34 PM PST 24
Peak memory 196132 kb
Host smart-2d37343a-2585-43f3-8353-b6d2633ab182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197093357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.197093357
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1030266723
Short name T520
Test name
Test status
Simulation time 28484049 ps
CPU time 1.15 seconds
Started Feb 04 02:44:34 PM PST 24
Finished Feb 04 02:44:37 PM PST 24
Peak memory 197008 kb
Host smart-4cd20721-13f2-4722-8d3f-21e387365a7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030266723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1030266723
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1666403487
Short name T285
Test name
Test status
Simulation time 591163098 ps
CPU time 1.36 seconds
Started Feb 04 02:44:41 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 196596 kb
Host smart-6ab8738a-8b78-4327-9eba-c6bd5f5c2d94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666403487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1666403487
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3051515887
Short name T381
Test name
Test status
Simulation time 40330799 ps
CPU time 0.83 seconds
Started Feb 04 02:44:28 PM PST 24
Finished Feb 04 02:44:31 PM PST 24
Peak memory 195348 kb
Host smart-1aa4efe3-c99e-4192-8f7f-63f28fb39ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051515887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3051515887
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1953105016
Short name T708
Test name
Test status
Simulation time 19796662 ps
CPU time 0.67 seconds
Started Feb 04 02:44:39 PM PST 24
Finished Feb 04 02:44:47 PM PST 24
Peak memory 194088 kb
Host smart-50a32e34-223a-4886-858e-821cc024cd95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953105016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1953105016
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3488523207
Short name T521
Test name
Test status
Simulation time 193279622 ps
CPU time 1.39 seconds
Started Feb 04 02:44:32 PM PST 24
Finished Feb 04 02:44:35 PM PST 24
Peak memory 197740 kb
Host smart-0311800b-eb68-419e-a529-680a8c0809fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488523207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3488523207
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4200282584
Short name T269
Test name
Test status
Simulation time 201441003 ps
CPU time 0.92 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 196196 kb
Host smart-e844c084-0e49-4bfb-aea0-6444cd4daf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200282584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4200282584
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.838905910
Short name T568
Test name
Test status
Simulation time 99976570 ps
CPU time 1.21 seconds
Started Feb 04 02:44:31 PM PST 24
Finished Feb 04 02:44:34 PM PST 24
Peak memory 195584 kb
Host smart-45943981-0027-4b57-bc6d-d28e5c227ed0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838905910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.838905910
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.924317694
Short name T445
Test name
Test status
Simulation time 2692743494 ps
CPU time 30.07 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:33 PM PST 24
Peak memory 197940 kb
Host smart-5f0595d9-1d63-4865-a39c-49790b45fefd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924317694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.924317694
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1506524853
Short name T682
Test name
Test status
Simulation time 48480565857 ps
CPU time 718.4 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:56:46 PM PST 24
Peak memory 206260 kb
Host smart-6b9f26ed-7777-41b1-83fc-1bb04ba06a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1506524853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1506524853
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3144442948
Short name T672
Test name
Test status
Simulation time 37899319 ps
CPU time 0.55 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:03 PM PST 24
Peak memory 193296 kb
Host smart-f32c1c1d-b7e1-4842-95d3-e73f5dfa6202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144442948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3144442948
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2027288887
Short name T299
Test name
Test status
Simulation time 47130961 ps
CPU time 0.66 seconds
Started Feb 04 02:44:42 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 193980 kb
Host smart-8300d36c-d317-4af6-accd-8320222a0214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027288887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2027288887
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4045214385
Short name T247
Test name
Test status
Simulation time 322902428 ps
CPU time 3.06 seconds
Started Feb 04 02:44:51 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195224 kb
Host smart-d3308035-add0-49ae-8d96-5b0154916e21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045214385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4045214385
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1978267408
Short name T570
Test name
Test status
Simulation time 184591968 ps
CPU time 0.84 seconds
Started Feb 04 02:44:58 PM PST 24
Finished Feb 04 02:45:22 PM PST 24
Peak memory 196752 kb
Host smart-cfd6cf6e-5ed3-475f-9ba6-b4e78c0d272c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978267408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1978267408
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2007942957
Short name T586
Test name
Test status
Simulation time 93737983 ps
CPU time 1.35 seconds
Started Feb 04 02:44:53 PM PST 24
Finished Feb 04 02:45:16 PM PST 24
Peak memory 196468 kb
Host smart-37c04d54-073e-449f-bdd9-459833689dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007942957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2007942957
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1055989264
Short name T436
Test name
Test status
Simulation time 577061465 ps
CPU time 1.44 seconds
Started Feb 04 02:44:49 PM PST 24
Finished Feb 04 02:45:10 PM PST 24
Peak memory 196636 kb
Host smart-368f1472-d90f-45c6-9ec8-7fd7849e71ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055989264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1055989264
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.540323035
Short name T619
Test name
Test status
Simulation time 532516837 ps
CPU time 2.75 seconds
Started Feb 04 02:44:48 PM PST 24
Finished Feb 04 02:45:09 PM PST 24
Peak memory 196940 kb
Host smart-66ab8b9c-2964-442d-a9f5-c238edff8ac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540323035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
540323035
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2953395035
Short name T567
Test name
Test status
Simulation time 29863701 ps
CPU time 0.95 seconds
Started Feb 04 02:44:55 PM PST 24
Finished Feb 04 02:45:18 PM PST 24
Peak memory 195724 kb
Host smart-91012b38-b3b2-4f0a-b7b0-eb4219ab9827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953395035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2953395035
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.586861850
Short name T484
Test name
Test status
Simulation time 63633617 ps
CPU time 1.04 seconds
Started Feb 04 02:44:38 PM PST 24
Finished Feb 04 02:44:46 PM PST 24
Peak memory 195864 kb
Host smart-9200f3ce-7d82-415d-b2ef-a5bf93c1ffdd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586861850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.586861850
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4242797048
Short name T718
Test name
Test status
Simulation time 225039314 ps
CPU time 1.2 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:03 PM PST 24
Peak memory 197732 kb
Host smart-b220c373-35a3-4d83-ad34-04466ffae608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242797048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4242797048
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4086227653
Short name T615
Test name
Test status
Simulation time 56377998 ps
CPU time 1.24 seconds
Started Feb 04 02:44:40 PM PST 24
Finished Feb 04 02:44:48 PM PST 24
Peak memory 195328 kb
Host smart-15926671-9d82-4493-b379-c42e78400e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086227653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4086227653
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2597622477
Short name T875
Test name
Test status
Simulation time 218533064 ps
CPU time 0.78 seconds
Started Feb 04 02:44:47 PM PST 24
Finished Feb 04 02:45:02 PM PST 24
Peak memory 194948 kb
Host smart-7ff19450-6259-4e2a-8f01-2c396dafca8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597622477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2597622477
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2485395589
Short name T556
Test name
Test status
Simulation time 27149964253 ps
CPU time 79.67 seconds
Started Feb 04 02:44:54 PM PST 24
Finished Feb 04 02:46:35 PM PST 24
Peak memory 197940 kb
Host smart-08b45e60-055f-4d39-b7d9-d3cf131ba95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485395589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2485395589
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1009142289
Short name T624
Test name
Test status
Simulation time 331515617743 ps
CPU time 2093.91 seconds
Started Feb 04 02:44:51 PM PST 24
Finished Feb 04 03:20:09 PM PST 24
Peak memory 198100 kb
Host smart-34193012-b0a5-44d9-b58e-08f9d75f1f8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1009142289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1009142289
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3959066663
Short name T776
Test name
Test status
Simulation time 34620322 ps
CPU time 0.55 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:27 PM PST 24
Peak memory 193700 kb
Host smart-5038f262-21ca-402d-8cc2-3fa97e6b6fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959066663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3959066663
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1832309088
Short name T841
Test name
Test status
Simulation time 34465871 ps
CPU time 0.79 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 195740 kb
Host smart-924aea95-43d4-4df1-b4e4-89c55e760b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832309088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1832309088
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3849281445
Short name T284
Test name
Test status
Simulation time 3640786114 ps
CPU time 16.73 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:53 PM PST 24
Peak memory 196444 kb
Host smart-a786109c-c1ce-4b2b-9896-cabd78138ee6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849281445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3849281445
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2250728536
Short name T714
Test name
Test status
Simulation time 554401774 ps
CPU time 0.9 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 197348 kb
Host smart-65cd8e5b-6db7-4a4e-a6fa-45f51487eca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250728536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2250728536
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4140154186
Short name T239
Test name
Test status
Simulation time 679594915 ps
CPU time 0.93 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:23 PM PST 24
Peak memory 196572 kb
Host smart-a7bcb9e2-3a0a-4b3d-b069-dfd73a24eece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140154186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4140154186
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.122909497
Short name T702
Test name
Test status
Simulation time 421313626 ps
CPU time 1.24 seconds
Started Feb 04 02:42:20 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 196028 kb
Host smart-0f24c6cc-3117-4f56-8566-730e1720b447
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122909497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.122909497
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3414673864
Short name T523
Test name
Test status
Simulation time 153822763 ps
CPU time 2.86 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:25 PM PST 24
Peak memory 196996 kb
Host smart-65e25e72-3330-4db9-af03-c56f18b8ad14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414673864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3414673864
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1278667044
Short name T432
Test name
Test status
Simulation time 54844602 ps
CPU time 0.72 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:37 PM PST 24
Peak memory 195076 kb
Host smart-2a2aa7f3-d12b-45e5-bc5b-db15a0f9de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278667044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1278667044
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.501418725
Short name T459
Test name
Test status
Simulation time 51639944 ps
CPU time 1.17 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 196716 kb
Host smart-fd5b16d9-90ff-4799-ab54-b21b7d438ffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501418725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.501418725
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.949853897
Short name T635
Test name
Test status
Simulation time 58107697 ps
CPU time 2.7 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:29 PM PST 24
Peak memory 197668 kb
Host smart-c45d45d5-8ae1-41b6-a846-c83c75b25cfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949853897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.949853897
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1530632156
Short name T587
Test name
Test status
Simulation time 154132135 ps
CPU time 1.03 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 195512 kb
Host smart-fa552db8-1743-456c-803d-5e045f3f6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530632156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1530632156
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2351097616
Short name T640
Test name
Test status
Simulation time 236945326 ps
CPU time 1.05 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:28 PM PST 24
Peak memory 195284 kb
Host smart-4b5655d7-4d5f-41b9-b5e9-882356deaf07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351097616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2351097616
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1182890132
Short name T564
Test name
Test status
Simulation time 71361607879 ps
CPU time 197.04 seconds
Started Feb 04 02:42:23 PM PST 24
Finished Feb 04 02:45:45 PM PST 24
Peak memory 197924 kb
Host smart-5fb88d57-b0d7-4d03-903d-965a38caaf96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182890132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1182890132
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.4205031112
Short name T301
Test name
Test status
Simulation time 63402331152 ps
CPU time 129.77 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:44:47 PM PST 24
Peak memory 206072 kb
Host smart-4466caf1-3bdd-4062-ba03-5a3918601972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4205031112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.4205031112
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.491360119
Short name T550
Test name
Test status
Simulation time 16707448 ps
CPU time 0.63 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 193904 kb
Host smart-e7964cdc-b8dd-490d-a41d-4b669bcd6b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491360119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.491360119
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.642645446
Short name T588
Test name
Test status
Simulation time 53161633 ps
CPU time 0.94 seconds
Started Feb 04 02:42:30 PM PST 24
Finished Feb 04 02:42:34 PM PST 24
Peak memory 196492 kb
Host smart-34704455-66b1-48da-9c98-500749de7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642645446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.642645446
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.766835533
Short name T230
Test name
Test status
Simulation time 591137133 ps
CPU time 15.64 seconds
Started Feb 04 02:42:27 PM PST 24
Finished Feb 04 02:42:45 PM PST 24
Peak memory 195260 kb
Host smart-d2473f81-336b-4c95-b1a6-b08bad63670c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766835533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.766835533
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2857916184
Short name T67
Test name
Test status
Simulation time 182151189 ps
CPU time 0.81 seconds
Started Feb 04 02:42:30 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 196416 kb
Host smart-6f4aceec-ca36-4fa9-a8e8-e1aa5e30e497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857916184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2857916184
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2932610429
Short name T761
Test name
Test status
Simulation time 54506600 ps
CPU time 0.7 seconds
Started Feb 04 02:42:30 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 194080 kb
Host smart-0c749114-ec8c-455c-b1f1-aa8f86e78925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932610429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2932610429
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2439567906
Short name T673
Test name
Test status
Simulation time 188927579 ps
CPU time 2.14 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 197844 kb
Host smart-5194495b-8cba-4dc4-aba6-bcbd48a8fe0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439567906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2439567906
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1501214895
Short name T366
Test name
Test status
Simulation time 44059310 ps
CPU time 1.5 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:42:46 PM PST 24
Peak memory 195652 kb
Host smart-2a0686e5-fb99-4453-b612-beae9b9ffdb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501214895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1501214895
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3214346226
Short name T218
Test name
Test status
Simulation time 216736632 ps
CPU time 1.19 seconds
Started Feb 04 02:42:19 PM PST 24
Finished Feb 04 02:42:24 PM PST 24
Peak memory 196524 kb
Host smart-87e9ad51-f1ca-4800-96d5-79c8b87db7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214346226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3214346226
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.338123757
Short name T843
Test name
Test status
Simulation time 31549052 ps
CPU time 1.16 seconds
Started Feb 04 02:42:21 PM PST 24
Finished Feb 04 02:42:26 PM PST 24
Peak memory 195768 kb
Host smart-7a0d7d74-63d8-4900-bfb5-c488eeb1d78a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338123757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.338123757
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.757041793
Short name T273
Test name
Test status
Simulation time 140847033 ps
CPU time 1.98 seconds
Started Feb 04 02:42:32 PM PST 24
Finished Feb 04 02:42:37 PM PST 24
Peak memory 197776 kb
Host smart-1fb0361a-15a3-4eb0-8218-bd43a9a42ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757041793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.757041793
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3092839611
Short name T885
Test name
Test status
Simulation time 42800673 ps
CPU time 1.19 seconds
Started Feb 04 02:42:35 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 196132 kb
Host smart-d78bc4bf-8541-47ed-a619-1dc6b1c08c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092839611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3092839611
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2659098010
Short name T849
Test name
Test status
Simulation time 268724407 ps
CPU time 1.29 seconds
Started Feb 04 02:42:22 PM PST 24
Finished Feb 04 02:42:27 PM PST 24
Peak memory 197728 kb
Host smart-f4c94b70-462c-4f3f-bbe6-82cece37a661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659098010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2659098010
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.906520502
Short name T674
Test name
Test status
Simulation time 2913034940 ps
CPU time 30.88 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:43:01 PM PST 24
Peak memory 197952 kb
Host smart-15508aed-2cdf-48ff-80c7-448c9f0fea06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906520502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.906520502
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3916614739
Short name T397
Test name
Test status
Simulation time 203918883776 ps
CPU time 679.22 seconds
Started Feb 04 02:42:30 PM PST 24
Finished Feb 04 02:53:52 PM PST 24
Peak memory 198044 kb
Host smart-5247b3bf-a133-4126-bb1f-c8093e9d6f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3916614739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3916614739
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3839678811
Short name T762
Test name
Test status
Simulation time 22441574 ps
CPU time 0.57 seconds
Started Feb 04 02:42:29 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 193684 kb
Host smart-b7b91847-f69f-4ad7-9b55-c6e8029b19e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839678811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3839678811
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1212275857
Short name T372
Test name
Test status
Simulation time 34412997 ps
CPU time 0.63 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:30 PM PST 24
Peak memory 193784 kb
Host smart-85205793-dfff-4493-9af0-3dbf894f00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212275857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1212275857
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2953627666
Short name T798
Test name
Test status
Simulation time 332218307 ps
CPU time 17.94 seconds
Started Feb 04 02:42:33 PM PST 24
Finished Feb 04 02:42:54 PM PST 24
Peak memory 196976 kb
Host smart-170e9703-2a00-437c-91a9-d57dda7fa3f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953627666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2953627666
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3366773103
Short name T754
Test name
Test status
Simulation time 53083794 ps
CPU time 0.86 seconds
Started Feb 04 02:42:29 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 195848 kb
Host smart-30c2d1fa-0e88-4c4b-b871-a46ed3343962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366773103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3366773103
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.509599022
Short name T629
Test name
Test status
Simulation time 68856575 ps
CPU time 1.11 seconds
Started Feb 04 02:42:31 PM PST 24
Finished Feb 04 02:42:35 PM PST 24
Peak memory 195884 kb
Host smart-736fd9c7-0073-463e-94dd-901443a1e4ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509599022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.509599022
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.900320965
Short name T857
Test name
Test status
Simulation time 45348515 ps
CPU time 1.06 seconds
Started Feb 04 02:42:34 PM PST 24
Finished Feb 04 02:42:37 PM PST 24
Peak memory 195928 kb
Host smart-13cd763c-188b-4a84-846d-722a36a8de27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900320965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.900320965
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2400433963
Short name T713
Test name
Test status
Simulation time 61329227 ps
CPU time 1.84 seconds
Started Feb 04 02:42:34 PM PST 24
Finished Feb 04 02:42:38 PM PST 24
Peak memory 196696 kb
Host smart-219f724d-8db3-47ea-bbf5-794e7ae4680b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400433963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2400433963
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1772357335
Short name T805
Test name
Test status
Simulation time 44416190 ps
CPU time 0.77 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:42:45 PM PST 24
Peak memory 195164 kb
Host smart-4a32ba5b-7b50-4bbf-a741-519d857be2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772357335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1772357335
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3077814754
Short name T385
Test name
Test status
Simulation time 21120581 ps
CPU time 0.68 seconds
Started Feb 04 02:42:27 PM PST 24
Finished Feb 04 02:42:30 PM PST 24
Peak memory 194252 kb
Host smart-74e0eeaf-9379-4720-b8bf-b22da86ad000
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077814754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3077814754
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2617989506
Short name T513
Test name
Test status
Simulation time 238086122 ps
CPU time 2.17 seconds
Started Feb 04 02:42:26 PM PST 24
Finished Feb 04 02:42:31 PM PST 24
Peak memory 197700 kb
Host smart-067bc53a-44fb-4ebf-ae68-5418ac4a2d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617989506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2617989506
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4170975093
Short name T341
Test name
Test status
Simulation time 45058167 ps
CPU time 0.86 seconds
Started Feb 04 02:42:27 PM PST 24
Finished Feb 04 02:42:30 PM PST 24
Peak memory 195200 kb
Host smart-2a368f3e-65ac-47e4-a889-91e5488d73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170975093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4170975093
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.4220426012
Short name T222
Test name
Test status
Simulation time 91721002 ps
CPU time 1.47 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:42:46 PM PST 24
Peak memory 196456 kb
Host smart-92cee848-43f6-4a1d-bfa0-970640dc20ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220426012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.4220426012
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.803150397
Short name T677
Test name
Test status
Simulation time 52284307263 ps
CPU time 133.58 seconds
Started Feb 04 02:42:33 PM PST 24
Finished Feb 04 02:44:49 PM PST 24
Peak memory 197940 kb
Host smart-cdce9f80-f3ad-4df5-9f44-cc469294ffcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803150397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.803150397
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.35590667
Short name T325
Test name
Test status
Simulation time 229233952678 ps
CPU time 1455.64 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 03:06:46 PM PST 24
Peak memory 198004 kb
Host smart-1934d139-40ee-429d-82be-0ccddf61b987
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=35590667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.35590667
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.471005408
Short name T433
Test name
Test status
Simulation time 92646689 ps
CPU time 0.55 seconds
Started Feb 04 02:42:32 PM PST 24
Finished Feb 04 02:42:35 PM PST 24
Peak memory 193740 kb
Host smart-b8bc2ac4-9834-4fcf-af85-d780fc8de668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471005408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.471005408
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1748151053
Short name T811
Test name
Test status
Simulation time 158552248 ps
CPU time 0.88 seconds
Started Feb 04 02:42:29 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 196360 kb
Host smart-35c883b6-9f02-4b17-b0e5-b5f980f7a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748151053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1748151053
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2931017303
Short name T731
Test name
Test status
Simulation time 823382606 ps
CPU time 25.58 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:43:10 PM PST 24
Peak memory 196824 kb
Host smart-de80d422-dec9-488d-8d41-27730cba8532
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931017303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2931017303
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3140990587
Short name T542
Test name
Test status
Simulation time 193527151 ps
CPU time 1.18 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 196232 kb
Host smart-5bc1f6bd-05bb-47a9-a72f-ad5e9970a672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140990587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3140990587
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1667368965
Short name T675
Test name
Test status
Simulation time 138203010 ps
CPU time 0.73 seconds
Started Feb 04 02:42:33 PM PST 24
Finished Feb 04 02:42:36 PM PST 24
Peak memory 195380 kb
Host smart-0fc9adba-0cc9-4670-a2af-4d6dc1d60b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667368965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1667368965
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1435751075
Short name T642
Test name
Test status
Simulation time 71730844 ps
CPU time 2.65 seconds
Started Feb 04 02:42:27 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 197860 kb
Host smart-aabb856e-4ee4-4e88-b860-4b569ec60466
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435751075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1435751075
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3495968178
Short name T884
Test name
Test status
Simulation time 893928255 ps
CPU time 2.81 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:33 PM PST 24
Peak memory 195616 kb
Host smart-97bc193e-dfa3-4168-9707-5bc02f128b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495968178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3495968178
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3132066658
Short name T402
Test name
Test status
Simulation time 96851102 ps
CPU time 1.09 seconds
Started Feb 04 02:42:31 PM PST 24
Finished Feb 04 02:42:35 PM PST 24
Peak memory 196512 kb
Host smart-7ba7f196-7374-4f42-9593-0cd836b785ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132066658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3132066658
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.604948809
Short name T609
Test name
Test status
Simulation time 198788572 ps
CPU time 1.09 seconds
Started Feb 04 02:42:27 PM PST 24
Finished Feb 04 02:42:31 PM PST 24
Peak memory 195896 kb
Host smart-cdbfdebf-2e13-40ad-9b2e-3562da5ce145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604948809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.604948809
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1287873162
Short name T314
Test name
Test status
Simulation time 531873599 ps
CPU time 6.16 seconds
Started Feb 04 02:42:34 PM PST 24
Finished Feb 04 02:42:42 PM PST 24
Peak memory 197188 kb
Host smart-a4c0d8ea-03f7-407d-a584-da0e33150eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287873162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1287873162
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1448277684
Short name T420
Test name
Test status
Simulation time 510791870 ps
CPU time 0.89 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:31 PM PST 24
Peak memory 195052 kb
Host smart-337b8d8f-efb7-47cf-ae30-f0dfd90940eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448277684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1448277684
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.70983156
Short name T240
Test name
Test status
Simulation time 118635152 ps
CPU time 0.86 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:42:45 PM PST 24
Peak memory 195544 kb
Host smart-d68d4ecf-ea97-4bc7-86c4-9bef58ffd888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70983156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.70983156
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1362830943
Short name T769
Test name
Test status
Simulation time 32877536749 ps
CPU time 218.98 seconds
Started Feb 04 02:42:33 PM PST 24
Finished Feb 04 02:46:15 PM PST 24
Peak memory 197984 kb
Host smart-7884ac1b-346d-4f39-a9ac-99d7978f7796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362830943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1362830943
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3556215594
Short name T403
Test name
Test status
Simulation time 268674751670 ps
CPU time 1216.96 seconds
Started Feb 04 02:42:29 PM PST 24
Finished Feb 04 03:02:49 PM PST 24
Peak memory 198120 kb
Host smart-be3e65b6-e2cf-4b65-a049-88b43540e8d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3556215594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3556215594
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3108102379
Short name T871
Test name
Test status
Simulation time 15846813 ps
CPU time 0.58 seconds
Started Feb 04 02:42:49 PM PST 24
Finished Feb 04 02:42:52 PM PST 24
Peak memory 194428 kb
Host smart-47e50707-7212-45f4-9062-bf814e783381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108102379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3108102379
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3563904026
Short name T585
Test name
Test status
Simulation time 99549446 ps
CPU time 0.67 seconds
Started Feb 04 02:42:55 PM PST 24
Finished Feb 04 02:43:00 PM PST 24
Peak memory 193916 kb
Host smart-59d4e363-4633-41f1-ba4a-39c8ec779869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563904026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3563904026
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3749852444
Short name T281
Test name
Test status
Simulation time 490390781 ps
CPU time 6.34 seconds
Started Feb 04 02:42:47 PM PST 24
Finished Feb 04 02:42:55 PM PST 24
Peak memory 195348 kb
Host smart-af3e1c31-648e-4119-968c-bf658f2c498f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749852444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3749852444
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2696961630
Short name T878
Test name
Test status
Simulation time 88706538 ps
CPU time 1.15 seconds
Started Feb 04 02:42:48 PM PST 24
Finished Feb 04 02:42:51 PM PST 24
Peak memory 197608 kb
Host smart-244de822-8661-42d2-8855-55e579fe64e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696961630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2696961630
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2490121270
Short name T613
Test name
Test status
Simulation time 90497532 ps
CPU time 1.36 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:42:55 PM PST 24
Peak memory 196568 kb
Host smart-205d07ef-3a3a-4eb2-aa72-91aeff8fd239
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490121270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2490121270
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.388787061
Short name T286
Test name
Test status
Simulation time 245520771 ps
CPU time 2.59 seconds
Started Feb 04 02:42:44 PM PST 24
Finished Feb 04 02:42:48 PM PST 24
Peak memory 197864 kb
Host smart-bdd5694c-00ff-4d8c-ae88-272c29e97818
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388787061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.388787061
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.38299041
Short name T699
Test name
Test status
Simulation time 435732679 ps
CPU time 2.35 seconds
Started Feb 04 02:42:52 PM PST 24
Finished Feb 04 02:42:57 PM PST 24
Peak memory 196592 kb
Host smart-a1c77126-b51b-4b81-bede-deb9c1b33cec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38299041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.38299041
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2728953392
Short name T219
Test name
Test status
Simulation time 32584198 ps
CPU time 1.18 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:32 PM PST 24
Peak memory 196796 kb
Host smart-34d8e5b8-c751-4f48-888a-4ee66f0f1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728953392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2728953392
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1337642859
Short name T345
Test name
Test status
Simulation time 142469101 ps
CPU time 0.94 seconds
Started Feb 04 02:42:40 PM PST 24
Finished Feb 04 02:42:45 PM PST 24
Peak memory 195684 kb
Host smart-f6dc68a5-88b9-4850-99bc-20658780153f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337642859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1337642859
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2118424021
Short name T649
Test name
Test status
Simulation time 562946295 ps
CPU time 2.14 seconds
Started Feb 04 02:42:44 PM PST 24
Finished Feb 04 02:42:47 PM PST 24
Peak memory 197740 kb
Host smart-d976d111-54ef-4b4e-8049-49a31d0080ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118424021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2118424021
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2490370721
Short name T339
Test name
Test status
Simulation time 128736805 ps
CPU time 1.12 seconds
Started Feb 04 02:42:26 PM PST 24
Finished Feb 04 02:42:30 PM PST 24
Peak memory 196196 kb
Host smart-b51979d6-7b9b-4036-8007-ff059f525a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490370721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2490370721
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2420909858
Short name T264
Test name
Test status
Simulation time 368777751 ps
CPU time 1.09 seconds
Started Feb 04 02:42:28 PM PST 24
Finished Feb 04 02:42:31 PM PST 24
Peak memory 196144 kb
Host smart-70ce159b-c952-44d1-b6df-e24ddb2b447e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420909858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2420909858
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3766247841
Short name T288
Test name
Test status
Simulation time 29922248250 ps
CPU time 46.82 seconds
Started Feb 04 02:42:51 PM PST 24
Finished Feb 04 02:43:41 PM PST 24
Peak memory 197948 kb
Host smart-6a35bb7c-29f5-4dda-b01f-50924f9b549f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766247841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3766247841
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1595538732
Short name T469
Test name
Test status
Simulation time 252777266709 ps
CPU time 1299.48 seconds
Started Feb 04 02:42:45 PM PST 24
Finished Feb 04 03:04:26 PM PST 24
Peak memory 198004 kb
Host smart-a2357d21-289e-4b81-b657-d4df6c54ae9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1595538732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1595538732
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2060779794
Short name T201
Test name
Test status
Simulation time 171739406 ps
CPU time 0.98 seconds
Started Feb 04 04:15:15 PM PST 24
Finished Feb 04 04:15:18 PM PST 24
Peak memory 195524 kb
Host smart-f1cb7a0e-9a0c-4bbf-8637-1848bafdded2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2060779794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2060779794
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2041335192
Short name T157
Test name
Test status
Simulation time 77389548 ps
CPU time 1.6 seconds
Started Feb 04 04:14:56 PM PST 24
Finished Feb 04 04:14:58 PM PST 24
Peak memory 196960 kb
Host smart-e3ec9bf7-1f84-4047-ba49-36e22f9d29d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041335192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2041335192
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3918535922
Short name T176
Test name
Test status
Simulation time 51684123 ps
CPU time 1.34 seconds
Started Feb 04 04:15:14 PM PST 24
Finished Feb 04 04:15:18 PM PST 24
Peak memory 197032 kb
Host smart-de3eafa5-782a-41b0-b5f5-acae125a4e37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3918535922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3918535922
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.320767539
Short name T129
Test name
Test status
Simulation time 32998310 ps
CPU time 1.02 seconds
Started Feb 04 04:15:11 PM PST 24
Finished Feb 04 04:15:13 PM PST 24
Peak memory 196304 kb
Host smart-8a2de14d-e198-4733-9d03-c7698da2b16e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320767539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.320767539
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4164680062
Short name T205
Test name
Test status
Simulation time 48757701 ps
CPU time 0.81 seconds
Started Feb 04 04:15:43 PM PST 24
Finished Feb 04 04:15:46 PM PST 24
Peak memory 194372 kb
Host smart-d898375e-9dc7-4c72-98f8-c7695e6ad08a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4164680062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4164680062
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1439672812
Short name T178
Test name
Test status
Simulation time 113140788 ps
CPU time 1.2 seconds
Started Feb 04 04:15:38 PM PST 24
Finished Feb 04 04:15:41 PM PST 24
Peak memory 196868 kb
Host smart-10785d48-1580-4b0d-9285-359d4c3350f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439672812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1439672812
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.10141669
Short name T200
Test name
Test status
Simulation time 251683058 ps
CPU time 1.3 seconds
Started Feb 04 04:15:42 PM PST 24
Finished Feb 04 04:15:47 PM PST 24
Peak memory 195780 kb
Host smart-67a47d3c-c492-4b38-a5f5-7b74f8f9701e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=10141669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.10141669
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807831638
Short name T206
Test name
Test status
Simulation time 45250701 ps
CPU time 1.23 seconds
Started Feb 04 04:15:47 PM PST 24
Finished Feb 04 04:15:49 PM PST 24
Peak memory 196008 kb
Host smart-e3102f1c-ac0e-4a1e-b03d-7d08f502db1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807831638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2807831638
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.866162145
Short name T190
Test name
Test status
Simulation time 73996058 ps
CPU time 1.27 seconds
Started Feb 04 04:15:43 PM PST 24
Finished Feb 04 04:15:47 PM PST 24
Peak memory 196684 kb
Host smart-ab968edb-86ea-4d35-b208-37d2559567ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=866162145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.866162145
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2286757742
Short name T185
Test name
Test status
Simulation time 103040397 ps
CPU time 1.15 seconds
Started Feb 04 04:15:41 PM PST 24
Finished Feb 04 04:15:47 PM PST 24
Peak memory 195848 kb
Host smart-f4b1ee33-5baf-49f4-a544-13ef8c726821
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286757742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2286757742
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1894140562
Short name T164
Test name
Test status
Simulation time 247190597 ps
CPU time 1.64 seconds
Started Feb 04 04:15:43 PM PST 24
Finished Feb 04 04:15:47 PM PST 24
Peak memory 198136 kb
Host smart-9009a9e4-159b-4922-bed8-e99c18dfe337
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1894140562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1894140562
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956586856
Short name T141
Test name
Test status
Simulation time 265003693 ps
CPU time 1.14 seconds
Started Feb 04 04:16:23 PM PST 24
Finished Feb 04 04:16:25 PM PST 24
Peak memory 196692 kb
Host smart-2ad2654b-5028-46ef-9791-3093f2965e8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956586856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2956586856
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3125658097
Short name T209
Test name
Test status
Simulation time 62067177 ps
CPU time 1.24 seconds
Started Feb 04 04:15:52 PM PST 24
Finished Feb 04 04:15:54 PM PST 24
Peak memory 197068 kb
Host smart-d0f1f317-b855-49fa-8181-7c7dac197ff2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3125658097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3125658097
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.659676394
Short name T172
Test name
Test status
Simulation time 268394916 ps
CPU time 1.33 seconds
Started Feb 04 04:15:59 PM PST 24
Finished Feb 04 04:16:03 PM PST 24
Peak memory 195772 kb
Host smart-d7cbb2ff-f0c8-4b07-9107-5f64280a7856
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659676394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.659676394
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1680146025
Short name T179
Test name
Test status
Simulation time 209669199 ps
CPU time 1.26 seconds
Started Feb 04 04:15:58 PM PST 24
Finished Feb 04 04:16:01 PM PST 24
Peak memory 196892 kb
Host smart-2335934c-0ad8-4924-b9de-ddf541421f4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1680146025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1680146025
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3146559711
Short name T128
Test name
Test status
Simulation time 198970032 ps
CPU time 1.79 seconds
Started Feb 04 04:16:03 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196652 kb
Host smart-d0fc519f-552a-4ced-81ee-853686a87634
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146559711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3146559711
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2492921898
Short name T207
Test name
Test status
Simulation time 114011317 ps
CPU time 1.33 seconds
Started Feb 04 04:15:55 PM PST 24
Finished Feb 04 04:15:57 PM PST 24
Peak memory 198072 kb
Host smart-166a2e54-8968-4376-8fac-d61cacb3923e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2492921898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2492921898
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1296349330
Short name T194
Test name
Test status
Simulation time 184079394 ps
CPU time 1.36 seconds
Started Feb 04 04:16:04 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 195760 kb
Host smart-bf661a42-b522-464b-aa63-105ce8b2d1b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296349330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1296349330
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2933244754
Short name T171
Test name
Test status
Simulation time 207402376 ps
CPU time 1.13 seconds
Started Feb 04 04:16:04 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196608 kb
Host smart-5e6d5220-810e-4917-abfa-9665aa5b8c77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2933244754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2933244754
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3736404018
Short name T163
Test name
Test status
Simulation time 32835200 ps
CPU time 1.16 seconds
Started Feb 04 04:16:13 PM PST 24
Finished Feb 04 04:16:15 PM PST 24
Peak memory 196632 kb
Host smart-1909e8eb-7286-4bdd-9cec-ea2f20101cc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736404018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3736404018
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.804716453
Short name T132
Test name
Test status
Simulation time 271636048 ps
CPU time 1.61 seconds
Started Feb 04 04:16:03 PM PST 24
Finished Feb 04 04:16:10 PM PST 24
Peak memory 196868 kb
Host smart-f7a07bb7-4958-457a-a675-f4576145c39d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=804716453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.804716453
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1974316271
Short name T150
Test name
Test status
Simulation time 44243339 ps
CPU time 1.36 seconds
Started Feb 04 04:16:01 PM PST 24
Finished Feb 04 04:16:04 PM PST 24
Peak memory 198124 kb
Host smart-71793843-3629-44f5-8a60-3ff86bb74e10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974316271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1974316271
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4294854719
Short name T189
Test name
Test status
Simulation time 101401724 ps
CPU time 1.23 seconds
Started Feb 04 04:16:04 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196604 kb
Host smart-3c62f1d3-32ff-4574-97d6-0ca84bc0ce9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294854719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4294854719
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3026252214
Short name T170
Test name
Test status
Simulation time 166727051 ps
CPU time 1.21 seconds
Started Feb 04 04:15:15 PM PST 24
Finished Feb 04 04:15:18 PM PST 24
Peak memory 196556 kb
Host smart-9d182d29-cf56-4e0e-a35a-6099ebc99c42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3026252214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3026252214
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3631127399
Short name T144
Test name
Test status
Simulation time 30552901 ps
CPU time 0.84 seconds
Started Feb 04 04:15:12 PM PST 24
Finished Feb 04 04:15:14 PM PST 24
Peak memory 196200 kb
Host smart-1ee8a2b4-906a-46c3-a799-a76e7836537d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631127399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3631127399
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2677261630
Short name T195
Test name
Test status
Simulation time 154356804 ps
CPU time 1.32 seconds
Started Feb 04 04:16:04 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196008 kb
Host smart-1e3a42c5-ed66-4c08-bf3b-0833141ee721
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2677261630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2677261630
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1794141352
Short name T196
Test name
Test status
Simulation time 135776099 ps
CPU time 0.83 seconds
Started Feb 04 04:16:05 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 195300 kb
Host smart-63a7ff4a-785e-48ff-9dae-0ae482811585
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794141352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1794141352
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.951226684
Short name T147
Test name
Test status
Simulation time 171860267 ps
CPU time 1.51 seconds
Started Feb 04 04:16:01 PM PST 24
Finished Feb 04 04:16:04 PM PST 24
Peak memory 197028 kb
Host smart-ece5dae4-f8b2-49ed-9795-b9036bdf6ea6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=951226684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.951226684
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1390063326
Short name T180
Test name
Test status
Simulation time 136855563 ps
CPU time 1.06 seconds
Started Feb 04 04:16:01 PM PST 24
Finished Feb 04 04:16:04 PM PST 24
Peak memory 196208 kb
Host smart-b6e4590b-0966-468b-8efa-9a402418433b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390063326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1390063326
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.800670433
Short name T184
Test name
Test status
Simulation time 54459327 ps
CPU time 1.04 seconds
Started Feb 04 04:16:05 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196836 kb
Host smart-2b010ede-5ad4-4ee9-8d70-3b6bac22c016
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=800670433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.800670433
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2626143571
Short name T188
Test name
Test status
Simulation time 73932790 ps
CPU time 1.54 seconds
Started Feb 04 04:16:07 PM PST 24
Finished Feb 04 04:16:12 PM PST 24
Peak memory 198044 kb
Host smart-c426601b-3457-42db-b332-8580cda6856c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626143571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2626143571
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3931670796
Short name T126
Test name
Test status
Simulation time 316002253 ps
CPU time 1.63 seconds
Started Feb 04 04:16:20 PM PST 24
Finished Feb 04 04:16:23 PM PST 24
Peak memory 198076 kb
Host smart-eb561075-b392-4777-b44c-21fea6ffdbdf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3931670796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3931670796
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3153581005
Short name T177
Test name
Test status
Simulation time 50219702 ps
CPU time 1.38 seconds
Started Feb 04 04:16:05 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 198044 kb
Host smart-0d509fa6-7088-4611-9b03-0006346ca983
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153581005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3153581005
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1078659011
Short name T130
Test name
Test status
Simulation time 160122600 ps
CPU time 1.3 seconds
Started Feb 04 04:16:06 PM PST 24
Finished Feb 04 04:16:11 PM PST 24
Peak memory 196776 kb
Host smart-a4eec5b8-8f38-4756-a482-0dde76153876
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1078659011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1078659011
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711747031
Short name T127
Test name
Test status
Simulation time 134502829 ps
CPU time 1.37 seconds
Started Feb 04 04:16:18 PM PST 24
Finished Feb 04 04:16:21 PM PST 24
Peak memory 195768 kb
Host smart-a35aef73-e421-42e2-bbcb-06ec162e0979
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711747031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2711747031
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1722977480
Short name T42
Test name
Test status
Simulation time 134661609 ps
CPU time 1.18 seconds
Started Feb 04 04:16:11 PM PST 24
Finished Feb 04 04:16:13 PM PST 24
Peak memory 196012 kb
Host smart-7a2f7501-dfa2-4394-a15a-344fbd03f8f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1722977480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1722977480
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1223233243
Short name T146
Test name
Test status
Simulation time 53092300 ps
CPU time 1.05 seconds
Started Feb 04 04:16:17 PM PST 24
Finished Feb 04 04:16:20 PM PST 24
Peak memory 196768 kb
Host smart-84bfb47d-30ca-4b2d-a1be-3082c9fb43fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223233243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1223233243
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1581920869
Short name T165
Test name
Test status
Simulation time 47067210 ps
CPU time 1.12 seconds
Started Feb 04 04:16:20 PM PST 24
Finished Feb 04 04:16:22 PM PST 24
Peak memory 196752 kb
Host smart-44cbe657-362a-4c35-88ee-c015ec81e289
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1581920869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1581920869
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2315051775
Short name T137
Test name
Test status
Simulation time 169252513 ps
CPU time 1.09 seconds
Started Feb 04 04:16:11 PM PST 24
Finished Feb 04 04:16:13 PM PST 24
Peak memory 196000 kb
Host smart-cbec9894-4a22-47e2-a7aa-fc8786a33962
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315051775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2315051775
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2939100227
Short name T142
Test name
Test status
Simulation time 59257043 ps
CPU time 1.28 seconds
Started Feb 04 04:16:14 PM PST 24
Finished Feb 04 04:16:16 PM PST 24
Peak memory 195720 kb
Host smart-d01e5adf-7bda-4166-a38b-b87295827e55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2939100227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2939100227
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575332229
Short name T124
Test name
Test status
Simulation time 176595339 ps
CPU time 1.23 seconds
Started Feb 04 04:16:27 PM PST 24
Finished Feb 04 04:16:28 PM PST 24
Peak memory 196692 kb
Host smart-e8b9d7b4-3ccb-4618-890a-48be8b203fe0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575332229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.575332229
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3416263310
Short name T138
Test name
Test status
Simulation time 221340695 ps
CPU time 1.35 seconds
Started Feb 04 04:16:22 PM PST 24
Finished Feb 04 04:16:24 PM PST 24
Peak memory 196544 kb
Host smart-a6299ac1-5be6-4cfb-b585-4bd35155e719
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3416263310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3416263310
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3925719700
Short name T203
Test name
Test status
Simulation time 109928644 ps
CPU time 1.34 seconds
Started Feb 04 04:16:23 PM PST 24
Finished Feb 04 04:16:26 PM PST 24
Peak memory 196080 kb
Host smart-a55a2287-8fc2-44c3-8cac-815c31679e1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925719700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3925719700
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.346457932
Short name T59
Test name
Test status
Simulation time 79646049 ps
CPU time 1.52 seconds
Started Feb 04 04:16:20 PM PST 24
Finished Feb 04 04:16:23 PM PST 24
Peak memory 197020 kb
Host smart-61f938fb-1045-4638-ad14-4fa96836255a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=346457932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.346457932
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2202766238
Short name T143
Test name
Test status
Simulation time 25483610 ps
CPU time 0.84 seconds
Started Feb 04 04:16:24 PM PST 24
Finished Feb 04 04:16:26 PM PST 24
Peak memory 195412 kb
Host smart-ceaf4c82-e85a-4e69-ae08-d90934dba308
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202766238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2202766238
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1761286121
Short name T159
Test name
Test status
Simulation time 47764437 ps
CPU time 1.13 seconds
Started Feb 04 04:15:12 PM PST 24
Finished Feb 04 04:15:14 PM PST 24
Peak memory 195960 kb
Host smart-ea9e7f49-4f89-4672-8895-df2eab67f4e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1761286121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1761286121
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1599095154
Short name T135
Test name
Test status
Simulation time 114401311 ps
CPU time 0.83 seconds
Started Feb 04 04:15:10 PM PST 24
Finished Feb 04 04:15:11 PM PST 24
Peak memory 195508 kb
Host smart-21299693-d4e7-4f42-bbcf-a8b281c67ab8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599095154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1599095154
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2106755236
Short name T181
Test name
Test status
Simulation time 407488712 ps
CPU time 1.69 seconds
Started Feb 04 04:16:27 PM PST 24
Finished Feb 04 04:16:30 PM PST 24
Peak memory 198032 kb
Host smart-785b0502-77ac-4a45-82c7-d09a34f1637f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2106755236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2106755236
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3255744940
Short name T208
Test name
Test status
Simulation time 479411909 ps
CPU time 1 seconds
Started Feb 04 04:16:19 PM PST 24
Finished Feb 04 04:16:21 PM PST 24
Peak memory 196528 kb
Host smart-fe7cf0ad-2db0-4838-a23f-099e70d8fbb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255744940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3255744940
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4180243201
Short name T175
Test name
Test status
Simulation time 48460899 ps
CPU time 0.98 seconds
Started Feb 04 04:16:20 PM PST 24
Finished Feb 04 04:16:22 PM PST 24
Peak memory 195876 kb
Host smart-68f2a02c-1656-488a-9f37-fc8cc3c47848
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4180243201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4180243201
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1170393123
Short name T174
Test name
Test status
Simulation time 80479825 ps
CPU time 1.33 seconds
Started Feb 04 04:16:26 PM PST 24
Finished Feb 04 04:16:29 PM PST 24
Peak memory 197072 kb
Host smart-8466da3a-cf0f-4084-be2a-10315863e9f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170393123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1170393123
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1584582605
Short name T57
Test name
Test status
Simulation time 228887534 ps
CPU time 1.11 seconds
Started Feb 04 04:16:43 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 196004 kb
Host smart-9c0f66bd-a4e3-48a9-87dd-fed6a98a51a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1584582605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1584582605
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.149817357
Short name T60
Test name
Test status
Simulation time 44781031 ps
CPU time 1.24 seconds
Started Feb 04 04:16:45 PM PST 24
Finished Feb 04 04:16:47 PM PST 24
Peak memory 196504 kb
Host smart-72893c01-b946-46d4-a17f-944afecef27c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149817357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.149817357
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4255889698
Short name T169
Test name
Test status
Simulation time 26352764 ps
CPU time 0.94 seconds
Started Feb 04 04:16:46 PM PST 24
Finished Feb 04 04:16:47 PM PST 24
Peak memory 196448 kb
Host smart-999cb33e-08e1-480f-be00-f12fa6cb320f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4255889698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4255889698
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1730088065
Short name T161
Test name
Test status
Simulation time 186374241 ps
CPU time 1.53 seconds
Started Feb 04 04:16:43 PM PST 24
Finished Feb 04 04:16:46 PM PST 24
Peak memory 196952 kb
Host smart-ff438d00-413f-42d9-b1ea-8c8675235a37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730088065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1730088065
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.774102070
Short name T162
Test name
Test status
Simulation time 41755207 ps
CPU time 1.31 seconds
Started Feb 04 04:16:43 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 196008 kb
Host smart-0cfc1c26-2057-44f5-9262-e8b611793529
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=774102070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.774102070
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1588721872
Short name T197
Test name
Test status
Simulation time 61190731 ps
CPU time 1.34 seconds
Started Feb 04 04:16:37 PM PST 24
Finished Feb 04 04:16:39 PM PST 24
Peak memory 198112 kb
Host smart-d8fe0095-7af2-4ea9-8d7c-b19632f5cc97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588721872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1588721872
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2826603776
Short name T149
Test name
Test status
Simulation time 19407644 ps
CPU time 0.78 seconds
Started Feb 04 04:16:41 PM PST 24
Finished Feb 04 04:16:44 PM PST 24
Peak memory 195000 kb
Host smart-786eedb5-f391-40ba-9408-8b342613be55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2826603776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2826603776
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511606507
Short name T182
Test name
Test status
Simulation time 53869817 ps
CPU time 1.17 seconds
Started Feb 04 04:16:36 PM PST 24
Finished Feb 04 04:16:38 PM PST 24
Peak memory 196660 kb
Host smart-b2222427-08e3-4635-b2c7-d8436a586fdd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511606507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1511606507
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.789921143
Short name T202
Test name
Test status
Simulation time 175238681 ps
CPU time 1.02 seconds
Started Feb 04 04:16:38 PM PST 24
Finished Feb 04 04:16:44 PM PST 24
Peak memory 195752 kb
Host smart-d095c522-b1be-4f53-a8f9-d1d97ab8aed2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=789921143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.789921143
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2381455396
Short name T198
Test name
Test status
Simulation time 134338593 ps
CPU time 1.48 seconds
Started Feb 04 04:16:46 PM PST 24
Finished Feb 04 04:16:49 PM PST 24
Peak memory 196764 kb
Host smart-287f2004-c439-4c51-b24e-edcccd380374
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381455396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2381455396
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2393775471
Short name T139
Test name
Test status
Simulation time 146448155 ps
CPU time 0.96 seconds
Started Feb 04 04:16:47 PM PST 24
Finished Feb 04 04:16:49 PM PST 24
Peak memory 195560 kb
Host smart-978cf7db-2416-4f1f-a731-161d2e7d3a2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393775471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2393775471
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2777641873
Short name T191
Test name
Test status
Simulation time 52974291 ps
CPU time 1.42 seconds
Started Feb 04 04:16:39 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 197996 kb
Host smart-1cfafc79-19c1-43af-b8bd-f0a2143d80c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2777641873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2777641873
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.458622916
Short name T54
Test name
Test status
Simulation time 429683080 ps
CPU time 1.41 seconds
Started Feb 04 04:16:42 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 197024 kb
Host smart-3a557836-39f2-486e-a806-83ac749fabd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458622916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.458622916
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3985466316
Short name T212
Test name
Test status
Simulation time 49920947 ps
CPU time 1.31 seconds
Started Feb 04 04:16:42 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 196588 kb
Host smart-c2e58b95-4c42-4213-ad24-8d822529a41a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3985466316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3985466316
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2692475813
Short name T145
Test name
Test status
Simulation time 327698377 ps
CPU time 1.32 seconds
Started Feb 04 04:16:48 PM PST 24
Finished Feb 04 04:16:50 PM PST 24
Peak memory 196724 kb
Host smart-e08e8c0d-dac2-44cb-a95b-f14720182af6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692475813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2692475813
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1691830448
Short name T168
Test name
Test status
Simulation time 176982086 ps
CPU time 1.09 seconds
Started Feb 04 04:15:12 PM PST 24
Finished Feb 04 04:15:14 PM PST 24
Peak memory 196768 kb
Host smart-4e54411a-23d3-4ac9-af36-4ff69fd09d0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1691830448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1691830448
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2620795098
Short name T131
Test name
Test status
Simulation time 676084326 ps
CPU time 1.28 seconds
Started Feb 04 04:15:17 PM PST 24
Finished Feb 04 04:15:19 PM PST 24
Peak memory 198096 kb
Host smart-1fed7390-36f1-4973-b2b9-975504d49df1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620795098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2620795098
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2000674473
Short name T136
Test name
Test status
Simulation time 306887245 ps
CPU time 1.78 seconds
Started Feb 04 04:16:48 PM PST 24
Finished Feb 04 04:16:50 PM PST 24
Peak memory 197440 kb
Host smart-2816d7d8-4e8a-4310-a353-86e2ea2863e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2000674473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2000674473
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.484683545
Short name T140
Test name
Test status
Simulation time 63100152 ps
CPU time 0.97 seconds
Started Feb 04 04:16:45 PM PST 24
Finished Feb 04 04:16:47 PM PST 24
Peak memory 197124 kb
Host smart-baa8d63a-fe06-4dd1-aaae-5585b27e36ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484683545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.484683545
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2529710514
Short name T199
Test name
Test status
Simulation time 321631289 ps
CPU time 1.37 seconds
Started Feb 04 04:16:42 PM PST 24
Finished Feb 04 04:16:45 PM PST 24
Peak memory 196784 kb
Host smart-856e95b4-745d-4092-a111-47396818f6f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2529710514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2529710514
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3910881659
Short name T44
Test name
Test status
Simulation time 73711277 ps
CPU time 1.22 seconds
Started Feb 04 04:16:46 PM PST 24
Finished Feb 04 04:16:48 PM PST 24
Peak memory 196592 kb
Host smart-7400ca31-687c-46f4-b625-40ccdb5b0daf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910881659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3910881659
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.310239992
Short name T204
Test name
Test status
Simulation time 83596224 ps
CPU time 1.47 seconds
Started Feb 04 04:17:05 PM PST 24
Finished Feb 04 04:17:08 PM PST 24
Peak memory 198012 kb
Host smart-82407b5c-c6b8-44c6-bd63-511c4a44c90e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=310239992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.310239992
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604819008
Short name T56
Test name
Test status
Simulation time 422525230 ps
CPU time 1.09 seconds
Started Feb 04 04:16:57 PM PST 24
Finished Feb 04 04:16:59 PM PST 24
Peak memory 195788 kb
Host smart-bc3a9eff-5c35-4c39-8075-d00568dbec0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604819008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3604819008
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.343286938
Short name T133
Test name
Test status
Simulation time 75733136 ps
CPU time 1.51 seconds
Started Feb 04 04:16:56 PM PST 24
Finished Feb 04 04:16:58 PM PST 24
Peak memory 198096 kb
Host smart-0bfe8b50-bb99-4ae6-862b-477c9579a1a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=343286938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.343286938
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1850647737
Short name T154
Test name
Test status
Simulation time 233375488 ps
CPU time 1.42 seconds
Started Feb 04 04:17:01 PM PST 24
Finished Feb 04 04:17:06 PM PST 24
Peak memory 198116 kb
Host smart-2570fc99-e856-44b3-a22a-0625f6901ce6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850647737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1850647737
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3369229230
Short name T148
Test name
Test status
Simulation time 123061297 ps
CPU time 1.33 seconds
Started Feb 04 04:16:55 PM PST 24
Finished Feb 04 04:16:57 PM PST 24
Peak memory 198080 kb
Host smart-00615887-7124-41bd-b7be-044d1a0b5fc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3369229230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3369229230
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2518182379
Short name T153
Test name
Test status
Simulation time 250972247 ps
CPU time 1.21 seconds
Started Feb 04 04:16:58 PM PST 24
Finished Feb 04 04:17:00 PM PST 24
Peak memory 196740 kb
Host smart-bbbf989e-c490-424c-a57d-bd257ff69c17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518182379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2518182379
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.112941920
Short name T103
Test name
Test status
Simulation time 142583046 ps
CPU time 1.25 seconds
Started Feb 04 04:17:07 PM PST 24
Finished Feb 04 04:17:10 PM PST 24
Peak memory 196544 kb
Host smart-d715c9d5-b86c-41ed-9d19-c6c8af3d782d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=112941920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.112941920
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1209436593
Short name T173
Test name
Test status
Simulation time 148165785 ps
CPU time 1.73 seconds
Started Feb 04 04:17:05 PM PST 24
Finished Feb 04 04:17:08 PM PST 24
Peak memory 196840 kb
Host smart-67e6d14a-b50a-4f7e-b833-85b56b63a619
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209436593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1209436593
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.136482233
Short name T55
Test name
Test status
Simulation time 180931693 ps
CPU time 0.97 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 196464 kb
Host smart-bff04b04-3d05-4fb5-97fc-5d2fa4cb680a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=136482233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.136482233
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1753216786
Short name T187
Test name
Test status
Simulation time 145967225 ps
CPU time 1.38 seconds
Started Feb 04 04:17:09 PM PST 24
Finished Feb 04 04:17:13 PM PST 24
Peak memory 196040 kb
Host smart-1f02fb72-3f60-4883-bc66-6534c6293603
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753216786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1753216786
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.738358418
Short name T134
Test name
Test status
Simulation time 150361276 ps
CPU time 1.39 seconds
Started Feb 04 04:17:01 PM PST 24
Finished Feb 04 04:17:06 PM PST 24
Peak memory 195700 kb
Host smart-9ec5d781-d784-4004-95b7-df89f5c488da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=738358418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.738358418
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3096458623
Short name T151
Test name
Test status
Simulation time 58122262 ps
CPU time 1.19 seconds
Started Feb 04 04:17:27 PM PST 24
Finished Feb 04 04:17:29 PM PST 24
Peak memory 197296 kb
Host smart-43559d11-9699-43f4-ab2c-74ddbc86b26b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096458623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3096458623
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3496789112
Short name T211
Test name
Test status
Simulation time 53254600 ps
CPU time 1.75 seconds
Started Feb 04 04:17:05 PM PST 24
Finished Feb 04 04:17:08 PM PST 24
Peak memory 198144 kb
Host smart-5711ac77-9f99-435b-b0f9-a8ef4f17a7f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3496789112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3496789112
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.979406649
Short name T166
Test name
Test status
Simulation time 39335439 ps
CPU time 1.11 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 196076 kb
Host smart-10c0942b-a1e8-4ea5-9cf8-a74e86a46fdb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979406649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.979406649
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3939465798
Short name T125
Test name
Test status
Simulation time 933058091 ps
CPU time 1.52 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:06 PM PST 24
Peak memory 197012 kb
Host smart-ace6e3e2-e85c-4d73-92eb-b13aa4eb1f23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3939465798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3939465798
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3351778328
Short name T183
Test name
Test status
Simulation time 85772138 ps
CPU time 1.45 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:06 PM PST 24
Peak memory 196664 kb
Host smart-e60a944f-47b7-4e6b-91c9-2b9a57f3dd52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351778328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3351778328
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3066104238
Short name T156
Test name
Test status
Simulation time 81250844 ps
CPU time 1.33 seconds
Started Feb 04 04:15:19 PM PST 24
Finished Feb 04 04:15:25 PM PST 24
Peak memory 196944 kb
Host smart-b2cf1c33-ad42-4f6e-842e-b0993928f417
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3066104238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3066104238
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.680269245
Short name T186
Test name
Test status
Simulation time 115688483 ps
CPU time 1.03 seconds
Started Feb 04 04:15:23 PM PST 24
Finished Feb 04 04:15:25 PM PST 24
Peak memory 196352 kb
Host smart-0ee75c5c-b50f-4427-bcf3-79b8c1c740d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680269245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.680269245
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3873060191
Short name T152
Test name
Test status
Simulation time 265956394 ps
CPU time 1.31 seconds
Started Feb 04 04:15:28 PM PST 24
Finished Feb 04 04:15:30 PM PST 24
Peak memory 195684 kb
Host smart-a1671417-1741-4071-b28d-7b627565f5e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3873060191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3873060191
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2478936395
Short name T160
Test name
Test status
Simulation time 43223185 ps
CPU time 1.35 seconds
Started Feb 04 04:15:27 PM PST 24
Finished Feb 04 04:15:29 PM PST 24
Peak memory 196692 kb
Host smart-51799aa2-cbf3-4724-a0c6-c832ce80a2ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478936395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2478936395
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3588726233
Short name T192
Test name
Test status
Simulation time 78854925 ps
CPU time 1.44 seconds
Started Feb 04 04:15:28 PM PST 24
Finished Feb 04 04:15:30 PM PST 24
Peak memory 195988 kb
Host smart-6c3b070b-1037-49a8-9406-49e25fb14f9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3588726233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3588726233
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2927756421
Short name T193
Test name
Test status
Simulation time 20397135 ps
CPU time 0.81 seconds
Started Feb 04 04:15:27 PM PST 24
Finished Feb 04 04:15:29 PM PST 24
Peak memory 195476 kb
Host smart-12b45f89-4d9b-4baa-adf6-873769fcdee5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927756421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2927756421
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3705670156
Short name T167
Test name
Test status
Simulation time 318075857 ps
CPU time 1.27 seconds
Started Feb 04 04:15:29 PM PST 24
Finished Feb 04 04:15:31 PM PST 24
Peak memory 198056 kb
Host smart-4a26f388-2a29-407c-9e0c-f9aaf93e9491
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3705670156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3705670156
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701335934
Short name T155
Test name
Test status
Simulation time 39183122 ps
CPU time 1.23 seconds
Started Feb 04 04:15:32 PM PST 24
Finished Feb 04 04:15:34 PM PST 24
Peak memory 195928 kb
Host smart-5f4ece01-7090-4c86-8890-da32a455074c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701335934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3701335934
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1248386680
Short name T210
Test name
Test status
Simulation time 139972514 ps
CPU time 1.19 seconds
Started Feb 04 04:15:31 PM PST 24
Finished Feb 04 04:15:33 PM PST 24
Peak memory 198084 kb
Host smart-26de6012-4b45-45cd-a39b-db2f5d479a7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1248386680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1248386680
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2671414705
Short name T158
Test name
Test status
Simulation time 73675548 ps
CPU time 1.22 seconds
Started Feb 04 04:15:33 PM PST 24
Finished Feb 04 04:15:35 PM PST 24
Peak memory 198084 kb
Host smart-4b14c68a-ea21-437d-91d3-f450c76fa366
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671414705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2671414705
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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