Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5689244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27529800

1

T16

227

T1

256

T11

595

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12759046	1			T16	112		T1	126		T11	153
values[0x0]	10020479	1			T16	55		T1	64		T11	215
values[0x1]	10439519	1			T16	60		T1	66		T11	262

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4316412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28902632

1

T16

227

T1

256

T11

621

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	135841	1			T2	6		T13	1		T31	2
valid_sources[0x01]	113941	1			T7	5		T83	1		T69	2
valid_sources[0x02]	125177	1			T1	2		T2	1		T8	35
valid_sources[0x03]	123786	1			T1	2		T4	1		T8	5
valid_sources[0x04]	191357	1			T12	3		T5	3		T26	1
valid_sources[0x05]	118411	1			T2	1		T26	1		T31	4
valid_sources[0x06]	125164	1			T26	2		T31	1		T83	4
valid_sources[0x07]	132991	1			T11	8		T2	6		T64	4
valid_sources[0x08]	120615	1			T1	7		T4	1		T31	9
valid_sources[0x09]	127086	1			T17	1		T31	2		T9	3
valid_sources[0x0a]	122085	1			T11	3		T7	5		T8	10
valid_sources[0x0b]	121588	1			T11	4		T2	3		T4	1
valid_sources[0x0c]	118368	1			T11	2		T31	1		T15	1
valid_sources[0x0d]	121426	1			T1	3		T11	17		T8	14
valid_sources[0x0e]	119955	1			T1	1		T11	1		T24	7
valid_sources[0x0f]	119013	1			T11	4		T2	7		T5	2
valid_sources[0x10]	125823	1			T11	2		T4	1		T31	1
valid_sources[0x11]	123562	1			T2	6		T31	6		T83	1
valid_sources[0x12]	122672	1			T11	3		T31	2		T69	4
valid_sources[0x13]	115330	1			T17	1		T18	1		T31	3
valid_sources[0x14]	120892	1			T1	5		T2	3		T18	1
valid_sources[0x15]	121160	1			T11	4		T5	1		T26	1
valid_sources[0x16]	118776	1			T1	5		T7	5		T31	4
valid_sources[0x17]	125208	1			T26	1		T31	7		T64	2
valid_sources[0x18]	121640	1			T2	4		T6	1		T8	22
valid_sources[0x19]	161857	1			T1	1		T26	1		T81	1
valid_sources[0x1a]	120451	1			T5	2		T31	17		T10	2
valid_sources[0x1b]	125435	1			T11	2		T2	2		T31	2
valid_sources[0x1c]	121161	1			T2	10		T12	8		T8	2
valid_sources[0x1d]	125208	1			T1	4		T2	5		T5	2
valid_sources[0x1e]	123076	1			T1	6		T6	1		T7	6
valid_sources[0x1f]	127105	1			T2	3		T8	22		T26	1
valid_sources[0x20]	121139	1			T1	2		T31	2		T15	1
valid_sources[0x21]	214082	1			T11	3		T26	1		T31	3
valid_sources[0x22]	126788	1			T2	11		T5	1		T7	3
valid_sources[0x23]	253450	1			T1	1		T11	10		T2	5
valid_sources[0x24]	124709	1			T1	4		T11	2		T12	12
valid_sources[0x25]	128335	1			T11	1		T4	1		T8	10
valid_sources[0x26]	127835	1			T16	27		T11	4		T17	2
valid_sources[0x27]	128212	1			T1	1		T2	3		T5	1
valid_sources[0x28]	119873	1			T11	3		T2	3		T31	3
valid_sources[0x29]	124110	1			T6	1		T17	3		T31	3
valid_sources[0x2a]	127224	1			T11	1		T7	1		T26	1
valid_sources[0x2b]	113824	1			T16	18		T11	2		T2	1
valid_sources[0x2c]	127820	1			T4	1		T26	2		T31	9
valid_sources[0x2d]	180247	1			T4	1		T9	2		T10	3
valid_sources[0x2e]	115201	1			T1	5		T11	4		T31	2
valid_sources[0x2f]	130491	1			T11	7		T12	2		T26	1
valid_sources[0x30]	120069	1			T11	6		T12	9		T31	2
valid_sources[0x31]	118225	1			T8	3		T17	2		T26	1
valid_sources[0x32]	124246	1			T67	3		T26	2		T68	9
valid_sources[0x33]	122183	1			T16	16		T11	1		T31	1
valid_sources[0x34]	120150	1			T2	1		T5	2		T17	2
valid_sources[0x35]	119360	1			T5	1		T17	1		T26	3
valid_sources[0x36]	127518	1			T1	2		T11	16		T15	1
valid_sources[0x37]	119271	1			T1	12		T11	6		T2	4
valid_sources[0x38]	116124	1			T26	1		T31	6		T10	2
valid_sources[0x39]	123817	1			T16	10		T4	1		T8	4
valid_sources[0x3a]	122447	1			T11	1		T26	1		T31	2
valid_sources[0x3b]	126524	1			T11	1		T4	1		T31	9
valid_sources[0x3c]	127940	1			T11	1		T2	11		T5	1
valid_sources[0x3d]	133652	1			T8	6		T26	1		T31	1
valid_sources[0x3e]	121614	1			T8	10		T31	1		T10	1
valid_sources[0x3f]	125890	1			T1	1		T2	2		T12	1
valid_sources[0x40]	129301	1			T11	5		T4	1		T15	1
valid_sources[0x41]	137383	1			T1	1		T11	2		T8	7
valid_sources[0x42]	126445	1			T1	5		T4	1		T26	1
valid_sources[0x43]	117412	1			T2	9		T4	1		T12	14
valid_sources[0x44]	122515	1			T1	6		T11	13		T4	1
valid_sources[0x45]	121616	1			T26	3		T31	2		T10	1
valid_sources[0x46]	119877	1			T2	12		T6	1		T8	4
valid_sources[0x47]	122780	1			T1	2		T5	1		T6	2
valid_sources[0x48]	130229	1			T11	21		T8	22		T67	2
valid_sources[0x49]	129924	1			T2	8		T4	1		T26	1
valid_sources[0x4a]	128481	1			T1	2		T11	4		T8	14
valid_sources[0x4b]	126005	1			T1	1		T11	3		T2	5
valid_sources[0x4c]	126620	1			T1	2		T11	6		T2	4
valid_sources[0x4d]	155706	1			T11	2		T4	1		T8	1
valid_sources[0x4e]	127338	1			T1	1		T11	6		T5	1
valid_sources[0x4f]	123603	1			T11	13		T2	3		T26	1
valid_sources[0x50]	130750	1			T11	18		T2	17		T31	1
valid_sources[0x51]	128634	1			T11	2		T26	2		T9	12
valid_sources[0x52]	118292	1			T11	9		T31	8		T69	1
valid_sources[0x53]	121978	1			T16	19		T11	3		T8	7
valid_sources[0x54]	129121	1			T11	1		T2	2		T7	4
valid_sources[0x55]	121326	1			T2	19		T4	1		T10	8
valid_sources[0x56]	125598	1			T8	1		T26	1		T83	1
valid_sources[0x57]	124075	1			T1	5		T11	1		T4	1
valid_sources[0x58]	127474	1			T1	1		T26	1		T31	1
valid_sources[0x59]	211057	1			T11	5		T2	7		T4	1
valid_sources[0x5a]	133036	1			T1	1		T11	11		T5	1
valid_sources[0x5b]	122913	1			T4	1		T5	1		T13	1
valid_sources[0x5c]	131585	1			T1	6		T4	1		T5	1
valid_sources[0x5d]	117680	1			T16	6		T8	24		T31	9
valid_sources[0x5e]	125740	1			T11	3		T2	8		T5	1
valid_sources[0x5f]	129819	1			T1	2		T2	8		T4	1
valid_sources[0x60]	125226	1			T12	4		T26	2		T18	1
valid_sources[0x61]	127165	1			T1	2		T11	1		T26	1
valid_sources[0x62]	127710	1			T11	4		T5	1		T26	1
valid_sources[0x63]	117484	1			T16	2		T1	1		T2	11
valid_sources[0x64]	128045	1			T1	1		T3	9		T4	1
valid_sources[0x65]	127383	1			T2	17		T12	7		T8	33
valid_sources[0x66]	118821	1			T11	8		T4	1		T6	1
valid_sources[0x67]	123375	1			T1	1		T5	1		T8	70
valid_sources[0x68]	124046	1			T1	1		T11	2		T2	9
valid_sources[0x69]	115559	1			T16	2		T11	5		T2	7
valid_sources[0x6a]	115391	1			T1	2		T11	12		T2	2
valid_sources[0x6b]	128730	1			T6	2		T31	1		T10	2
valid_sources[0x6c]	119245	1			T11	1		T13	1		T31	2
valid_sources[0x6d]	117922	1			T11	1		T4	1		T26	2
valid_sources[0x6e]	136094	1			T16	9		T1	1		T8	2
valid_sources[0x6f]	225383	1			T11	9		T67	14		T31	4
valid_sources[0x70]	129807	1			T1	4		T5	1		T26	2
valid_sources[0x71]	149474	1			T11	16		T26	3		T31	2
valid_sources[0x72]	241511	1			T11	3		T8	4		T31	8
valid_sources[0x73]	247346	1			T7	3		T71	4		T65	1
valid_sources[0x74]	114541	1			T16	11		T2	21		T5	3
valid_sources[0x75]	123652	1			T1	1		T2	9		T8	7
valid_sources[0x76]	123277	1			T1	2		T11	20		T2	3
valid_sources[0x77]	251824	1			T2	6		T4	1		T32	10
valid_sources[0x78]	118075	1			T1	1		T11	1		T31	2
valid_sources[0x79]	114059	1			T11	2		T7	5		T26	1
valid_sources[0x7a]	122021	1			T1	2		T2	18		T6	1
valid_sources[0x7b]	129855	1			T2	3		T10	2		T81	1
valid_sources[0x7c]	122484	1			T1	4		T11	2		T6	1
valid_sources[0x7d]	129014	1			T31	3		T15	1		T9	8
valid_sources[0x7e]	133583	1			T1	6		T31	1		T9	3
valid_sources[0x7f]	122908	1			T11	5		T2	7		T7	8
valid_sources[0x80]	126581	1			T1	7		T2	2		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7576685

1

T16

112

T1

126

T11

153

values[0x0]

all_enables

biggest_size

9978233

1

T16

55

T1

64

T11

212

values[0x1]

all_enables

biggest_size

9974882

1

T16

60

T1

66

T11

230