Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	355121917	0	0	0
ctrl_en_input_filter_rd_A	355121917	422076	0	0
intr_ctrl_en_falling_rd_A	355121917	448234	0	0
intr_ctrl_en_lvlhigh_rd_A	355121917	420027	0	0
intr_ctrl_en_lvllow_rd_A	355121917	450930	0	0
intr_ctrl_en_rising_rd_A	355121917	425906	0	0
intr_enable_rd_A	355121917	425395	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	422076	0	0
T1	2844	47	0	0
T2	14843	110	0	0
T3	1193	9	0	0
T4	1441	2	0	0
T5	1138	14	0	0
T6	1552	9	0	0
T7	3009	88	0	0
T8	0	78	0	0
T9	0	35	0	0
T10	0	81	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	448234	0	0
T1	2844	68	0	0
T2	14843	111	0	0
T3	1193	4	0	0
T4	1441	13	0	0
T5	1138	17	0	0
T6	1552	10	0	0
T7	3009	102	0	0
T8	0	90	0	0
T9	0	33	0	0
T10	0	60	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	420027	0	0
T1	2844	76	0	0
T2	14843	119	0	0
T3	1193	3	0	0
T4	1441	11	0	0
T5	1138	21	0	0
T6	1552	6	0	0
T7	3009	64	0	0
T8	0	49	0	0
T9	0	28	0	0
T10	0	86	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	450930	0	0
T1	2844	72	0	0
T2	14843	103	0	0
T3	1193	5	0	0
T4	1441	8	0	0
T5	1138	19	0	0
T6	1552	7	0	0
T7	3009	89	0	0
T8	0	69	0	0
T9	0	14	0	0
T10	0	91	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	425906	0	0
T1	2844	20	0	0
T2	14843	146	0	0
T3	1193	7	0	0
T4	1441	8	0	0
T5	1138	8	0	0
T6	1552	9	0	0
T7	3009	86	0	0
T8	0	28	0	0
T9	0	62	0	0
T10	0	54	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355121917	425395	0	0
T1	2844	57	0	0
T2	14843	90	0	0
T3	1193	9	0	0
T4	1441	11	0	0
T5	1138	13	0	0
T6	1552	3	0	0
T7	3009	76	0	0
T8	0	62	0	0
T11	3575	0	0	0
T12	1883	0	0	0
T13	1952	0	0	0
T14	0	31	0	0
T15	0	12	0	0