Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3569103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16464905

1

T30

322673

T31

299

T32

216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7873201	1			T30	153432		T31	70		T32	120
values[0x0]	5966909	1			T30	117448		T31	132		T32	65
values[0x1]	6193898	1			T30	122031		T31	127		T32	83

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2729478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17304530

1

T30

339069

T31

307

T32

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	67259	1			T30	109		T31	1		T22	2
valid_sources[0x01]	79035	1			T30	1426		T22	3		T24	4
valid_sources[0x02]	65120	1			T30	65		T31	2		T20	2
valid_sources[0x03]	80809	1			T30	2083		T31	1		T22	1
valid_sources[0x04]	77814	1			T30	148		T22	2		T24	5
valid_sources[0x05]	76066	1			T30	2335		T22	6		T24	3
valid_sources[0x06]	75856	1			T30	579		T24	5		T25	3
valid_sources[0x07]	74677	1			T30	2031		T22	1		T23	1
valid_sources[0x08]	75436	1			T30	338		T20	1		T24	3
valid_sources[0x09]	76841	1			T30	1503		T22	1		T24	6
valid_sources[0x0a]	67568	1			T30	719		T22	7		T24	6
valid_sources[0x0b]	77970	1			T30	224		T31	2		T20	1
valid_sources[0x0c]	85281	1			T30	2613		T31	1		T20	1
valid_sources[0x0d]	70279	1			T30	494		T31	1		T22	2
valid_sources[0x0e]	79579	1			T30	614		T31	2		T23	5
valid_sources[0x0f]	74245	1			T30	397		T23	2		T24	6
valid_sources[0x10]	76664	1			T30	443		T31	2		T24	5
valid_sources[0x11]	76433	1			T30	951		T31	2		T20	1
valid_sources[0x12]	83093	1			T30	250		T31	2		T22	1
valid_sources[0x13]	70972	1			T30	233		T31	4		T24	5
valid_sources[0x14]	76203	1			T30	1495		T22	1		T24	3
valid_sources[0x15]	70204	1			T30	1337		T24	2		T26	4
valid_sources[0x16]	74130	1			T30	1638		T22	2		T24	9
valid_sources[0x17]	76020	1			T30	1424		T20	3		T24	10
valid_sources[0x18]	76268	1			T30	4191		T33	885		T23	1
valid_sources[0x19]	74005	1			T30	126		T22	2		T24	3
valid_sources[0x1a]	70753	1			T30	50		T22	3		T24	6
valid_sources[0x1b]	191944	1			T30	220		T22	2		T24	2
valid_sources[0x1c]	70672	1			T30	139		T24	7		T25	1
valid_sources[0x1d]	85338	1			T30	4350		T31	1		T24	7
valid_sources[0x1e]	70403	1			T30	640		T24	5		T25	2
valid_sources[0x1f]	67992	1			T30	173		T22	3		T23	1
valid_sources[0x20]	73098	1			T30	334		T24	4		T26	3
valid_sources[0x21]	76352	1			T30	4472		T31	4		T24	6
valid_sources[0x22]	70405	1			T30	261		T23	2		T24	3
valid_sources[0x23]	67467	1			T30	891		T31	3		T22	1
valid_sources[0x24]	71396	1			T30	465		T31	8		T24	7
valid_sources[0x25]	74797	1			T30	1977		T31	1		T24	4
valid_sources[0x26]	67352	1			T30	271		T31	2		T22	2
valid_sources[0x27]	77899	1			T30	1395		T31	1		T22	1
valid_sources[0x28]	87226	1			T30	5327		T31	3		T20	2
valid_sources[0x29]	77781	1			T30	1894		T20	3		T24	5
valid_sources[0x2a]	85687	1			T30	5347		T31	1		T24	6
valid_sources[0x2b]	76501	1			T30	5008		T22	1		T24	6
valid_sources[0x2c]	70749	1			T30	364		T31	2		T20	1
valid_sources[0x2d]	80085	1			T30	668		T20	1		T24	10
valid_sources[0x2e]	69995	1			T30	573		T22	2		T24	5
valid_sources[0x2f]	69080	1			T30	1413		T23	1		T24	2
valid_sources[0x30]	77224	1			T30	835		T31	2		T22	2
valid_sources[0x31]	72638	1			T30	1491		T31	4		T22	2
valid_sources[0x32]	71862	1			T30	553		T24	6		T25	3
valid_sources[0x33]	74747	1			T30	471		T31	3		T22	1
valid_sources[0x34]	68348	1			T30	860		T20	1		T22	1
valid_sources[0x35]	72120	1			T30	1547		T31	1		T20	2
valid_sources[0x36]	74087	1			T30	558		T31	1		T24	5
valid_sources[0x37]	68261	1			T30	238		T31	1		T22	1
valid_sources[0x38]	75942	1			T30	1122		T31	1		T21	9
valid_sources[0x39]	75940	1			T30	220		T31	1		T20	2
valid_sources[0x3a]	68243	1			T30	1565		T24	4		T25	2
valid_sources[0x3b]	75205	1			T30	2118		T31	3		T24	8
valid_sources[0x3c]	74511	1			T30	1613		T20	1		T22	1
valid_sources[0x3d]	72328	1			T30	671		T31	4		T24	4
valid_sources[0x3e]	77016	1			T30	383		T31	1		T22	2
valid_sources[0x3f]	75190	1			T30	462		T22	1		T24	8
valid_sources[0x40]	74031	1			T30	270		T31	1		T20	1
valid_sources[0x41]	75500	1			T30	491		T22	1		T24	3
valid_sources[0x42]	77188	1			T30	648		T31	3		T22	1
valid_sources[0x43]	73569	1			T30	1153		T31	1		T20	1
valid_sources[0x44]	82347	1			T30	1136		T24	6		T25	1
valid_sources[0x45]	72858	1			T30	1057		T24	8		T25	3
valid_sources[0x46]	73928	1			T30	3321		T23	2		T24	9
valid_sources[0x47]	72839	1			T30	270		T22	3		T24	4
valid_sources[0x48]	70226	1			T30	177		T31	2		T22	3
valid_sources[0x49]	80589	1			T30	3257		T31	1		T22	2
valid_sources[0x4a]	76960	1			T30	1590		T24	3		T26	6
valid_sources[0x4b]	73262	1			T30	1752		T22	1		T24	1
valid_sources[0x4c]	72674	1			T30	83		T31	6		T22	1
valid_sources[0x4d]	161662	1			T30	652		T31	2		T24	7
valid_sources[0x4e]	74441	1			T30	587		T31	2		T24	3
valid_sources[0x4f]	70281	1			T30	2196		T24	9		T25	5
valid_sources[0x50]	81776	1			T30	578		T31	2		T22	2
valid_sources[0x51]	65454	1			T30	419		T31	1		T24	9
valid_sources[0x52]	77928	1			T30	2912		T32	268		T24	3
valid_sources[0x53]	71498	1			T30	578		T24	3		T25	5
valid_sources[0x54]	79020	1			T30	2112		T31	5		T22	3
valid_sources[0x55]	67990	1			T30	1156		T20	2		T22	6
valid_sources[0x56]	81276	1			T30	77		T31	3		T22	1
valid_sources[0x57]	161241	1			T30	776		T31	4		T22	2
valid_sources[0x58]	72976	1			T30	337		T31	3		T22	1
valid_sources[0x59]	80423	1			T30	3296		T31	2		T20	2
valid_sources[0x5a]	70883	1			T30	1889		T31	6		T20	5
valid_sources[0x5b]	71741	1			T30	215		T31	3		T22	3
valid_sources[0x5c]	83983	1			T30	573		T20	1		T22	1
valid_sources[0x5d]	74343	1			T30	246		T31	2		T24	6
valid_sources[0x5e]	76165	1			T30	2706		T31	4		T24	5
valid_sources[0x5f]	74667	1			T30	490		T31	1		T24	7
valid_sources[0x60]	70862	1			T30	404		T31	1		T20	1
valid_sources[0x61]	84870	1			T30	208		T31	1		T22	3
valid_sources[0x62]	202658	1			T30	1138		T31	1		T22	2
valid_sources[0x63]	78292	1			T30	2557		T31	3		T24	9
valid_sources[0x64]	74709	1			T30	4024		T31	2		T24	5
valid_sources[0x65]	73435	1			T30	491		T31	1		T22	2
valid_sources[0x66]	75760	1			T30	4033		T31	3		T22	2
valid_sources[0x67]	71686	1			T30	1172		T24	7		T25	1
valid_sources[0x68]	72804	1			T30	680		T31	4		T23	2
valid_sources[0x69]	79323	1			T30	381		T22	1		T23	1
valid_sources[0x6a]	75626	1			T30	93		T31	4		T24	5
valid_sources[0x6b]	72614	1			T30	675		T31	2		T24	3
valid_sources[0x6c]	76509	1			T30	2134		T31	2		T20	1
valid_sources[0x6d]	67420	1			T30	296		T31	1		T24	4
valid_sources[0x6e]	69299	1			T30	567		T31	4		T24	3
valid_sources[0x6f]	68991	1			T30	344		T31	1		T22	1
valid_sources[0x70]	76533	1			T30	446		T31	1		T24	7
valid_sources[0x71]	71607	1			T30	242		T31	1		T22	6
valid_sources[0x72]	77270	1			T30	371		T20	1		T22	1
valid_sources[0x73]	73751	1			T30	2198		T20	1		T24	7
valid_sources[0x74]	71794	1			T30	1120		T22	1		T24	5
valid_sources[0x75]	74600	1			T30	1255		T31	4		T22	1
valid_sources[0x76]	72231	1			T30	349		T31	1		T20	1
valid_sources[0x77]	75267	1			T30	2792		T31	1		T24	11
valid_sources[0x78]	71681	1			T30	294		T31	1		T20	2
valid_sources[0x79]	131635	1			T30	851		T24	2		T25	1
valid_sources[0x7a]	81562	1			T30	1802		T31	1		T20	1
valid_sources[0x7b]	74875	1			T30	772		T31	4		T22	1
valid_sources[0x7c]	69945	1			T30	641		T22	1		T24	4
valid_sources[0x7d]	74319	1			T30	2542		T22	3		T23	1
valid_sources[0x7e]	69779	1			T30	470		T31	7		T20	2
valid_sources[0x7f]	69967	1			T30	1348		T31	3		T24	6
valid_sources[0x80]	75157	1			T30	1377		T31	1		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4576117

1

T30

88721

T31

40

T32

68

values[0x0]

all_enables

biggest_size

5944177

1

T30

117021

T31

132

T32

65

values[0x1]

all_enables

biggest_size

5944611

1

T30

116931

T31

127

T32

83