Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202066655	0	0	0
ctrl_en_input_filter_rd_A	202066655	208824	0	0
intr_ctrl_en_falling_rd_A	202066655	220692	0	0
intr_ctrl_en_lvlhigh_rd_A	202066655	206719	0	0
intr_ctrl_en_lvllow_rd_A	202066655	222176	0	0
intr_ctrl_en_rising_rd_A	202066655	207075	0	0
intr_enable_rd_A	202066655	209400	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	208824	0	0
T1	741963	1969	0	0
T2	0	2294	0	0
T3	0	5234	0	0
T4	0	64	0	0
T5	0	357	0	0
T6	0	300	0	0
T7	0	2503	0	0
T8	0	1174	0	0
T9	0	454	0	0
T10	0	259	0	0
T11	5427	0	0	0
T12	2337	0	0	0
T13	2252	0	0	0
T14	4560	0	0	0
T15	943	0	0	0
T16	1961	0	0	0
T17	3932	0	0	0
T18	4654	0	0	0
T19	6933	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	220692	0	0
T1	0	1865	0	0
T2	0	2214	0	0
T3	0	5580	0	0
T4	0	108	0	0
T5	0	396	0	0
T6	0	257	0	0
T7	0	2677	0	0
T8	0	1182	0	0
T9	0	293	0	0
T20	3821	8	0	0
T21	921	0	0	0
T22	4567	0	0	0
T23	1162	0	0	0
T24	20353	0	0	0
T25	5647	0	0	0
T26	8537	0	0	0
T27	1083	0	0	0
T28	1417	0	0	0
T29	5122	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	206719	0	0
T1	741963	1808	0	0
T2	0	2302	0	0
T3	0	5121	0	0
T4	0	120	0	0
T5	0	442	0	0
T6	0	296	0	0
T7	0	2617	0	0
T8	0	1170	0	0
T9	0	454	0	0
T10	0	333	0	0
T11	5427	0	0	0
T12	2337	0	0	0
T13	2252	0	0	0
T14	4560	0	0	0
T15	943	0	0	0
T16	1961	0	0	0
T17	3932	0	0	0
T18	4654	0	0	0
T19	6933	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	222176	0	0
T1	741963	1935	0	0
T2	0	2080	0	0
T3	0	5359	0	0
T4	0	115	0	0
T5	0	415	0	0
T6	0	316	0	0
T7	0	2694	0	0
T8	0	1251	0	0
T9	0	338	0	0
T10	0	274	0	0
T11	5427	0	0	0
T12	2337	0	0	0
T13	2252	0	0	0
T14	4560	0	0	0
T15	943	0	0	0
T16	1961	0	0	0
T17	3932	0	0	0
T18	4654	0	0	0
T19	6933	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	207075	0	0
T1	741963	1940	0	0
T2	0	2245	0	0
T3	0	5064	0	0
T4	0	106	0	0
T5	0	336	0	0
T6	0	349	0	0
T7	0	2603	0	0
T8	0	1231	0	0
T9	0	401	0	0
T10	0	262	0	0
T11	5427	0	0	0
T12	2337	0	0	0
T13	2252	0	0	0
T14	4560	0	0	0
T15	943	0	0	0
T16	1961	0	0	0
T17	3932	0	0	0
T18	4654	0	0	0
T19	6933	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202066655	209400	0	0
T1	741963	1801	0	0
T2	0	2358	0	0
T3	0	4971	0	0
T4	0	138	0	0
T5	0	451	0	0
T6	0	257	0	0
T7	0	2789	0	0
T8	0	1240	0	0
T9	0	440	0	0
T10	0	283	0	0
T11	5427	0	0	0
T12	2337	0	0	0
T13	2252	0	0	0
T14	4560	0	0	0
T15	943	0	0	0
T16	1961	0	0	0
T17	3932	0	0	0
T18	4654	0	0	0
T19	6933	0	0	0