Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3939809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17966081

1

T20

175

T21

3

T22

174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8666461	1			T20	81		T21	1		T22	173
values[0x0]	6501088	1			T20	63		T21	2		T22	38
values[0x1]	6738341	1			T20	75		T21	2		T22	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3019756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18886134

1

T20

183

T21

3

T22

185

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87992	1			T22	1		T23	5		T24	2
valid_sources[0x01]	89936	1			T22	1		T23	6		T24	1
valid_sources[0x02]	81405	1			T22	3		T23	3		T24	2
valid_sources[0x03]	81225	1			T20	3		T22	3		T23	4
valid_sources[0x04]	78871	1			T22	2		T23	6		T24	5
valid_sources[0x05]	76181	1			T22	2		T23	10		T25	1
valid_sources[0x06]	71123	1			T23	6		T24	5		T26	6
valid_sources[0x07]	80573	1			T22	2		T23	6		T24	5
valid_sources[0x08]	85980	1			T23	4		T24	2		T26	3
valid_sources[0x09]	82610	1			T22	1		T23	9		T24	3
valid_sources[0x0a]	80800	1			T22	2		T23	4		T24	1
valid_sources[0x0b]	72858	1			T23	7		T24	18		T26	7
valid_sources[0x0c]	78839	1			T23	8		T24	1		T26	1
valid_sources[0x0d]	84272	1			T23	13		T24	11		T26	10
valid_sources[0x0e]	82518	1			T22	1		T23	5		T24	5
valid_sources[0x0f]	74573	1			T22	3		T23	3		T24	1
valid_sources[0x10]	73503	1			T20	8		T22	1		T23	10
valid_sources[0x11]	79825	1			T23	9		T24	1		T26	8
valid_sources[0x12]	201523	1			T22	4		T23	6		T24	2
valid_sources[0x13]	68528	1			T22	1		T23	7		T24	1
valid_sources[0x14]	78533	1			T23	4		T24	6		T26	11
valid_sources[0x15]	77550	1			T23	7		T24	3		T26	11
valid_sources[0x16]	79593	1			T23	5		T24	1		T26	6
valid_sources[0x17]	219055	1			T22	1		T23	8		T26	6
valid_sources[0x18]	75415	1			T23	3		T24	1		T26	10
valid_sources[0x19]	72747	1			T23	7		T24	3		T26	4
valid_sources[0x1a]	71748	1			T20	6		T22	4		T23	8
valid_sources[0x1b]	83883	1			T22	8		T23	6		T24	2
valid_sources[0x1c]	87470	1			T20	2		T23	2		T24	6
valid_sources[0x1d]	77106	1			T22	3		T23	2		T24	5
valid_sources[0x1e]	72172	1			T22	1		T23	5		T24	3
valid_sources[0x1f]	77259	1			T22	1		T23	8		T24	3
valid_sources[0x20]	77616	1			T22	1		T23	4		T24	11
valid_sources[0x21]	79010	1			T22	1		T23	2		T24	3
valid_sources[0x22]	74340	1			T20	2		T22	1		T23	5
valid_sources[0x23]	87654	1			T23	5		T24	5		T26	7
valid_sources[0x24]	85991	1			T22	1		T23	3		T24	4
valid_sources[0x25]	76352	1			T23	9		T24	1		T26	9
valid_sources[0x26]	92921	1			T22	3		T23	4		T24	2
valid_sources[0x27]	79581	1			T22	1		T23	8		T24	7
valid_sources[0x28]	73609	1			T20	1		T23	5		T24	5
valid_sources[0x29]	147668	1			T20	5		T22	1		T23	8
valid_sources[0x2a]	79062	1			T22	4		T23	4		T24	5
valid_sources[0x2b]	78913	1			T23	3		T24	5		T26	11
valid_sources[0x2c]	133096	1			T23	5		T24	6		T26	11
valid_sources[0x2d]	81158	1			T23	5		T24	3		T26	11
valid_sources[0x2e]	80074	1			T23	6		T24	1		T26	8
valid_sources[0x2f]	77049	1			T22	1		T23	5		T26	7
valid_sources[0x30]	76522	1			T20	11		T22	6		T23	6
valid_sources[0x31]	80576	1			T22	1		T23	3		T24	1
valid_sources[0x32]	78040	1			T22	1		T23	4		T24	2
valid_sources[0x33]	82122	1			T23	7		T24	2		T26	5
valid_sources[0x34]	75280	1			T23	3		T24	3		T26	4
valid_sources[0x35]	78229	1			T22	2		T23	6		T24	15
valid_sources[0x36]	86836	1			T23	12		T24	4		T26	10
valid_sources[0x37]	83567	1			T20	1		T23	5		T24	3
valid_sources[0x38]	78120	1			T22	5		T23	11		T24	1
valid_sources[0x39]	69007	1			T22	1		T23	9		T24	3
valid_sources[0x3a]	221653	1			T23	2		T24	3		T26	7
valid_sources[0x3b]	81034	1			T22	1		T23	4		T26	8
valid_sources[0x3c]	80362	1			T20	4		T22	2		T23	3
valid_sources[0x3d]	74050	1			T22	3		T23	10		T24	2
valid_sources[0x3e]	84841	1			T22	1		T23	6		T24	3
valid_sources[0x3f]	96370	1			T22	1		T23	5		T24	2
valid_sources[0x40]	73617	1			T20	6		T22	3		T23	5
valid_sources[0x41]	77785	1			T23	5		T24	1		T26	8
valid_sources[0x42]	77402	1			T20	5		T23	3		T24	5
valid_sources[0x43]	75760	1			T23	2		T24	1		T26	3
valid_sources[0x44]	77306	1			T23	7		T24	3		T26	5
valid_sources[0x45]	89188	1			T23	10		T26	8		T30	2727
valid_sources[0x46]	77397	1			T22	2		T23	1		T24	3
valid_sources[0x47]	73320	1			T23	5		T26	7		T30	2885
valid_sources[0x48]	77382	1			T23	5		T24	3		T26	9
valid_sources[0x49]	75447	1			T23	5		T24	1		T26	9
valid_sources[0x4a]	88806	1			T20	2		T23	2		T24	5
valid_sources[0x4b]	86492	1			T23	5		T24	2		T26	5
valid_sources[0x4c]	78378	1			T23	5		T24	8		T26	9
valid_sources[0x4d]	85361	1			T22	1		T23	4		T24	5
valid_sources[0x4e]	90177	1			T23	7		T26	12		T30	2949
valid_sources[0x4f]	223356	1			T23	6		T24	7		T26	4
valid_sources[0x50]	78484	1			T22	2		T23	6		T24	1
valid_sources[0x51]	90353	1			T22	2		T23	10		T24	2
valid_sources[0x52]	75574	1			T22	1		T23	6		T24	2
valid_sources[0x53]	84092	1			T23	4		T26	12		T28	1
valid_sources[0x54]	81996	1			T22	2		T23	10		T24	2
valid_sources[0x55]	73243	1			T22	1		T23	4		T24	1
valid_sources[0x56]	83627	1			T23	3		T24	4		T26	6
valid_sources[0x57]	83803	1			T23	6		T24	2		T26	10
valid_sources[0x58]	79387	1			T23	2		T24	4		T26	8
valid_sources[0x59]	69626	1			T23	3		T24	3		T26	14
valid_sources[0x5a]	213773	1			T22	3		T23	1		T24	1
valid_sources[0x5b]	89755	1			T23	9		T24	2		T26	4
valid_sources[0x5c]	85515	1			T22	1		T23	10		T24	5
valid_sources[0x5d]	83497	1			T22	3		T23	4		T26	9
valid_sources[0x5e]	79008	1			T22	1		T23	5		T24	3
valid_sources[0x5f]	79708	1			T23	5		T24	4		T26	11
valid_sources[0x60]	98686	1			T23	5		T24	3		T26	8
valid_sources[0x61]	68149	1			T20	3		T23	5		T24	3
valid_sources[0x62]	71496	1			T20	1		T23	8		T24	3
valid_sources[0x63]	75283	1			T22	6		T23	6		T24	4
valid_sources[0x64]	78057	1			T20	16		T23	4		T24	5
valid_sources[0x65]	116868	1			T23	3		T24	6		T25	3
valid_sources[0x66]	76706	1			T20	1		T23	4		T24	4
valid_sources[0x67]	80694	1			T22	1		T23	4		T24	3
valid_sources[0x68]	67741	1			T23	7		T24	2		T26	9
valid_sources[0x69]	75322	1			T23	7		T24	4		T26	6
valid_sources[0x6a]	85034	1			T20	2		T22	2		T23	6
valid_sources[0x6b]	76455	1			T23	5		T24	6		T26	5
valid_sources[0x6c]	75854	1			T20	1		T23	8		T26	11
valid_sources[0x6d]	69171	1			T20	4		T22	5		T23	5
valid_sources[0x6e]	77673	1			T23	9		T24	2		T26	9
valid_sources[0x6f]	82839	1			T23	2		T24	4		T25	17
valid_sources[0x70]	88375	1			T22	2		T23	4		T24	4
valid_sources[0x71]	82489	1			T22	3		T23	4		T24	2
valid_sources[0x72]	79766	1			T21	1		T22	2		T23	6
valid_sources[0x73]	80126	1			T23	5		T24	2		T26	1
valid_sources[0x74]	77440	1			T21	1		T22	1		T23	1
valid_sources[0x75]	90725	1			T23	7		T24	3		T26	15
valid_sources[0x76]	65900	1			T22	1		T23	5		T24	5
valid_sources[0x77]	83256	1			T22	1		T23	10		T24	4
valid_sources[0x78]	70356	1			T22	1		T23	7		T24	6
valid_sources[0x79]	86050	1			T23	4		T24	7		T26	4
valid_sources[0x7a]	81454	1			T22	1		T23	4		T26	4
valid_sources[0x7b]	73515	1			T20	1		T23	3		T24	2
valid_sources[0x7c]	77938	1			T23	13		T24	3		T26	3
valid_sources[0x7d]	86496	1			T22	1		T23	9		T24	3
valid_sources[0x7e]	77736	1			T22	1		T23	5		T24	4
valid_sources[0x7f]	84110	1			T20	5		T22	1		T23	6
valid_sources[0x80]	79257	1			T22	1		T23	9		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5011185

1

T20

37

T21

1

T22

94

values[0x0]

all_enables

biggest_size

6477410

1

T20

63

T21

1

T22

38

values[0x1]

all_enables

biggest_size

6477486

1

T20

75

T21

1

T22

42