Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	184733449	0	0	0
ctrl_en_input_filter_rd_A	184733449	118704	0	0
intr_ctrl_en_falling_rd_A	184733449	125410	0	0
intr_ctrl_en_lvlhigh_rd_A	184733449	120378	0	0
intr_ctrl_en_lvllow_rd_A	184733449	125307	0	0
intr_ctrl_en_rising_rd_A	184733449	119737	0	0
intr_enable_rd_A	184733449	119646	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	118704	0	0
T1	51417	404	0	0
T2	185132	7324	0	0
T3	54368	400	0	0
T4	0	877	0	0
T5	0	1	0	0
T6	0	4	0	0
T7	0	201	0	0
T8	0	3502	0	0
T9	0	30	0	0
T10	0	1494	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	125410	0	0
T1	51417	332	0	0
T2	185132	7338	0	0
T3	54368	332	0	0
T4	0	954	0	0
T7	0	201	0	0
T8	0	3571	0	0
T9	0	11	0	0
T10	0	1481	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0
T18	0	102	0	0
T19	0	3998	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	120378	0	0
T1	51417	288	0	0
T2	185132	6973	0	0
T3	54368	422	0	0
T4	0	792	0	0
T5	0	4	0	0
T6	0	15	0	0
T7	0	169	0	0
T8	0	3670	0	0
T9	0	12	0	0
T10	0	1605	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	125307	0	0
T1	51417	353	0	0
T2	185132	7602	0	0
T3	54368	405	0	0
T4	0	762	0	0
T5	0	4	0	0
T7	0	118	0	0
T8	0	3834	0	0
T9	0	16	0	0
T10	0	1528	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0
T18	0	96	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	119737	0	0
T1	51417	258	0	0
T2	185132	7007	0	0
T3	54368	373	0	0
T4	0	747	0	0
T5	0	5	0	0
T7	0	190	0	0
T8	0	3360	0	0
T9	0	21	0	0
T10	0	1488	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0
T18	0	104	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184733449	119646	0	0
T1	51417	366	0	0
T2	185132	7407	0	0
T3	54368	421	0	0
T4	0	800	0	0
T7	0	155	0	0
T8	0	3578	0	0
T9	0	33	0	0
T10	0	1492	0	0
T11	4410	0	0	0
T12	6394	0	0	0
T13	10383	0	0	0
T14	5697	0	0	0
T15	7837	0	0	0
T16	6762	0	0	0
T17	2694	0	0	0
T18	0	91	0	0
T19	0	3947	0	0