Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2683278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11582568

1

T20

107

T21

2003

T22

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5805613	1			T20	63		T21	3102		T22	1
values[0x0]	4164525	1			T20	36		T21	215		T22	6
values[0x1]	4295708	1			T20	32		T21	240		T22	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2071465	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12194381

1

T20

113

T21

2308

T22

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57676	1			T21	22		T23	1		T25	13
valid_sources[0x01]	44193	1			T21	10		T23	1		T25	11
valid_sources[0x02]	51695	1			T21	35		T25	11		T28	13
valid_sources[0x03]	51549	1			T21	21		T23	2		T25	6
valid_sources[0x04]	58749	1			T21	10		T24	6		T25	6
valid_sources[0x05]	51266	1			T21	15		T25	8		T27	4
valid_sources[0x06]	51393	1			T21	5		T25	13		T27	1
valid_sources[0x07]	49957	1			T21	12		T25	7		T28	11
valid_sources[0x08]	57072	1			T21	12		T23	1		T25	6
valid_sources[0x09]	50953	1			T21	15		T25	3		T27	1
valid_sources[0x0a]	56428	1			T21	14		T23	1		T24	3
valid_sources[0x0b]	50508	1			T21	9		T24	4		T25	5
valid_sources[0x0c]	51195	1			T21	19		T24	23		T25	13
valid_sources[0x0d]	50357	1			T21	21		T24	4		T25	8
valid_sources[0x0e]	45833	1			T21	20		T25	4		T27	1
valid_sources[0x0f]	52077	1			T21	29		T22	1		T24	3
valid_sources[0x10]	53742	1			T21	12		T24	3		T25	14
valid_sources[0x11]	56244	1			T21	21		T23	1		T25	7
valid_sources[0x12]	49413	1			T21	18		T25	17		T27	1
valid_sources[0x13]	53165	1			T21	8		T24	5		T25	14
valid_sources[0x14]	60951	1			T21	25		T25	12		T29	1
valid_sources[0x15]	51694	1			T21	11		T25	13		T27	2
valid_sources[0x16]	47059	1			T21	13		T25	11		T27	1
valid_sources[0x17]	50107	1			T21	12		T23	2		T25	9
valid_sources[0x18]	56425	1			T21	17		T25	9		T28	22
valid_sources[0x19]	55969	1			T21	15		T23	1		T24	5
valid_sources[0x1a]	57793	1			T21	17		T25	7		T27	1
valid_sources[0x1b]	58902	1			T21	6		T25	12		T27	1
valid_sources[0x1c]	54910	1			T21	24		T24	2		T25	4
valid_sources[0x1d]	49734	1			T21	12		T23	1		T25	12
valid_sources[0x1e]	49078	1			T21	11		T25	9		T27	1
valid_sources[0x1f]	52699	1			T21	12		T23	3		T25	12
valid_sources[0x20]	54060	1			T21	20		T23	3		T25	7
valid_sources[0x21]	48867	1			T21	11		T25	15		T27	2
valid_sources[0x22]	52605	1			T21	18		T25	7		T29	2
valid_sources[0x23]	51446	1			T21	10		T25	8		T28	3
valid_sources[0x24]	55764	1			T21	9		T23	4		T25	3
valid_sources[0x25]	102251	1			T21	16		T25	8		T27	1
valid_sources[0x26]	50539	1			T21	5		T25	7		T29	1
valid_sources[0x27]	49692	1			T21	25		T25	7		T27	1
valid_sources[0x28]	52449	1			T21	12		T25	4		T111	3
valid_sources[0x29]	53443	1			T21	11		T25	19		T27	2
valid_sources[0x2a]	51513	1			T21	7		T25	18		T27	2
valid_sources[0x2b]	47745	1			T21	11		T22	3		T23	2
valid_sources[0x2c]	48697	1			T21	20		T25	7		T113	1
valid_sources[0x2d]	52314	1			T21	18		T24	1		T25	13
valid_sources[0x2e]	46669	1			T21	17		T23	2		T25	10
valid_sources[0x2f]	48341	1			T21	9		T22	1		T25	10
valid_sources[0x30]	51511	1			T21	17		T25	13		T111	2
valid_sources[0x31]	52659	1			T21	14		T25	11		T27	4
valid_sources[0x32]	49193	1			T21	13		T25	7		T28	8
valid_sources[0x33]	50381	1			T21	4		T25	17		T28	3
valid_sources[0x34]	51768	1			T21	9		T25	11		T37	2
valid_sources[0x35]	54731	1			T21	6		T25	12		T27	1
valid_sources[0x36]	54758	1			T21	13		T25	3		T27	1
valid_sources[0x37]	48724	1			T21	13		T25	5		T27	1
valid_sources[0x38]	45960	1			T21	21		T24	12		T25	10
valid_sources[0x39]	51479	1			T21	12		T25	10		T27	1
valid_sources[0x3a]	48795	1			T21	16		T23	1		T25	9
valid_sources[0x3b]	54516	1			T21	13		T25	12		T28	8
valid_sources[0x3c]	49746	1			T21	11		T25	10		T27	3
valid_sources[0x3d]	136949	1			T21	11		T23	6		T24	1
valid_sources[0x3e]	50901	1			T21	18		T24	5		T25	4
valid_sources[0x3f]	55767	1			T21	13		T25	10		T27	1
valid_sources[0x40]	51860	1			T21	3		T24	12		T25	4
valid_sources[0x41]	47523	1			T21	11		T25	8		T27	1
valid_sources[0x42]	50201	1			T21	8		T23	2		T25	15
valid_sources[0x43]	53358	1			T21	30		T23	1		T25	9
valid_sources[0x44]	51283	1			T21	17		T24	29		T25	10
valid_sources[0x45]	56851	1			T21	14		T25	10		T27	3
valid_sources[0x46]	45530	1			T21	26		T25	1		T27	1
valid_sources[0x47]	54520	1			T21	10		T23	1		T25	8
valid_sources[0x48]	52613	1			T21	18		T23	1		T25	11
valid_sources[0x49]	54706	1			T21	15		T25	14		T27	2
valid_sources[0x4a]	57020	1			T21	12		T24	2		T25	7
valid_sources[0x4b]	48836	1			T21	15		T24	2		T25	10
valid_sources[0x4c]	50993	1			T21	27		T23	2		T25	9
valid_sources[0x4d]	56104	1			T21	15		T25	10		T27	1
valid_sources[0x4e]	49425	1			T21	17		T25	6		T28	1
valid_sources[0x4f]	49934	1			T21	7		T23	1		T25	14
valid_sources[0x50]	47310	1			T21	12		T25	8		T27	1
valid_sources[0x51]	57303	1			T21	18		T25	7		T27	1
valid_sources[0x52]	48502	1			T21	35		T23	1		T24	5
valid_sources[0x53]	53165	1			T21	14		T24	4		T25	6
valid_sources[0x54]	45960	1			T21	24		T25	11		T27	1
valid_sources[0x55]	56400	1			T21	17		T22	5		T25	8
valid_sources[0x56]	58237	1			T21	15		T23	2		T24	5
valid_sources[0x57]	52183	1			T21	17		T23	1		T25	2
valid_sources[0x58]	52808	1			T21	12		T23	1		T25	12
valid_sources[0x59]	50998	1			T21	5		T25	7		T27	2
valid_sources[0x5a]	50740	1			T21	21		T25	12		T27	1
valid_sources[0x5b]	54389	1			T21	10		T23	1		T24	1
valid_sources[0x5c]	54491	1			T21	8		T23	2		T25	7
valid_sources[0x5d]	50298	1			T21	15		T25	17		T27	1
valid_sources[0x5e]	55970	1			T21	10		T25	8		T27	1
valid_sources[0x5f]	47204	1			T21	2		T24	5		T25	10
valid_sources[0x60]	51636	1			T21	18		T23	2		T25	9
valid_sources[0x61]	52809	1			T21	12		T25	10		T27	1
valid_sources[0x62]	49619	1			T21	1		T25	6		T27	2
valid_sources[0x63]	57474	1			T21	17		T25	9		T27	3
valid_sources[0x64]	50031	1			T21	16		T24	4		T25	7
valid_sources[0x65]	47858	1			T21	10		T25	11		T27	1
valid_sources[0x66]	48973	1			T21	11		T23	1		T25	5
valid_sources[0x67]	58167	1			T20	131		T21	11		T25	18
valid_sources[0x68]	52164	1			T21	5		T25	15		T27	2
valid_sources[0x69]	48682	1			T21	14		T24	2		T25	7
valid_sources[0x6a]	52749	1			T21	14		T24	10		T25	21
valid_sources[0x6b]	54683	1			T21	9		T24	10		T25	15
valid_sources[0x6c]	54856	1			T21	10		T25	10		T28	1
valid_sources[0x6d]	56536	1			T21	19		T25	14		T27	1
valid_sources[0x6e]	48145	1			T21	6		T25	4		T28	8
valid_sources[0x6f]	50729	1			T21	13		T25	11		T27	1
valid_sources[0x70]	219150	1			T21	9		T25	7		T27	4
valid_sources[0x71]	53445	1			T21	13		T25	14		T27	3
valid_sources[0x72]	48422	1			T21	8		T23	1		T25	15
valid_sources[0x73]	46835	1			T21	11		T24	17		T25	9
valid_sources[0x74]	48260	1			T21	13		T23	6		T25	8
valid_sources[0x75]	48129	1			T21	15		T23	1		T27	2
valid_sources[0x76]	117470	1			T21	7		T24	4		T25	11
valid_sources[0x77]	55131	1			T21	23		T25	3		T28	13
valid_sources[0x78]	46254	1			T21	20		T25	4		T27	1
valid_sources[0x79]	53710	1			T21	8		T24	11		T25	8
valid_sources[0x7a]	48028	1			T21	9		T24	8		T25	15
valid_sources[0x7b]	123165	1			T21	19		T23	1		T25	17
valid_sources[0x7c]	47523	1			T21	16		T25	12		T29	1
valid_sources[0x7d]	50419	1			T21	15		T23	2		T24	4
valid_sources[0x7e]	50752	1			T21	12		T25	3		T27	1
valid_sources[0x7f]	49398	1			T21	14		T25	7		T27	2
valid_sources[0x80]	52639	1			T21	8		T23	2		T25	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3284228

1

T20

39

T21

1548

T22

1

values[0x0]

all_enables

biggest_size

4150509

1

T20

36

T21

215

T22

2

values[0x1]

all_enables

biggest_size

4147831

1

T20

32

T21

240

T22

2