Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	126169313	0	0	0
ctrl_en_input_filter_rd_A	126169313	107439	0	0
intr_ctrl_en_falling_rd_A	126169313	110250	0	0
intr_ctrl_en_lvlhigh_rd_A	126169313	108276	0	0
intr_ctrl_en_lvllow_rd_A	126169313	110685	0	0
intr_ctrl_en_rising_rd_A	126169313	108526	0	0
intr_enable_rd_A	126169313	107864	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	107439	0	0
T1	181336	5606	0	0
T2	4897	2	0	0
T3	5806	52	0	0
T4	18648	122	0	0
T5	0	4059	0	0
T6	0	286	0	0
T7	0	1259	0	0
T8	0	4172	0	0
T9	0	2	0	0
T10	0	173	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	110250	0	0
T1	181336	5399	0	0
T2	4897	2	0	0
T3	5806	29	0	0
T4	18648	111	0	0
T5	0	4249	0	0
T6	0	326	0	0
T7	0	1602	0	0
T8	0	4384	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	2	0	0
T17	0	2	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	108276	0	0
T1	181336	5684	0	0
T2	4897	7	0	0
T3	5806	15	0	0
T4	18648	113	0	0
T5	0	4189	0	0
T6	0	242	0	0
T7	0	1502	0	0
T8	0	4293	0	0
T10	0	119	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	110685	0	0
T1	181336	5481	0	0
T2	4897	0	0	0
T3	5806	40	0	0
T4	18648	103	0	0
T5	0	4130	0	0
T6	0	353	0	0
T7	0	1492	0	0
T8	0	4318	0	0
T9	0	4	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	4	0	0
T18	0	8	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	108526	0	0
T1	181336	5810	0	0
T2	4897	0	0	0
T3	5806	20	0	0
T4	18648	155	0	0
T5	0	4094	0	0
T6	0	325	0	0
T7	0	1354	0	0
T8	0	4571	0	0
T10	0	133	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	5	0	0
T19	0	112	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126169313	107864	0	0
T1	181336	5602	0	0
T2	4897	0	0	0
T3	5806	30	0	0
T4	18648	97	0	0
T5	0	4025	0	0
T6	0	315	0	0
T7	0	1382	0	0
T8	0	4458	0	0
T9	0	9	0	0
T10	0	230	0	0
T11	4473	0	0	0
T12	21190	0	0	0
T13	924030	0	0	0
T14	1671	0	0	0
T15	6379	0	0	0
T16	8415	5	0	0