Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3391703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15008106

1

T22

38

T23

569

T24

290

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7373607	1			T22	22		T23	693		T24	160
values[0x0]	5422826	1			T22	15		T23	116		T24	111
values[0x1]	5603376	1			T22	12		T23	109		T24	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2613817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15785992

1

T22

40

T23

636

T24

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68131	1			T23	1		T25	4801		T11	1
valid_sources[0x01]	66447	1			T23	2		T25	4742		T12	7
valid_sources[0x02]	69556	1			T23	3		T25	4929		T12	6
valid_sources[0x03]	75399	1			T25	4984		T12	6		T15	101
valid_sources[0x04]	69869	1			T23	1		T24	1		T25	4900
valid_sources[0x05]	65687	1			T23	5		T25	5259		T11	1
valid_sources[0x06]	72376	1			T23	4		T25	4643		T12	7
valid_sources[0x07]	62543	1			T23	7		T25	5082		T12	6
valid_sources[0x08]	71591	1			T23	1		T25	4994		T12	7
valid_sources[0x09]	65536	1			T23	1		T25	5133		T12	11
valid_sources[0x0a]	69297	1			T23	14		T25	5052		T12	11
valid_sources[0x0b]	69454	1			T24	2		T25	5071		T12	10
valid_sources[0x0c]	70973	1			T23	4		T25	4777		T11	1
valid_sources[0x0d]	75503	1			T23	9		T25	5171		T12	9
valid_sources[0x0e]	93442	1			T23	4		T24	2		T25	4693
valid_sources[0x0f]	73191	1			T23	1		T24	1		T25	5056
valid_sources[0x10]	68837	1			T23	4		T25	4970		T12	6
valid_sources[0x11]	74457	1			T25	5043		T12	2		T15	107
valid_sources[0x12]	70186	1			T23	9		T25	5283		T12	8
valid_sources[0x13]	70206	1			T23	4		T24	2		T25	4684
valid_sources[0x14]	71568	1			T23	5		T24	2		T25	5009
valid_sources[0x15]	75991	1			T23	3		T25	4870		T12	6
valid_sources[0x16]	70957	1			T25	4943		T12	8		T13	30
valid_sources[0x17]	69643	1			T23	3		T25	4771		T12	5
valid_sources[0x18]	66929	1			T23	6		T24	2		T25	5250
valid_sources[0x19]	63154	1			T23	5		T24	3		T25	4675
valid_sources[0x1a]	76497	1			T23	4		T24	6		T25	5174
valid_sources[0x1b]	68767	1			T23	2		T25	4791		T12	10
valid_sources[0x1c]	77738	1			T23	1		T25	4788		T12	6
valid_sources[0x1d]	65581	1			T23	3		T24	5		T25	4790
valid_sources[0x1e]	67928	1			T24	6		T25	4979		T12	3
valid_sources[0x1f]	71465	1			T23	2		T25	4985		T12	13
valid_sources[0x20]	72614	1			T23	4		T25	5091		T12	9
valid_sources[0x21]	69695	1			T23	3		T24	4		T25	5324
valid_sources[0x22]	63463	1			T23	1		T24	6		T25	5132
valid_sources[0x23]	75303	1			T23	5		T25	4851		T12	11
valid_sources[0x24]	72278	1			T23	2		T24	3		T25	4855
valid_sources[0x25]	72257	1			T23	1		T25	4715		T12	8
valid_sources[0x26]	68482	1			T23	3		T24	1		T25	4915
valid_sources[0x27]	71695	1			T23	2		T24	5		T25	4814
valid_sources[0x28]	61007	1			T23	3		T24	3		T25	4970
valid_sources[0x29]	70580	1			T23	7		T24	4		T25	4759
valid_sources[0x2a]	93714	1			T23	12		T24	5		T25	4680
valid_sources[0x2b]	72883	1			T23	7		T25	5265		T12	12
valid_sources[0x2c]	75183	1			T23	4		T24	1		T25	5222
valid_sources[0x2d]	68468	1			T25	4548		T11	2		T12	9
valid_sources[0x2e]	66017	1			T23	13		T25	5019		T11	1
valid_sources[0x2f]	74224	1			T25	4775		T11	2		T12	8
valid_sources[0x30]	78571	1			T23	1		T24	3		T25	4703
valid_sources[0x31]	65913	1			T23	1		T25	4931		T11	1
valid_sources[0x32]	65748	1			T23	3		T24	1		T25	4948
valid_sources[0x33]	89544	1			T23	3		T25	4747		T12	8
valid_sources[0x34]	77959	1			T23	1		T25	4959		T11	2
valid_sources[0x35]	72865	1			T23	3		T24	5		T25	5140
valid_sources[0x36]	64541	1			T23	6		T25	4788		T12	8
valid_sources[0x37]	71908	1			T23	5		T24	1		T25	4728
valid_sources[0x38]	71043	1			T23	4		T25	5171		T12	12
valid_sources[0x39]	72034	1			T23	2		T25	4961		T12	7
valid_sources[0x3a]	67272	1			T24	4		T25	4823		T12	10
valid_sources[0x3b]	79879	1			T25	4887		T11	1		T12	11
valid_sources[0x3c]	63145	1			T23	4		T24	4		T25	4870
valid_sources[0x3d]	67653	1			T23	1		T24	1		T25	4804
valid_sources[0x3e]	69888	1			T23	9		T24	17		T25	4952
valid_sources[0x3f]	70933	1			T23	13		T25	4651		T12	11
valid_sources[0x40]	63272	1			T23	4		T25	4848		T12	9
valid_sources[0x41]	61727	1			T23	6		T25	4723		T12	7
valid_sources[0x42]	70319	1			T23	5		T24	1		T25	5006
valid_sources[0x43]	63587	1			T23	9		T25	4927		T11	2
valid_sources[0x44]	78071	1			T23	4		T24	2		T25	4960
valid_sources[0x45]	72114	1			T23	8		T24	2		T25	4819
valid_sources[0x46]	63970	1			T25	4817		T11	1		T12	12
valid_sources[0x47]	69283	1			T23	8		T25	4808		T12	7
valid_sources[0x48]	69421	1			T23	11		T25	4818		T12	13
valid_sources[0x49]	69360	1			T23	3		T24	4		T25	4561
valid_sources[0x4a]	73833	1			T23	2		T25	4777		T12	7
valid_sources[0x4b]	69817	1			T22	49		T24	3		T25	5020
valid_sources[0x4c]	73258	1			T23	2		T25	5341		T11	1
valid_sources[0x4d]	62796	1			T25	5053		T12	6		T15	123
valid_sources[0x4e]	64454	1			T23	5		T25	4790		T12	13
valid_sources[0x4f]	73665	1			T25	4861		T12	4		T15	149
valid_sources[0x50]	66703	1			T23	2		T25	5170		T11	1
valid_sources[0x51]	70859	1			T25	4685		T12	8		T15	63
valid_sources[0x52]	72610	1			T23	3		T25	5020		T12	5
valid_sources[0x53]	65804	1			T23	2		T25	4894		T12	9
valid_sources[0x54]	69796	1			T23	14		T24	2		T25	4849
valid_sources[0x55]	70618	1			T25	5283		T11	1		T12	9
valid_sources[0x56]	72634	1			T23	2		T25	5128		T12	15
valid_sources[0x57]	71865	1			T23	1		T24	3		T25	4863
valid_sources[0x58]	61840	1			T24	7		T25	4918		T12	5
valid_sources[0x59]	69727	1			T23	2		T25	4918		T11	1
valid_sources[0x5a]	67177	1			T25	4947		T12	7		T15	117
valid_sources[0x5b]	79214	1			T24	8		T25	4992		T12	9
valid_sources[0x5c]	72184	1			T23	1		T25	4856		T12	10
valid_sources[0x5d]	69681	1			T23	3		T24	2		T25	4971
valid_sources[0x5e]	75611	1			T23	4		T24	3		T25	4860
valid_sources[0x5f]	70493	1			T24	2		T25	5202		T12	13
valid_sources[0x60]	191637	1			T23	2		T25	4826		T12	10
valid_sources[0x61]	78188	1			T23	4		T24	3		T25	4887
valid_sources[0x62]	72481	1			T23	13		T24	7		T25	5111
valid_sources[0x63]	70593	1			T23	2		T25	4871		T12	6
valid_sources[0x64]	78450	1			T23	3		T25	4777		T12	14
valid_sources[0x65]	70314	1			T23	3		T24	1		T25	4796
valid_sources[0x66]	71823	1			T23	5		T25	4687		T12	6
valid_sources[0x67]	66496	1			T23	1		T24	1		T25	4673
valid_sources[0x68]	68972	1			T23	5		T24	6		T25	4728
valid_sources[0x69]	76067	1			T23	1		T25	4980		T12	9
valid_sources[0x6a]	75506	1			T23	6		T24	1		T25	4952
valid_sources[0x6b]	65821	1			T23	6		T25	4638		T12	7
valid_sources[0x6c]	71182	1			T23	1		T25	4961		T12	5
valid_sources[0x6d]	69620	1			T23	13		T24	2		T25	5092
valid_sources[0x6e]	71456	1			T23	4		T25	4740		T12	9
valid_sources[0x6f]	72245	1			T23	3		T24	2		T25	4893
valid_sources[0x70]	65058	1			T23	2		T24	1		T25	4894
valid_sources[0x71]	65337	1			T23	1		T24	3		T25	5154
valid_sources[0x72]	69182	1			T24	1		T25	5109		T12	14
valid_sources[0x73]	69544	1			T25	4694		T12	15		T15	59
valid_sources[0x74]	69122	1			T23	9		T24	2		T25	4761
valid_sources[0x75]	67202	1			T23	4		T25	4635		T12	8
valid_sources[0x76]	70581	1			T23	2		T25	4968		T12	8
valid_sources[0x77]	64590	1			T25	4682		T12	6		T15	78
valid_sources[0x78]	69060	1			T23	4		T24	3		T25	4931
valid_sources[0x79]	76492	1			T25	4891		T11	1		T12	4
valid_sources[0x7a]	74410	1			T25	5116		T12	10		T15	189
valid_sources[0x7b]	69734	1			T25	4700		T12	6		T15	65
valid_sources[0x7c]	65819	1			T23	2		T25	4831		T12	9
valid_sources[0x7d]	71636	1			T23	1		T25	4969		T12	5
valid_sources[0x7e]	66393	1			T23	4		T25	4936		T26	46
valid_sources[0x7f]	66933	1			T23	1		T25	5007		T12	6
valid_sources[0x80]	66650	1			T23	3		T25	4960		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4199311

1

T22

11

T23

344

T24

85

values[0x0]

all_enables

biggest_size

5404273

1

T22

15

T23

116

T24

111

values[0x1]

all_enables

biggest_size

5404522

1

T22

12

T23

109

T24

94