Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149049976	0	0	0
ctrl_en_input_filter_rd_A	149049976	100506	0	0
intr_ctrl_en_falling_rd_A	149049976	104270	0	0
intr_ctrl_en_lvlhigh_rd_A	149049976	100168	0	0
intr_ctrl_en_lvllow_rd_A	149049976	106992	0	0
intr_ctrl_en_rising_rd_A	149049976	100483	0	0
intr_enable_rd_A	149049976	98682	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	100506	0	0
T1	21208	142	0	0
T2	705285	1753	0	0
T3	0	12946	0	0
T4	0	147	0	0
T5	0	117	0	0
T6	0	263	0	0
T7	0	303	0	0
T8	0	6952	0	0
T9	0	65	0	0
T10	0	1	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	104270	0	0
T1	21208	221	0	0
T2	705285	1904	0	0
T3	0	13996	0	0
T4	0	148	0	0
T5	0	87	0	0
T6	0	272	0	0
T7	0	260	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0
T19	0	4	0	0
T20	0	3	0	0
T21	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	100168	0	0
T1	21208	134	0	0
T2	705285	1912	0	0
T3	0	13162	0	0
T4	0	177	0	0
T5	0	89	0	0
T6	0	294	0	0
T7	0	292	0	0
T8	0	6853	0	0
T9	0	108	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0
T19	0	9	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	106992	0	0
T1	21208	139	0	0
T2	705285	1757	0	0
T3	0	14473	0	0
T4	0	198	0	0
T5	0	147	0	0
T6	0	304	0	0
T7	0	273	0	0
T8	0	6986	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0
T19	0	5	0	0
T20	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	100483	0	0
T1	21208	116	0	0
T2	705285	1943	0	0
T3	0	13341	0	0
T4	0	121	0	0
T5	0	114	0	0
T6	0	376	0	0
T7	0	278	0	0
T8	0	6906	0	0
T9	0	89	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0
T20	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149049976	98682	0	0
T1	21208	134	0	0
T2	705285	1760	0	0
T3	0	13064	0	0
T4	0	106	0	0
T5	0	131	0	0
T6	0	349	0	0
T7	0	315	0	0
T8	0	6847	0	0
T11	1853	0	0	0
T12	30316	0	0	0
T13	4700	0	0	0
T14	4554	0	0	0
T15	260067	0	0	0
T16	3916	0	0	0
T17	9269	0	0	0
T18	6632	0	0	0
T19	0	10	0	0
T20	0	4	0	0