Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207086113	0	0	0
ctrl_en_input_filter_rd_A	207086113	59183	0	0
intr_ctrl_en_falling_rd_A	207086113	60653	0	0
intr_ctrl_en_lvlhigh_rd_A	207086113	59354	0	0
intr_ctrl_en_lvllow_rd_A	207086113	59492	0	0
intr_ctrl_en_rising_rd_A	207086113	59539	0	0
intr_enable_rd_A	207086113	58922	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	59183	0	0
T1	9079	20	0	0
T2	0	3355	0	0
T3	0	6	0	0
T4	0	66	0	0
T5	0	4424	0	0
T6	0	327	0	0
T7	0	816	0	0
T8	0	175	0	0
T9	0	224	0	0
T10	0	6776	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	60653	0	0
T1	9079	40	0	0
T2	0	3291	0	0
T3	0	3	0	0
T4	0	95	0	0
T5	0	4530	0	0
T6	0	270	0	0
T7	0	762	0	0
T8	0	228	0	0
T9	0	222	0	0
T10	0	6850	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	59354	0	0
T1	9079	41	0	0
T2	0	3249	0	0
T4	0	63	0	0
T5	0	4521	0	0
T6	0	261	0	0
T7	0	777	0	0
T8	0	212	0	0
T9	0	276	0	0
T10	0	6822	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0
T20	0	9	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	59492	0	0
T1	9079	58	0	0
T2	0	3192	0	0
T4	0	77	0	0
T5	0	4569	0	0
T6	0	285	0	0
T7	0	808	0	0
T8	0	158	0	0
T9	0	262	0	0
T10	0	6931	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0
T21	0	8	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	59539	0	0
T1	9079	71	0	0
T2	0	3159	0	0
T3	0	7	0	0
T4	0	63	0	0
T5	0	4493	0	0
T6	0	335	0	0
T7	0	794	0	0
T8	0	153	0	0
T9	0	295	0	0
T10	0	6885	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207086113	58922	0	0
T1	9079	36	0	0
T2	0	3237	0	0
T3	0	7	0	0
T4	0	101	0	0
T5	0	4321	0	0
T6	0	349	0	0
T7	0	755	0	0
T8	0	144	0	0
T9	0	398	0	0
T10	0	6567	0	0
T11	4696	0	0	0
T12	1521	0	0	0
T13	1558	0	0	0
T14	50071	0	0	0
T15	1925	0	0	0
T16	1083	0	0	0
T17	6764	0	0	0
T18	8775	0	0	0
T19	3279	0	0	0