Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3521944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15816227

1

T21

152

T24

5

T25

1310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7694777	1			T21	7		T24	1		T25	1990
values[0x0]	5726214	1			T21	84		T24	10		T25	163
values[0x1]	5917180	1			T21	65		T24	10		T25	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2706363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16631808

1

T21

154

T24

6

T25

1505

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	72732	1			T25	16		T1	4		T12	6169
valid_sources[0x01]	71578	1			T25	8		T1	7		T12	6748
valid_sources[0x02]	69214	1			T21	3		T25	9		T11	1
valid_sources[0x03]	77387	1			T21	1		T25	7		T11	3
valid_sources[0x04]	70517	1			T25	11		T12	5900		T13	659
valid_sources[0x05]	73488	1			T21	2		T25	14		T11	1
valid_sources[0x06]	70954	1			T25	7		T11	1		T12	5364
valid_sources[0x07]	80649	1			T21	1		T25	9		T12	5654
valid_sources[0x08]	71315	1			T25	8		T12	5815		T13	686
valid_sources[0x09]	72240	1			T24	1		T25	10		T11	1
valid_sources[0x0a]	70796	1			T24	1		T25	7		T11	10
valid_sources[0x0b]	77978	1			T21	1		T25	12		T12	6170
valid_sources[0x0c]	70169	1			T25	9		T11	1		T12	6677
valid_sources[0x0d]	83088	1			T25	8		T12	5841		T13	742
valid_sources[0x0e]	67793	1			T21	1		T25	8		T12	5710
valid_sources[0x0f]	70794	1			T21	3		T25	14		T1	2
valid_sources[0x10]	73395	1			T25	13		T11	3		T12	5128
valid_sources[0x11]	76832	1			T25	6		T1	11		T11	3
valid_sources[0x12]	76312	1			T21	1		T25	10		T11	3
valid_sources[0x13]	224842	1			T25	8		T12	5673		T13	678
valid_sources[0x14]	206807	1			T25	8		T11	1		T12	4806
valid_sources[0x15]	72844	1			T21	2		T25	11		T11	4
valid_sources[0x16]	69825	1			T25	16		T11	2		T12	6034
valid_sources[0x17]	71509	1			T24	1		T25	10		T11	1
valid_sources[0x18]	70290	1			T25	10		T11	1		T12	6327
valid_sources[0x19]	72702	1			T21	2		T25	13		T11	3
valid_sources[0x1a]	72615	1			T21	1		T25	9		T11	3
valid_sources[0x1b]	71052	1			T21	1		T25	10		T11	3
valid_sources[0x1c]	75551	1			T25	7		T11	2		T12	5871
valid_sources[0x1d]	147663	1			T21	1		T25	6		T11	4
valid_sources[0x1e]	69195	1			T25	4		T12	5645		T13	629
valid_sources[0x1f]	72061	1			T21	1		T24	1		T25	10
valid_sources[0x20]	69721	1			T25	14		T12	7008		T13	684
valid_sources[0x21]	68532	1			T25	8		T12	5944		T13	584
valid_sources[0x22]	81621	1			T21	1		T25	6		T11	1
valid_sources[0x23]	72178	1			T25	5		T11	4		T12	6032
valid_sources[0x24]	66875	1			T21	1		T25	6		T12	5760
valid_sources[0x25]	71037	1			T25	6		T11	1		T12	5145
valid_sources[0x26]	73600	1			T21	2		T24	2		T25	9
valid_sources[0x27]	72042	1			T25	5		T11	5		T12	5745
valid_sources[0x28]	75624	1			T25	8		T11	1		T12	6312
valid_sources[0x29]	71128	1			T25	10		T11	5		T12	6399
valid_sources[0x2a]	72512	1			T21	2		T25	10		T11	1
valid_sources[0x2b]	70964	1			T25	3		T11	3		T12	5990
valid_sources[0x2c]	69576	1			T25	9		T11	3		T12	5815
valid_sources[0x2d]	75589	1			T24	1		T25	9		T12	6579
valid_sources[0x2e]	147875	1			T21	1		T25	3		T11	4
valid_sources[0x2f]	78094	1			T25	10		T1	2		T11	1
valid_sources[0x30]	70587	1			T21	1		T25	14		T11	2
valid_sources[0x31]	164801	1			T21	2		T25	3		T11	2
valid_sources[0x32]	69637	1			T21	2		T25	4		T11	1
valid_sources[0x33]	74285	1			T21	1		T24	1		T25	10
valid_sources[0x34]	72371	1			T25	10		T11	1		T12	5642
valid_sources[0x35]	71264	1			T25	9		T12	5685		T13	652
valid_sources[0x36]	78624	1			T21	2		T25	13		T11	1
valid_sources[0x37]	67211	1			T25	6		T11	4		T12	6029
valid_sources[0x38]	73956	1			T25	10		T11	2		T12	6612
valid_sources[0x39]	74318	1			T25	14		T1	7		T11	1
valid_sources[0x3a]	70750	1			T21	2		T25	13		T1	2
valid_sources[0x3b]	69516	1			T21	2		T25	8		T1	14
valid_sources[0x3c]	75339	1			T21	1		T25	7		T1	3
valid_sources[0x3d]	73827	1			T21	1		T25	9		T11	2
valid_sources[0x3e]	69766	1			T21	1		T25	9		T1	13
valid_sources[0x3f]	69242	1			T25	7		T12	5021		T13	662
valid_sources[0x40]	70848	1			T21	1		T25	10		T11	1
valid_sources[0x41]	71639	1			T21	2		T25	9		T12	5582
valid_sources[0x42]	69341	1			T21	2		T25	12		T12	5296
valid_sources[0x43]	73062	1			T21	2		T25	12		T12	6546
valid_sources[0x44]	71576	1			T25	10		T11	7		T12	5752
valid_sources[0x45]	72823	1			T25	9		T12	6847		T13	591
valid_sources[0x46]	71126	1			T21	1		T25	11		T1	4
valid_sources[0x47]	68685	1			T21	1		T25	9		T1	6
valid_sources[0x48]	68360	1			T25	10		T1	11		T12	5281
valid_sources[0x49]	70305	1			T21	2		T25	8		T12	5929
valid_sources[0x4a]	68781	1			T25	11		T12	5754		T13	654
valid_sources[0x4b]	68881	1			T25	10		T1	8		T11	2
valid_sources[0x4c]	74550	1			T21	1		T24	1		T25	13
valid_sources[0x4d]	69640	1			T25	7		T11	1		T12	5622
valid_sources[0x4e]	69968	1			T25	11		T12	4869		T13	616
valid_sources[0x4f]	72031	1			T25	8		T12	5341		T13	685
valid_sources[0x50]	76113	1			T25	9		T1	12		T12	5161
valid_sources[0x51]	74342	1			T25	11		T1	7		T11	1
valid_sources[0x52]	70560	1			T21	1		T25	9		T12	5710
valid_sources[0x53]	68284	1			T25	10		T11	1		T12	5317
valid_sources[0x54]	71604	1			T25	4		T12	5095		T13	585
valid_sources[0x55]	83695	1			T25	8		T11	1		T12	6101
valid_sources[0x56]	71367	1			T25	8		T11	2		T12	5704
valid_sources[0x57]	70722	1			T21	2		T25	13		T12	6200
valid_sources[0x58]	75078	1			T25	10		T12	6617		T13	641
valid_sources[0x59]	72371	1			T21	2		T24	1		T25	6
valid_sources[0x5a]	67966	1			T25	4		T11	3		T12	6050
valid_sources[0x5b]	75720	1			T21	2		T25	14		T11	2
valid_sources[0x5c]	68076	1			T25	14		T11	2		T12	6117
valid_sources[0x5d]	74288	1			T21	1		T25	4		T11	4
valid_sources[0x5e]	68636	1			T25	6		T1	2		T12	5511
valid_sources[0x5f]	139563	1			T25	6		T12	6527		T13	685
valid_sources[0x60]	70770	1			T21	1		T25	6		T1	10
valid_sources[0x61]	72565	1			T25	14		T11	1		T12	6374
valid_sources[0x62]	68118	1			T25	12		T11	10		T12	5750
valid_sources[0x63]	75223	1			T25	6		T11	2		T12	5572
valid_sources[0x64]	72947	1			T21	1		T25	14		T11	3
valid_sources[0x65]	70078	1			T21	1		T25	5		T11	1
valid_sources[0x66]	76785	1			T25	7		T11	8		T12	6766
valid_sources[0x67]	76835	1			T21	1		T25	10		T12	6122
valid_sources[0x68]	70166	1			T25	11		T1	21		T11	4
valid_sources[0x69]	67962	1			T24	1		T25	7		T12	5579
valid_sources[0x6a]	76759	1			T21	1		T25	8		T1	1
valid_sources[0x6b]	71978	1			T25	9		T11	1		T12	5179
valid_sources[0x6c]	76039	1			T21	1		T25	8		T11	1
valid_sources[0x6d]	73420	1			T21	4		T25	6		T11	2
valid_sources[0x6e]	70467	1			T25	8		T12	5152		T13	699
valid_sources[0x6f]	73190	1			T25	8		T1	4		T12	6640
valid_sources[0x70]	67667	1			T21	1		T25	10		T1	3
valid_sources[0x71]	75600	1			T21	1		T25	6		T1	6
valid_sources[0x72]	78161	1			T21	2		T25	10		T11	2
valid_sources[0x73]	70183	1			T21	1		T25	7		T11	1
valid_sources[0x74]	71768	1			T25	11		T11	6		T12	6460
valid_sources[0x75]	78487	1			T25	7		T11	3		T12	6241
valid_sources[0x76]	74181	1			T25	6		T12	5812		T13	638
valid_sources[0x77]	70950	1			T24	1		T25	7		T11	1
valid_sources[0x78]	68831	1			T25	6		T12	6180		T13	626
valid_sources[0x79]	68934	1			T25	12		T1	8		T12	4524
valid_sources[0x7a]	68186	1			T25	12		T12	5392		T13	643
valid_sources[0x7b]	69809	1			T21	1		T25	9		T11	4
valid_sources[0x7c]	67593	1			T24	1		T25	14		T12	6138
valid_sources[0x7d]	73458	1			T21	1		T24	1		T25	11
valid_sources[0x7e]	69707	1			T21	1		T25	10		T12	5752
valid_sources[0x7f]	67083	1			T21	2		T25	9		T12	6242
valid_sources[0x80]	70721	1			T25	8		T11	1		T12	6479

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4412099

1

T21

3

T24

1

T25

995

values[0x0]

all_enables

biggest_size

5706098

1

T21

84

T24

2

T25

163

values[0x1]

all_enables

biggest_size

5698030

1

T21

65

T24

2

T25

152