Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	159610664	0	0	0
ctrl_en_input_filter_rd_A	159610664	106288	0	0
intr_ctrl_en_falling_rd_A	159610664	111939	0	0
intr_ctrl_en_lvlhigh_rd_A	159610664	107219	0	0
intr_ctrl_en_lvllow_rd_A	159610664	111619	0	0
intr_ctrl_en_rising_rd_A	159610664	105262	0	0
intr_enable_rd_A	159610664	106249	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	106288	0	0
T1	3493	1	0	0
T2	0	326	0	0
T3	0	67	0	0
T4	0	18888	0	0
T5	0	842	0	0
T6	0	2047	0	0
T7	0	6465	0	0
T8	0	265	0	0
T9	0	333	0	0
T10	0	9	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T17	1877	0	0	0
T18	3599	0	0	0
T19	5566	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	111939	0	0
T1	3493	10	0	0
T2	0	277	0	0
T3	0	99	0	0
T4	0	21570	0	0
T5	0	609	0	0
T6	0	2076	0	0
T7	0	6621	0	0
T8	0	299	0	0
T9	0	278	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T17	1877	0	0	0
T18	3599	0	0	0
T19	5566	0	0	0
T20	0	218	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	107219	0	0
T1	3493	28	0	0
T2	0	264	0	0
T3	0	99	0	0
T4	0	19064	0	0
T5	0	727	0	0
T6	0	1974	0	0
T7	0	6755	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T21	5921	9	0	0
T22	0	9	0	0
T23	0	7	0	0
T24	797	0	0	0
T25	39031	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	111619	0	0
T1	3493	3	0	0
T2	0	373	0	0
T3	0	95	0	0
T4	0	21198	0	0
T5	0	696	0	0
T6	0	1888	0	0
T7	0	7057	0	0
T8	0	215	0	0
T9	0	199	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T17	1877	0	0	0
T18	3599	0	0	0
T19	5566	0	0	0
T26	0	4	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	105262	0	0
T1	3493	24	0	0
T2	0	250	0	0
T3	0	109	0	0
T4	0	19599	0	0
T5	0	773	0	0
T6	0	2169	0	0
T7	0	6294	0	0
T8	0	304	0	0
T9	0	170	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T17	1877	0	0	0
T18	3599	0	0	0
T19	5566	0	0	0
T23	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159610664	106249	0	0
T1	3493	2	0	0
T2	0	298	0	0
T3	0	95	0	0
T4	0	19955	0	0
T5	0	723	0	0
T6	0	2072	0	0
T7	0	6634	0	0
T8	0	279	0	0
T11	4379	0	0	0
T12	151695	0	0	0
T13	743200	0	0	0
T14	5132	0	0	0
T15	571422	0	0	0
T16	1208	0	0	0
T17	1877	0	0	0
T18	3599	3	0	0
T19	5566	0	0	0
T23	0	6	0	0