Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3135233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13780943

1

T21

3141

T22

437

T23

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6807905	1			T21	4840		T22	96		T23	14
values[0x0]	4975571	1			T21	372		T22	199		T23	33
values[0x1]	5132700	1			T21	343		T22	191		T23	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2418664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14497512

1

T21

3633

T22

442

T23

77

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63430	1			T21	11		T22	4		T23	2
valid_sources[0x01]	62236	1			T21	21		T23	1		T24	2
valid_sources[0x02]	65338	1			T21	11		T22	8		T24	1
valid_sources[0x03]	58986	1			T21	26		T22	2		T25	3
valid_sources[0x04]	66508	1			T21	20		T23	1		T25	3
valid_sources[0x05]	66405	1			T21	27		T25	5		T28	5
valid_sources[0x06]	62057	1			T21	21		T23	1		T25	1
valid_sources[0x07]	62634	1			T21	35		T22	1		T23	2
valid_sources[0x08]	56823	1			T21	25		T22	1		T25	3
valid_sources[0x09]	176113	1			T21	19		T22	2		T23	1
valid_sources[0x0a]	73776	1			T21	26		T22	2		T25	9
valid_sources[0x0b]	60326	1			T21	21		T22	1		T25	9
valid_sources[0x0c]	62982	1			T21	24		T22	1		T23	1
valid_sources[0x0d]	58281	1			T21	20		T24	4		T25	8
valid_sources[0x0e]	55781	1			T21	30		T22	5		T25	2
valid_sources[0x0f]	58989	1			T21	18		T22	2		T25	2
valid_sources[0x10]	99046	1			T21	26		T25	5		T26	2
valid_sources[0x11]	84579	1			T21	22		T25	7		T32	9
valid_sources[0x12]	55364	1			T21	16		T22	2		T24	4
valid_sources[0x13]	60583	1			T21	23		T25	4		T28	1
valid_sources[0x14]	56571	1			T21	19		T22	3		T25	2
valid_sources[0x15]	67259	1			T21	23		T22	4		T25	2
valid_sources[0x16]	66332	1			T21	12		T22	1		T24	5
valid_sources[0x17]	56614	1			T21	11		T22	3		T25	6
valid_sources[0x18]	68473	1			T21	20		T23	1		T25	1
valid_sources[0x19]	63642	1			T21	18		T24	1		T25	1
valid_sources[0x1a]	60264	1			T21	18		T23	2		T25	5
valid_sources[0x1b]	59285	1			T21	35		T22	2		T24	5
valid_sources[0x1c]	63158	1			T21	24		T22	1		T25	3
valid_sources[0x1d]	62098	1			T21	24		T23	1		T25	1
valid_sources[0x1e]	57072	1			T21	16		T25	2		T26	2
valid_sources[0x1f]	66044	1			T21	21		T22	3		T23	1
valid_sources[0x20]	59197	1			T21	21		T22	4		T28	6
valid_sources[0x21]	61966	1			T21	28		T22	1		T23	1
valid_sources[0x22]	57014	1			T21	27		T24	7		T25	1
valid_sources[0x23]	55415	1			T21	18		T22	2		T25	3
valid_sources[0x24]	66192	1			T21	18		T22	2		T26	2
valid_sources[0x25]	61250	1			T21	18		T25	3		T28	7
valid_sources[0x26]	57495	1			T21	17		T22	2		T25	2
valid_sources[0x27]	62032	1			T21	24		T24	2		T25	1
valid_sources[0x28]	53724	1			T21	22		T22	2		T23	3
valid_sources[0x29]	69285	1			T21	20		T22	3		T23	2
valid_sources[0x2a]	60387	1			T21	19		T22	2		T24	3
valid_sources[0x2b]	63146	1			T21	33		T22	2		T23	1
valid_sources[0x2c]	63831	1			T21	27		T22	1		T24	2
valid_sources[0x2d]	60110	1			T21	15		T23	1		T24	1
valid_sources[0x2e]	64790	1			T21	26		T22	1		T25	5
valid_sources[0x2f]	61735	1			T21	16		T22	2		T25	1
valid_sources[0x30]	64360	1			T21	38		T22	1		T25	4
valid_sources[0x31]	63364	1			T21	14		T25	1		T28	5
valid_sources[0x32]	66392	1			T21	28		T23	1		T25	4
valid_sources[0x33]	69389	1			T21	22		T22	7		T25	1
valid_sources[0x34]	63259	1			T21	18		T22	5		T25	9
valid_sources[0x35]	66706	1			T21	16		T22	4		T25	4
valid_sources[0x36]	65068	1			T21	15		T25	2		T26	7
valid_sources[0x37]	57643	1			T21	15		T22	1		T25	4
valid_sources[0x38]	67815	1			T21	21		T22	4		T25	4
valid_sources[0x39]	69602	1			T21	17		T25	2		T26	1
valid_sources[0x3a]	67265	1			T21	19		T22	2		T23	1
valid_sources[0x3b]	67631	1			T21	25		T22	1		T25	4
valid_sources[0x3c]	57802	1			T21	16		T22	1		T24	1
valid_sources[0x3d]	68791	1			T21	27		T25	1		T26	3
valid_sources[0x3e]	61655	1			T21	21		T22	1		T25	3
valid_sources[0x3f]	174201	1			T21	31		T22	3		T24	5
valid_sources[0x40]	62579	1			T21	21		T22	1		T25	9
valid_sources[0x41]	60077	1			T21	17		T22	2		T25	3
valid_sources[0x42]	53858	1			T21	17		T22	3		T25	5
valid_sources[0x43]	61530	1			T21	22		T22	2		T25	9
valid_sources[0x44]	59004	1			T21	15		T22	1		T25	5
valid_sources[0x45]	65429	1			T21	14		T23	1		T32	4
valid_sources[0x46]	72622	1			T21	22		T25	3		T28	8
valid_sources[0x47]	58450	1			T21	15		T24	1		T25	3
valid_sources[0x48]	60269	1			T21	22		T22	3		T24	1
valid_sources[0x49]	59485	1			T21	17		T24	2		T25	1
valid_sources[0x4a]	54642	1			T21	26		T22	10		T24	2
valid_sources[0x4b]	53794	1			T21	31		T22	1		T25	3
valid_sources[0x4c]	59082	1			T21	13		T22	2		T23	1
valid_sources[0x4d]	62808	1			T21	12		T22	1		T25	8
valid_sources[0x4e]	62502	1			T21	17		T22	3		T25	2
valid_sources[0x4f]	66784	1			T21	21		T22	1		T25	9
valid_sources[0x50]	59492	1			T21	27		T22	6		T25	2
valid_sources[0x51]	62173	1			T21	25		T24	5		T25	1
valid_sources[0x52]	60075	1			T21	27		T22	1		T23	1
valid_sources[0x53]	55102	1			T21	20		T22	2		T24	5
valid_sources[0x54]	53638	1			T21	15		T22	2		T23	1
valid_sources[0x55]	53618	1			T21	8		T22	4		T24	7
valid_sources[0x56]	53861	1			T21	20		T22	1		T24	1
valid_sources[0x57]	60602	1			T21	21		T22	3		T24	5
valid_sources[0x58]	61247	1			T21	23		T23	1		T25	1
valid_sources[0x59]	62526	1			T21	32		T25	2		T28	3
valid_sources[0x5a]	68435	1			T21	37		T22	2		T23	1
valid_sources[0x5b]	63296	1			T21	19		T25	5		T28	1
valid_sources[0x5c]	64948	1			T21	11		T25	2		T28	4
valid_sources[0x5d]	66124	1			T21	15		T22	1		T25	6
valid_sources[0x5e]	65361	1			T21	24		T22	2		T26	6
valid_sources[0x5f]	76637	1			T21	18		T25	4		T28	7
valid_sources[0x60]	60666	1			T21	19		T25	3		T28	2
valid_sources[0x61]	68653	1			T21	17		T23	1		T25	7
valid_sources[0x62]	56243	1			T21	21		T25	3		T28	3
valid_sources[0x63]	61568	1			T21	19		T25	6		T26	4
valid_sources[0x64]	80459	1			T21	27		T22	4		T25	3
valid_sources[0x65]	65868	1			T21	15		T22	3		T24	7
valid_sources[0x66]	56888	1			T21	14		T22	5		T25	5
valid_sources[0x67]	62143	1			T21	20		T22	2		T25	6
valid_sources[0x68]	61306	1			T21	32		T22	2		T25	4
valid_sources[0x69]	58595	1			T21	21		T22	3		T25	5
valid_sources[0x6a]	61737	1			T21	22		T22	2		T23	1
valid_sources[0x6b]	60523	1			T21	19		T23	1		T24	7
valid_sources[0x6c]	59583	1			T21	19		T25	5		T28	1
valid_sources[0x6d]	64579	1			T21	27		T22	4		T23	1
valid_sources[0x6e]	57174	1			T21	20		T25	1		T28	7
valid_sources[0x6f]	63340	1			T21	27		T22	3		T24	2
valid_sources[0x70]	58098	1			T21	13		T23	1		T24	3
valid_sources[0x71]	64113	1			T21	36		T22	3		T24	9
valid_sources[0x72]	56037	1			T21	10		T23	1		T25	4
valid_sources[0x73]	62415	1			T21	29		T22	1		T24	3
valid_sources[0x74]	71050	1			T21	16		T22	6		T24	3
valid_sources[0x75]	58479	1			T21	25		T22	2		T24	1
valid_sources[0x76]	215206	1			T21	29		T22	1		T23	1
valid_sources[0x77]	58517	1			T21	17		T22	1		T23	2
valid_sources[0x78]	59005	1			T21	16		T22	2		T25	3
valid_sources[0x79]	60763	1			T21	16		T22	1		T24	3
valid_sources[0x7a]	63698	1			T21	25		T22	4		T24	4
valid_sources[0x7b]	189980	1			T21	15		T22	2		T23	1
valid_sources[0x7c]	63385	1			T21	20		T22	4		T26	5
valid_sources[0x7d]	57986	1			T21	23		T26	4		T28	6
valid_sources[0x7e]	68023	1			T21	16		T22	3		T25	4
valid_sources[0x7f]	61756	1			T21	19		T22	2		T23	1
valid_sources[0x80]	60003	1			T21	10		T25	2		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3865534

1

T21

2426

T22

47

T23

7

values[0x0]

all_enables

biggest_size

4959357

1

T21

372

T22

199

T23

33

values[0x1]

all_enables

biggest_size

4956052

1

T21

343

T22

191

T23

37