Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	146622541	0	0	0
ctrl_en_input_filter_rd_A	146622541	101338	0	0
intr_ctrl_en_falling_rd_A	146622541	101882	0	0
intr_ctrl_en_lvlhigh_rd_A	146622541	98671	0	0
intr_ctrl_en_lvllow_rd_A	146622541	102178	0	0
intr_ctrl_en_rising_rd_A	146622541	98113	0	0
intr_enable_rd_A	146622541	99985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	101338	0	0
T1	3797	5	0	0
T2	34615	194	0	0
T3	0	945	0	0
T4	0	6452	0	0
T5	0	4770	0	0
T6	0	5276	0	0
T7	0	299	0	0
T8	0	81	0	0
T9	0	352	0	0
T10	0	116	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	0	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	101882	0	0
T1	3797	5	0	0
T2	34615	276	0	0
T3	0	1148	0	0
T4	0	5638	0	0
T5	0	4909	0	0
T6	0	4570	0	0
T7	0	390	0	0
T8	0	126	0	0
T9	0	264	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	6	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	98671	0	0
T2	34615	165	0	0
T3	0	1124	0	0
T4	0	6116	0	0
T5	0	4616	0	0
T6	0	4853	0	0
T7	0	246	0	0
T8	0	105	0	0
T9	0	284	0	0
T10	0	197	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	1	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0
T19	1034	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	102178	0	0
T2	34615	203	0	0
T3	0	1064	0	0
T4	0	5724	0	0
T5	0	5055	0	0
T6	0	4748	0	0
T7	0	297	0	0
T8	0	108	0	0
T9	0	213	0	0
T10	0	156	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	0	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0
T19	1034	0	0	0
T20	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	98113	0	0
T2	34615	253	0	0
T3	0	1100	0	0
T4	0	5928	0	0
T5	0	4855	0	0
T6	0	4581	0	0
T7	0	219	0	0
T8	0	102	0	0
T9	0	248	0	0
T10	0	118	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	6	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0
T19	1034	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146622541	99985	0	0
T2	34615	272	0	0
T3	0	1048	0	0
T4	0	5806	0	0
T5	0	5247	0	0
T6	0	4825	0	0
T7	0	310	0	0
T8	0	99	0	0
T9	0	311	0	0
T10	0	95	0	0
T11	8025	0	0	0
T12	1159	0	0	0
T13	6617	0	0	0
T14	5047	0	0	0
T15	763406	0	0	0
T16	2657	0	0	0
T17	4315	0	0	0
T18	5860	0	0	0
T19	1034	0	0	0
T20	0	3	0	0