Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 934
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T760 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2615355969 Mar 05 12:40:53 PM PST 24 Mar 05 12:40:54 PM PST 24 37273979 ps
T104 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1889494393 Mar 05 12:40:40 PM PST 24 Mar 05 12:40:41 PM PST 24 340135598 ps
T761 /workspace/coverage/cover_reg_top/48.gpio_intr_test.4129279543 Mar 05 12:40:48 PM PST 24 Mar 05 12:40:49 PM PST 24 28097935 ps
T47 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3885483830 Mar 05 12:41:08 PM PST 24 Mar 05 12:41:09 PM PST 24 125747376 ps
T762 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1206983973 Mar 05 12:40:37 PM PST 24 Mar 05 12:40:38 PM PST 24 13652449 ps
T763 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3608706256 Mar 05 12:41:03 PM PST 24 Mar 05 12:41:04 PM PST 24 26001612 ps
T764 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1028667455 Mar 05 12:41:10 PM PST 24 Mar 05 12:41:11 PM PST 24 200490785 ps
T90 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.380511248 Mar 05 12:40:32 PM PST 24 Mar 05 12:40:34 PM PST 24 119338305 ps
T91 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2309554237 Mar 05 12:40:54 PM PST 24 Mar 05 12:41:00 PM PST 24 19869907 ps
T765 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3625383674 Mar 05 12:40:36 PM PST 24 Mar 05 12:40:39 PM PST 24 134277074 ps
T766 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2721899199 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:55 PM PST 24 19739783 ps
T767 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3503989154 Mar 05 12:40:52 PM PST 24 Mar 05 12:40:58 PM PST 24 534859768 ps
T768 /workspace/coverage/cover_reg_top/21.gpio_intr_test.130359670 Mar 05 12:41:14 PM PST 24 Mar 05 12:41:14 PM PST 24 37525610 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2687980230 Mar 05 12:40:50 PM PST 24 Mar 05 12:40:51 PM PST 24 18153293 ps
T770 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.867492646 Mar 05 12:40:53 PM PST 24 Mar 05 12:40:54 PM PST 24 440051166 ps
T771 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2941974191 Mar 05 12:40:51 PM PST 24 Mar 05 12:40:52 PM PST 24 30433441 ps
T772 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2599925912 Mar 05 12:41:06 PM PST 24 Mar 05 12:41:06 PM PST 24 13174899 ps
T773 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3790952608 Mar 05 12:41:07 PM PST 24 Mar 05 12:41:08 PM PST 24 28215834 ps
T48 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.152751841 Mar 05 12:40:31 PM PST 24 Mar 05 12:40:32 PM PST 24 49431273 ps
T774 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2982754095 Mar 05 12:40:42 PM PST 24 Mar 05 12:40:44 PM PST 24 79158257 ps
T92 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.80315714 Mar 05 12:40:53 PM PST 24 Mar 05 12:40:54 PM PST 24 34819128 ps
T775 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3826014507 Mar 05 12:41:15 PM PST 24 Mar 05 12:41:16 PM PST 24 32917276 ps
T93 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2853217953 Mar 05 12:40:38 PM PST 24 Mar 05 12:40:39 PM PST 24 34126526 ps
T776 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3131623346 Mar 05 12:40:59 PM PST 24 Mar 05 12:41:00 PM PST 24 111360255 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2548836235 Mar 05 12:40:40 PM PST 24 Mar 05 12:40:41 PM PST 24 31550602 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.4036961115 Mar 05 12:40:42 PM PST 24 Mar 05 12:40:43 PM PST 24 135715122 ps
T779 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2625035951 Mar 05 12:41:13 PM PST 24 Mar 05 12:41:15 PM PST 24 17135255 ps
T780 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2673491598 Mar 05 12:41:04 PM PST 24 Mar 05 12:41:05 PM PST 24 96077808 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.104098827 Mar 05 12:40:41 PM PST 24 Mar 05 12:40:42 PM PST 24 13846792 ps
T782 /workspace/coverage/cover_reg_top/26.gpio_intr_test.643370028 Mar 05 12:40:51 PM PST 24 Mar 05 12:40:52 PM PST 24 13464921 ps
T783 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2057397133 Mar 05 12:41:07 PM PST 24 Mar 05 12:41:08 PM PST 24 88293031 ps
T784 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1915790322 Mar 05 12:40:42 PM PST 24 Mar 05 12:40:44 PM PST 24 49868775 ps
T785 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3577883742 Mar 05 12:40:39 PM PST 24 Mar 05 12:40:40 PM PST 24 84953867 ps
T786 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3199072429 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:57 PM PST 24 242928211 ps
T787 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4198517365 Mar 05 12:40:51 PM PST 24 Mar 05 12:40:52 PM PST 24 12510434 ps
T788 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3151119853 Mar 05 12:41:13 PM PST 24 Mar 05 12:41:14 PM PST 24 25116749 ps
T789 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2009087266 Mar 05 12:41:03 PM PST 24 Mar 05 12:41:04 PM PST 24 64436867 ps
T790 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3852582438 Mar 05 12:41:06 PM PST 24 Mar 05 12:41:06 PM PST 24 16506110 ps
T791 /workspace/coverage/cover_reg_top/34.gpio_intr_test.109408192 Mar 05 12:41:02 PM PST 24 Mar 05 12:41:03 PM PST 24 13172890 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3369745500 Mar 05 12:40:53 PM PST 24 Mar 05 12:40:54 PM PST 24 18734412 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1322143040 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:57 PM PST 24 87952520 ps
T94 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4021912956 Mar 05 12:41:10 PM PST 24 Mar 05 12:41:11 PM PST 24 14954026 ps
T794 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2209328021 Mar 05 12:41:02 PM PST 24 Mar 05 12:41:03 PM PST 24 291322731 ps
T795 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2586963517 Mar 05 12:40:32 PM PST 24 Mar 05 12:40:33 PM PST 24 35239773 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3645148932 Mar 05 12:40:43 PM PST 24 Mar 05 12:40:44 PM PST 24 101427209 ps
T797 /workspace/coverage/cover_reg_top/40.gpio_intr_test.96620108 Mar 05 12:41:04 PM PST 24 Mar 05 12:41:05 PM PST 24 48943887 ps
T798 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2310711188 Mar 05 12:41:15 PM PST 24 Mar 05 12:41:16 PM PST 24 48211251 ps
T799 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1804243468 Mar 05 12:41:06 PM PST 24 Mar 05 12:41:07 PM PST 24 15996111 ps
T800 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4184465610 Mar 05 12:40:48 PM PST 24 Mar 05 12:40:49 PM PST 24 35631060 ps
T801 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2163088773 Mar 05 12:41:09 PM PST 24 Mar 05 12:41:11 PM PST 24 29079305 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.991561641 Mar 05 12:40:46 PM PST 24 Mar 05 12:40:49 PM PST 24 581359950 ps
T803 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3787829123 Mar 05 12:40:59 PM PST 24 Mar 05 12:41:00 PM PST 24 25349707 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.944260625 Mar 05 12:40:49 PM PST 24 Mar 05 12:40:50 PM PST 24 78447210 ps
T805 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3869736434 Mar 05 12:41:03 PM PST 24 Mar 05 12:41:04 PM PST 24 112677448 ps
T806 /workspace/coverage/cover_reg_top/24.gpio_intr_test.764738822 Mar 05 12:41:17 PM PST 24 Mar 05 12:41:18 PM PST 24 63126926 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2910154502 Mar 05 12:40:33 PM PST 24 Mar 05 12:40:34 PM PST 24 24126954 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.58189558 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:56 PM PST 24 58977028 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2777813823 Mar 05 12:40:47 PM PST 24 Mar 05 12:40:48 PM PST 24 43366311 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3514447332 Mar 05 12:40:59 PM PST 24 Mar 05 12:41:02 PM PST 24 1785515895 ps
T811 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.115212573 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:56 PM PST 24 173449968 ps
T812 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2129149670 Mar 05 12:41:03 PM PST 24 Mar 05 12:41:04 PM PST 24 218067881 ps
T813 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4179179816 Mar 05 12:40:34 PM PST 24 Mar 05 12:40:35 PM PST 24 55011147 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_intr_test.457712616 Mar 05 12:40:38 PM PST 24 Mar 05 12:40:39 PM PST 24 14807929 ps
T815 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3170946034 Mar 05 12:40:45 PM PST 24 Mar 05 12:40:46 PM PST 24 153149791 ps
T816 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2721343982 Mar 05 12:40:46 PM PST 24 Mar 05 12:40:47 PM PST 24 11045103 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4234597484 Mar 05 12:40:50 PM PST 24 Mar 05 12:40:51 PM PST 24 80890572 ps
T818 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2881027784 Mar 05 12:41:11 PM PST 24 Mar 05 12:41:12 PM PST 24 274132387 ps
T819 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3675905773 Mar 05 12:40:54 PM PST 24 Mar 05 12:40:55 PM PST 24 20342670 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3591586508 Mar 05 12:40:41 PM PST 24 Mar 05 12:40:42 PM PST 24 71258064 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.559924911 Mar 05 12:40:43 PM PST 24 Mar 05 12:40:46 PM PST 24 181299293 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3199911987 Mar 05 12:41:06 PM PST 24 Mar 05 12:41:08 PM PST 24 399607528 ps
T823 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2583613969 Mar 05 12:40:38 PM PST 24 Mar 05 12:40:39 PM PST 24 133086435 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1185276938 Mar 05 12:41:02 PM PST 24 Mar 05 12:41:04 PM PST 24 163057217 ps
T825 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4131629373 Mar 05 12:40:45 PM PST 24 Mar 05 12:40:47 PM PST 24 57890567 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1012810990 Mar 05 12:41:10 PM PST 24 Mar 05 12:41:17 PM PST 24 40818701 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2903945471 Mar 05 12:40:47 PM PST 24 Mar 05 12:40:48 PM PST 24 69082026 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2881121732 Mar 05 12:40:48 PM PST 24 Mar 05 12:40:49 PM PST 24 16441855 ps
T829 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1307116951 Mar 05 12:40:50 PM PST 24 Mar 05 12:40:51 PM PST 24 47797373 ps
T830 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4216595097 Mar 05 12:40:55 PM PST 24 Mar 05 12:40:55 PM PST 24 26255103 ps
T831 /workspace/coverage/cover_reg_top/19.gpio_intr_test.4204008101 Mar 05 12:41:10 PM PST 24 Mar 05 12:41:11 PM PST 24 34139049 ps
T832 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2408340292 Mar 05 12:40:59 PM PST 24 Mar 05 12:41:01 PM PST 24 43282442 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.789035967 Mar 05 12:41:01 PM PST 24 Mar 05 12:41:01 PM PST 24 40276872 ps
T833 /workspace/coverage/cover_reg_top/37.gpio_intr_test.860800513 Mar 05 12:41:05 PM PST 24 Mar 05 12:41:06 PM PST 24 23725783 ps
T834 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2407234656 Mar 05 12:40:40 PM PST 24 Mar 05 12:40:43 PM PST 24 111845156 ps
T835 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3688953094 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:17 PM PST 24 261430606 ps
T836 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.514144886 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 114185279 ps
T837 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3553034001 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:28 PM PST 24 96656310 ps
T838 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2697607005 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:18 PM PST 24 116864796 ps
T839 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3628811779 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:23 PM PST 24 153167958 ps
T840 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2366274621 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 122424941 ps
T841 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585354270 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:08 PM PST 24 50352654 ps
T842 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3590151222 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 28671820 ps
T843 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2960626181 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 35204229 ps
T844 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2859302289 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 31977361 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1315583143 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:21 PM PST 24 21366410 ps
T846 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3179179204 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:18 PM PST 24 39468412 ps
T847 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1342918093 Mar 05 12:39:26 PM PST 24 Mar 05 12:39:27 PM PST 24 135735287 ps
T848 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.680597640 Mar 05 12:39:19 PM PST 24 Mar 05 12:39:25 PM PST 24 123128569 ps
T849 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2328045992 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:15 PM PST 24 326606204 ps
T850 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2547732713 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 102485836 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3717293824 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:22 PM PST 24 28960336 ps
T852 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4283779440 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 264009416 ps
T853 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1868462310 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:44 PM PST 24 59674227 ps
T854 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233424177 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:26 PM PST 24 130666966 ps
T855 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.877741539 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:40 PM PST 24 216001370 ps
T856 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.480959284 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 60941705 ps
T857 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324064113 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:18 PM PST 24 200962880 ps
T858 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1562726037 Mar 05 12:39:30 PM PST 24 Mar 05 12:39:32 PM PST 24 358749815 ps
T859 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.314900854 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 261682270 ps
T860 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2486595026 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:28 PM PST 24 52517746 ps
T861 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1172486642 Mar 05 12:39:08 PM PST 24 Mar 05 12:39:10 PM PST 24 232527593 ps
T862 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.613466270 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 248390768 ps
T863 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4044386579 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 73930704 ps
T864 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149577221 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:36 PM PST 24 80662812 ps
T865 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2259791896 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 43060611 ps
T866 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3125086102 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 241846530 ps
T867 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1642215434 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 103247433 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2336780390 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:03 PM PST 24 281779284 ps
T869 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.440974877 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 222981705 ps
T870 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456231509 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:28 PM PST 24 64837923 ps
T871 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.315131672 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 25671779 ps
T872 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945807624 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 63641294 ps
T873 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.739960046 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:26 PM PST 24 261337976 ps
T874 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1608453528 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:23 PM PST 24 61416389 ps
T875 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.289016599 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 46615706 ps
T876 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3628067528 Mar 05 12:39:46 PM PST 24 Mar 05 12:39:48 PM PST 24 57624508 ps
T877 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453201455 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:32 PM PST 24 141094640 ps
T878 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1861627245 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:13 PM PST 24 259783955 ps
T879 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2174202540 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 263342031 ps
T880 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3022758074 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 65846769 ps
T881 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3131667745 Mar 05 12:39:03 PM PST 24 Mar 05 12:39:07 PM PST 24 167721156 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2609783219 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:19 PM PST 24 77866843 ps
T883 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2857982821 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:36 PM PST 24 72957013 ps
T884 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4099206124 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:07 PM PST 24 120896978 ps
T885 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3239095577 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 85224541 ps
T886 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3527350905 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 64979891 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2566623101 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:21 PM PST 24 61488205 ps
T888 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3192802822 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 72362504 ps
T889 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4141012562 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 54677428 ps
T890 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2851758178 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:13 PM PST 24 249330750 ps
T891 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.965968642 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 40731138 ps
T892 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1653213773 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:26 PM PST 24 126833018 ps
T893 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1228010107 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 140894080 ps
T894 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169437821 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 435395696 ps
T895 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2944875003 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:15 PM PST 24 224320092 ps
T896 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1816968712 Mar 05 12:39:21 PM PST 24 Mar 05 12:39:23 PM PST 24 189784233 ps
T897 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.224819047 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:29 PM PST 24 120549005 ps
T898 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2686858055 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:21 PM PST 24 31671168 ps
T899 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501941540 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 145102792 ps
T900 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2356400585 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 303629683 ps
T901 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3160637379 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:19 PM PST 24 206478774 ps
T902 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.498477970 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:16 PM PST 24 791224289 ps
T903 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3852585757 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:27 PM PST 24 151919144 ps
T904 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3280095886 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 44043504 ps
T905 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1543910381 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 42833886 ps
T906 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833506418 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:15 PM PST 24 132703759 ps
T907 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057199996 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 172235459 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3374753699 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:36 PM PST 24 128741103 ps
T909 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540825278 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 55275428 ps
T910 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3368000253 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 221842004 ps
T911 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1916696017 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 306030716 ps
T912 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2835779736 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:31 PM PST 24 54453028 ps
T913 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.469871386 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:27 PM PST 24 49279782 ps
T914 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4158410007 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:18 PM PST 24 262007305 ps
T915 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2980072196 Mar 05 12:39:32 PM PST 24 Mar 05 12:39:33 PM PST 24 79743609 ps
T916 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71020716 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:17 PM PST 24 71669227 ps
T917 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2020141379 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 37772432 ps
T918 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2609429038 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 148038603 ps
T919 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113988475 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 53682309 ps
T920 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495317508 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:12 PM PST 24 49762187 ps
T921 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3578031583 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:23 PM PST 24 139933976 ps
T922 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1462332329 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 43283659 ps
T923 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4180361378 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:13 PM PST 24 49062057 ps
T924 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3994747789 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 113951499 ps
T925 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1930459620 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 546523315 ps
T926 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1349977134 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 43539827 ps
T927 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2116002696 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:35 PM PST 24 56747207 ps
T928 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3788942381 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:35 PM PST 24 102931094 ps
T929 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4057127693 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:22 PM PST 24 153038340 ps
T930 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3324450297 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 83632911 ps
T931 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1042516900 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:08 PM PST 24 65713509 ps
T932 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272851840 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:08 PM PST 24 336050965 ps
T933 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3486772775 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 409115993 ps
T934 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4124344330 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:36 PM PST 24 206180874 ps

Test location /workspace/coverage/default/2.gpio_full_random.1611242504
Short name T24
Test name
Test status
Simulation time 260846615 ps
CPU time 0.96 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 196656 kb
Host smart-2b5e6434-0485-4466-a1ee-e18fa3829043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611242504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1611242504
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1696887393
Short name T28
Test name
Test status
Simulation time 40026756 ps
CPU time 1.72 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:22 PM PST 24
Peak memory 196916 kb
Host smart-5ad0c825-b141-4db0-94f4-d5ba57f368ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696887393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1696887393
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_full_random.2021426342
Short name T1
Test name
Test status
Simulation time 146143464 ps
CPU time 0.75 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 196656 kb
Host smart-ff18ba1a-6159-436e-a2b5-392f60c22e51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021426342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2021426342
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3984141759
Short name T33
Test name
Test status
Simulation time 102713024776 ps
CPU time 2232.14 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 01:36:56 PM PST 24
Peak memory 198288 kb
Host smart-5363b4f6-db13-40cf-9923-67e4d819dffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3984141759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3984141759
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.728808405
Short name T2
Test name
Test status
Simulation time 1236259517 ps
CPU time 4.52 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 197992 kb
Host smart-bd7dd013-edfe-4898-8e66-bc44f0490eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728808405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.728808405
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3914265186
Short name T40
Test name
Test status
Simulation time 71457550 ps
CPU time 0.79 seconds
Started Mar 05 12:59:08 PM PST 24
Finished Mar 05 12:59:09 PM PST 24
Peak memory 213836 kb
Host smart-c3a084c4-c7e6-4f6b-988b-31525450e0f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914265186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3914265186
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1451756529
Short name T83
Test name
Test status
Simulation time 41798102 ps
CPU time 0.62 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:40:43 PM PST 24
Peak memory 196004 kb
Host smart-e531b72f-05c6-4575-b218-96eb089980c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451756529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1451756529
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4174922661
Short name T49
Test name
Test status
Simulation time 106727630 ps
CPU time 1.34 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 198192 kb
Host smart-e141a7c0-259c-4718-890c-26c604741857
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174922661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.4174922661
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2969270436
Short name T119
Test name
Test status
Simulation time 67195819 ps
CPU time 0.59 seconds
Started Mar 05 01:00:19 PM PST 24
Finished Mar 05 01:00:20 PM PST 24
Peak memory 195032 kb
Host smart-70daca06-1198-4637-8450-0cf17dce3bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969270436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2969270436
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3401268631
Short name T108
Test name
Test status
Simulation time 277130951 ps
CPU time 0.86 seconds
Started Mar 05 01:01:03 PM PST 24
Finished Mar 05 01:01:04 PM PST 24
Peak memory 197336 kb
Host smart-388d20b4-263a-48b7-8b98-4a392e34426d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401268631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3401268631
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1709660717
Short name T98
Test name
Test status
Simulation time 67443051 ps
CPU time 0.86 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 196720 kb
Host smart-d6e55735-fda2-43e4-8b3d-ea0ee50f6fe8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709660717 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1709660717
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2881027784
Short name T818
Test name
Test status
Simulation time 274132387 ps
CPU time 1.12 seconds
Started Mar 05 12:41:11 PM PST 24
Finished Mar 05 12:41:12 PM PST 24
Peak memory 198428 kb
Host smart-66e695c6-ad71-4386-ae52-8d0b32297e9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881027784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2881027784
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.96908240
Short name T32
Test name
Test status
Simulation time 243124144 ps
CPU time 7.69 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 198032 kb
Host smart-c917c62e-c9ad-48b4-854c-125b52b9dbe9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96908240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress.96908240
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.380511248
Short name T90
Test name
Test status
Simulation time 119338305 ps
CPU time 0.75 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 196116 kb
Host smart-53fcfeab-695a-411b-9bb4-5003220da68a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380511248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.380511248
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.4036961115
Short name T778
Test name
Test status
Simulation time 135715122 ps
CPU time 1.41 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:40:43 PM PST 24
Peak memory 197292 kb
Host smart-05397589-fe88-416d-9263-c36d470bc4b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036961115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.4036961115
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2804791635
Short name T84
Test name
Test status
Simulation time 40430715 ps
CPU time 0.63 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 195408 kb
Host smart-8ea44e29-22c8-4436-bf69-a758888e1cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804791635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2804791635
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.944260625
Short name T804
Test name
Test status
Simulation time 78447210 ps
CPU time 0.92 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 198484 kb
Host smart-3fe45735-8359-4922-a8e6-66e055d4c5e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944260625 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.944260625
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2881121732
Short name T828
Test name
Test status
Simulation time 16441855 ps
CPU time 0.62 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 195696 kb
Host smart-0c1cbb2d-9cd4-4c79-b3a5-272ae170541d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881121732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2881121732
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2882831232
Short name T719
Test name
Test status
Simulation time 62043460 ps
CPU time 0.61 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 194192 kb
Host smart-58931ec3-c47a-4b40-89de-44821eee02e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882831232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2882831232
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3503989154
Short name T767
Test name
Test status
Simulation time 534859768 ps
CPU time 0.73 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:40:58 PM PST 24
Peak memory 196368 kb
Host smart-704b21fc-6314-4934-9e35-b85629a9d06e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503989154 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3503989154
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2957663290
Short name T709
Test name
Test status
Simulation time 218720193 ps
CPU time 1.84 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:57 PM PST 24
Peak memory 198504 kb
Host smart-c6b53254-e5c3-48b8-a181-ed0bd3a546a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957663290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2957663290
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4280045552
Short name T38
Test name
Test status
Simulation time 88655672 ps
CPU time 0.86 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 197396 kb
Host smart-0b2689da-2a74-4113-8f0b-81482f144011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280045552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4280045552
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2853217953
Short name T93
Test name
Test status
Simulation time 34126526 ps
CPU time 0.86 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 197028 kb
Host smart-9bd4dfbd-f774-4698-a4dd-fd7564d8dd22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853217953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2853217953
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.155043191
Short name T720
Test name
Test status
Simulation time 265013618 ps
CPU time 1.56 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 197148 kb
Host smart-b3c7fc82-0269-4a6c-a4bf-f677c6cdd97b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155043191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.155043191
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4179179816
Short name T813
Test name
Test status
Simulation time 55011147 ps
CPU time 0.63 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 195000 kb
Host smart-6c2d77d8-a3ae-4477-bebc-8a0feb31616a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179179816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4179179816
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.175706688
Short name T712
Test name
Test status
Simulation time 96857643 ps
CPU time 1.27 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 198584 kb
Host smart-8d41a476-8e49-4bb8-abc6-180a0e371cae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175706688 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.175706688
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.789035967
Short name T96
Test name
Test status
Simulation time 40276872 ps
CPU time 0.66 seconds
Started Mar 05 12:41:01 PM PST 24
Finished Mar 05 12:41:01 PM PST 24
Peak memory 195832 kb
Host smart-01d51aa0-85b9-4c2d-a782-dc532ac01916
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789035967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.789035967
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.457712616
Short name T814
Test name
Test status
Simulation time 14807929 ps
CPU time 0.61 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 194240 kb
Host smart-2cf3d501-d012-4ff3-b760-8034a605728d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457712616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.457712616
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.58189558
Short name T808
Test name
Test status
Simulation time 58977028 ps
CPU time 0.93 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 198200 kb
Host smart-b325e0b3-5311-4253-ab03-3d2049caaa51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58189558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.58189558
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3108160203
Short name T103
Test name
Test status
Simulation time 128850278 ps
CPU time 0.83 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 197464 kb
Host smart-9208bc44-5800-4acc-914d-a9a0bd937949
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108160203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3108160203
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2592745263
Short name T752
Test name
Test status
Simulation time 30217133 ps
CPU time 1.48 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:07 PM PST 24
Peak memory 198516 kb
Host smart-8524741d-2c7f-4e8d-84f5-775fc3ee9ac8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592745263 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2592745263
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3852582438
Short name T790
Test name
Test status
Simulation time 16506110 ps
CPU time 0.64 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:06 PM PST 24
Peak memory 195388 kb
Host smart-b0820477-3799-4f80-aaf4-459266ab3eda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852582438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3852582438
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1890103791
Short name T710
Test name
Test status
Simulation time 27183356 ps
CPU time 0.65 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 194876 kb
Host smart-b5f89846-9ee3-427e-a425-2fa93d73f0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890103791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1890103791
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3869736434
Short name T805
Test name
Test status
Simulation time 112677448 ps
CPU time 0.69 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 195272 kb
Host smart-ad206738-8080-44d3-9f08-f5ca5a6361ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869736434 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3869736434
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.82374815
Short name T717
Test name
Test status
Simulation time 167629174 ps
CPU time 2.29 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 198408 kb
Host smart-76839677-0e4a-4c0c-b43d-1e3f9be9e54b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82374815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.82374815
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2047857159
Short name T726
Test name
Test status
Simulation time 35773543 ps
CPU time 1.21 seconds
Started Mar 05 12:41:11 PM PST 24
Finished Mar 05 12:41:13 PM PST 24
Peak memory 198588 kb
Host smart-29249eb7-32b5-42f6-986b-66ec98b1b52c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047857159 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2047857159
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4122270959
Short name T727
Test name
Test status
Simulation time 14467518 ps
CPU time 0.59 seconds
Started Mar 05 12:41:05 PM PST 24
Finished Mar 05 12:41:06 PM PST 24
Peak memory 194332 kb
Host smart-33bb72c4-e3bc-4b16-81f8-b8ae45f9ec03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122270959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4122270959
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2294793778
Short name T716
Test name
Test status
Simulation time 61575074 ps
CPU time 0.59 seconds
Started Mar 05 12:41:13 PM PST 24
Finished Mar 05 12:41:18 PM PST 24
Peak memory 194132 kb
Host smart-e3301265-a4b2-475b-bdda-0aee05817bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294793778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2294793778
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3145072579
Short name T87
Test name
Test status
Simulation time 24176848 ps
CPU time 0.78 seconds
Started Mar 05 12:41:12 PM PST 24
Finished Mar 05 12:41:13 PM PST 24
Peak memory 197296 kb
Host smart-038c4203-b40d-497c-b4b2-7aa34cc1019f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145072579 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3145072579
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2408340292
Short name T832
Test name
Test status
Simulation time 43282442 ps
CPU time 2.11 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:01 PM PST 24
Peak memory 198512 kb
Host smart-a9d2c060-8aee-4c1c-82bd-229b7563c922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408340292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2408340292
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2126974015
Short name T36
Test name
Test status
Simulation time 1025759997 ps
CPU time 1.54 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 198560 kb
Host smart-9ff966f3-12dc-40f2-8b13-7337ec6b8a90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126974015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2126974015
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2542139725
Short name T748
Test name
Test status
Simulation time 21381771 ps
CPU time 0.72 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 198340 kb
Host smart-8b7449b3-827b-4045-a4ac-8c3585716e1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542139725 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2542139725
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2142741870
Short name T79
Test name
Test status
Simulation time 53628223 ps
CPU time 0.57 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 194968 kb
Host smart-f180f60d-b6eb-4293-a855-a2405bd62853
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142741870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2142741870
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1771911558
Short name T730
Test name
Test status
Simulation time 10946577 ps
CPU time 0.64 seconds
Started Mar 05 12:40:58 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 194200 kb
Host smart-40e5295c-82c1-4f18-bb82-ccad70472740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771911558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1771911558
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1691248161
Short name T97
Test name
Test status
Simulation time 20530937 ps
CPU time 0.62 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 195412 kb
Host smart-3b36c33a-0ee2-4c29-b5f2-bd12cc25742e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691248161 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1691248161
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1012810990
Short name T826
Test name
Test status
Simulation time 40818701 ps
CPU time 1.25 seconds
Started Mar 05 12:41:10 PM PST 24
Finished Mar 05 12:41:17 PM PST 24
Peak memory 198424 kb
Host smart-132aab22-0c52-441f-bf75-8a67fc053772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012810990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1012810990
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.82699908
Short name T746
Test name
Test status
Simulation time 13595615 ps
CPU time 0.64 seconds
Started Mar 05 12:41:20 PM PST 24
Finished Mar 05 12:41:20 PM PST 24
Peak memory 197460 kb
Host smart-533c7a03-cf6c-4bb5-ac18-d485228123ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82699908 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.82699908
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2721343982
Short name T816
Test name
Test status
Simulation time 11045103 ps
CPU time 0.6 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 195864 kb
Host smart-930abe86-1e15-4201-a8f5-837ab9b24adc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721343982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2721343982
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2548836235
Short name T777
Test name
Test status
Simulation time 31550602 ps
CPU time 0.56 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 194160 kb
Host smart-4941997d-92d2-4dfa-a857-574607617769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548836235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2548836235
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.827973257
Short name T99
Test name
Test status
Simulation time 31907974 ps
CPU time 0.85 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 196812 kb
Host smart-1c5ebd5d-7497-4108-8c3d-7a4817c966c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827973257 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.827973257
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.944823453
Short name T744
Test name
Test status
Simulation time 211254055 ps
CPU time 2.14 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 198484 kb
Host smart-5b5c1792-33d3-48b4-8ff7-f87b0650fdb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944823453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.944823453
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2209328021
Short name T794
Test name
Test status
Simulation time 291322731 ps
CPU time 0.82 seconds
Started Mar 05 12:41:02 PM PST 24
Finished Mar 05 12:41:03 PM PST 24
Peak memory 198220 kb
Host smart-e599cae7-81b6-4b59-875c-458d7ee75050
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209328021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2209328021
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3826014507
Short name T775
Test name
Test status
Simulation time 32917276 ps
CPU time 1.07 seconds
Started Mar 05 12:41:15 PM PST 24
Finished Mar 05 12:41:16 PM PST 24
Peak memory 198604 kb
Host smart-39e0ccb5-11f5-48fd-ae09-f31e57403870
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826014507 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3826014507
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.39685538
Short name T725
Test name
Test status
Simulation time 12889681 ps
CPU time 0.59 seconds
Started Mar 05 12:41:13 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 194924 kb
Host smart-3c1ffd06-1cc1-4f6c-9c14-7cc3b6e19c32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39685538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.39685538
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4216595097
Short name T830
Test name
Test status
Simulation time 26255103 ps
CPU time 0.56 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 194108 kb
Host smart-755e08ea-f03e-49ff-baf5-934e0cbbffd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216595097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4216595097
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.410593468
Short name T80
Test name
Test status
Simulation time 41894968 ps
CPU time 0.62 seconds
Started Mar 05 12:41:08 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 195236 kb
Host smart-5ba7c9aa-725c-4297-9687-9a800e4bfc83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410593468 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.410593468
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3028804624
Short name T749
Test name
Test status
Simulation time 60999721 ps
CPU time 1.34 seconds
Started Mar 05 12:41:10 PM PST 24
Finished Mar 05 12:41:12 PM PST 24
Peak memory 198412 kb
Host smart-0df01392-2fc3-411c-8ce1-1e1722abdd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028804624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3028804624
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2057397133
Short name T783
Test name
Test status
Simulation time 88293031 ps
CPU time 1.11 seconds
Started Mar 05 12:41:07 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 198476 kb
Host smart-c6a7c2cc-fa4c-4b06-8e70-5a26c5059188
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057397133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2057397133
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2306445050
Short name T753
Test name
Test status
Simulation time 305193830 ps
CPU time 0.81 seconds
Started Mar 05 12:41:07 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 197916 kb
Host smart-5d11acd9-4e56-433d-8c2e-97cec06c6f51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306445050 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2306445050
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4198517365
Short name T787
Test name
Test status
Simulation time 12510434 ps
CPU time 0.6 seconds
Started Mar 05 12:40:51 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 195008 kb
Host smart-01824972-248b-4c94-bcbb-8ea3d5a31347
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198517365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4198517365
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2675832650
Short name T757
Test name
Test status
Simulation time 24241475 ps
CPU time 0.65 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:40:53 PM PST 24
Peak memory 194144 kb
Host smart-c3a2d8b6-a1c1-426f-9ee5-a029c74b8b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675832650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2675832650
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3608706256
Short name T763
Test name
Test status
Simulation time 26001612 ps
CPU time 0.79 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 196444 kb
Host smart-00d87269-9a86-4a4e-9358-f0229b2b773b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608706256 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3608706256
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3131623346
Short name T776
Test name
Test status
Simulation time 111360255 ps
CPU time 0.93 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 198308 kb
Host smart-401bc8d0-fec4-41b0-9e96-a6db1bd801a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131623346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3131623346
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.815347384
Short name T37
Test name
Test status
Simulation time 96504806 ps
CPU time 1.42 seconds
Started Mar 05 12:41:00 PM PST 24
Finished Mar 05 12:41:01 PM PST 24
Peak memory 198448 kb
Host smart-b67f1627-8598-4d1d-befc-f9676aabb519
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815347384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.815347384
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1351603377
Short name T715
Test name
Test status
Simulation time 77096453 ps
CPU time 0.71 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:40:58 PM PST 24
Peak memory 198324 kb
Host smart-240d50c6-4ef4-4387-b82b-8c995a1fba74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351603377 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1351603377
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2757803440
Short name T750
Test name
Test status
Simulation time 67123030 ps
CPU time 0.61 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 196080 kb
Host smart-5f243f3b-9ae9-4218-8c58-8756a8168738
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757803440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2757803440
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1300651222
Short name T733
Test name
Test status
Simulation time 50173646 ps
CPU time 0.6 seconds
Started Mar 05 12:41:09 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 194144 kb
Host smart-2cc89075-5676-432a-a12d-c41253855dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300651222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1300651222
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1028667455
Short name T764
Test name
Test status
Simulation time 200490785 ps
CPU time 0.79 seconds
Started Mar 05 12:41:10 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 196600 kb
Host smart-aaf0d894-e679-455a-a63e-140e8e6445aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028667455 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1028667455
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2982754095
Short name T774
Test name
Test status
Simulation time 79158257 ps
CPU time 1.81 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 198480 kb
Host smart-d127155e-5e8f-472c-aed1-c7f86855dd02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982754095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2982754095
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2583613969
Short name T823
Test name
Test status
Simulation time 133086435 ps
CPU time 0.82 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 198308 kb
Host smart-ad0194c5-4fe0-480f-b455-76780c79d3dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583613969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2583613969
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3893201143
Short name T737
Test name
Test status
Simulation time 24281934 ps
CPU time 0.78 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 198324 kb
Host smart-4cbc0643-2a89-4ed8-a97d-8b4617c0eef0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893201143 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3893201143
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2309554237
Short name T91
Test name
Test status
Simulation time 19869907 ps
CPU time 0.61 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 195364 kb
Host smart-86dc2dc8-7ea5-48a0-89d1-50a5284dce4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309554237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2309554237
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4098124114
Short name T736
Test name
Test status
Simulation time 13054932 ps
CPU time 0.6 seconds
Started Mar 05 12:41:04 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 194164 kb
Host smart-9face1f3-6c32-4caa-a984-899b7c825915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098124114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4098124114
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.115212573
Short name T811
Test name
Test status
Simulation time 173449968 ps
CPU time 0.87 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 198084 kb
Host smart-e96bc8e0-6a93-4976-9371-e3c7ca6edb04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115212573 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.115212573
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3199911987
Short name T822
Test name
Test status
Simulation time 399607528 ps
CPU time 1.86 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 198404 kb
Host smart-567ad4eb-3a46-4073-a430-901d3aa48c30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199911987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3199911987
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3885483830
Short name T47
Test name
Test status
Simulation time 125747376 ps
CPU time 0.87 seconds
Started Mar 05 12:41:08 PM PST 24
Finished Mar 05 12:41:09 PM PST 24
Peak memory 197556 kb
Host smart-cadcf5e5-8191-4073-ae1b-bc93c995de68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885483830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3885483830
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3790952608
Short name T773
Test name
Test status
Simulation time 28215834 ps
CPU time 1.23 seconds
Started Mar 05 12:41:07 PM PST 24
Finished Mar 05 12:41:08 PM PST 24
Peak memory 198464 kb
Host smart-6fd079d4-b991-494e-bd27-4c5f7a176a85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790952608 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3790952608
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.200411302
Short name T102
Test name
Test status
Simulation time 22127991 ps
CPU time 0.58 seconds
Started Mar 05 12:41:13 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 195084 kb
Host smart-4f3da329-796e-49d4-9c02-5e11e01fa43e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200411302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.200411302
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3664110833
Short name T755
Test name
Test status
Simulation time 29190918 ps
CPU time 0.6 seconds
Started Mar 05 12:41:12 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 194088 kb
Host smart-16793a73-583c-41f3-ab1b-59cb860dffdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664110833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3664110833
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.191500841
Short name T85
Test name
Test status
Simulation time 46030580 ps
CPU time 0.9 seconds
Started Mar 05 12:41:04 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 196812 kb
Host smart-cfd707cc-a42b-4270-b443-514f9a7c22df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191500841 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.191500841
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3514447332
Short name T810
Test name
Test status
Simulation time 1785515895 ps
CPU time 2.47 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:02 PM PST 24
Peak memory 198492 kb
Host smart-3a4e7409-4bd4-4398-958a-ba0bc0861742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514447332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3514447332
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1889494393
Short name T104
Test name
Test status
Simulation time 340135598 ps
CPU time 1.36 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 198516 kb
Host smart-0cc41015-0f70-4d04-b355-f78e69ae798b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889494393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1889494393
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3151119853
Short name T788
Test name
Test status
Simulation time 25116749 ps
CPU time 0.81 seconds
Started Mar 05 12:41:13 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 198276 kb
Host smart-84c7389a-9a96-47b4-8277-61a98b0a9138
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151119853 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3151119853
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4021912956
Short name T94
Test name
Test status
Simulation time 14954026 ps
CPU time 0.6 seconds
Started Mar 05 12:41:10 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 195564 kb
Host smart-5e83dbff-e34f-4da5-8b51-3412505a7bb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021912956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4021912956
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.4204008101
Short name T831
Test name
Test status
Simulation time 34139049 ps
CPU time 0.58 seconds
Started Mar 05 12:41:10 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 194100 kb
Host smart-ea1764da-e0d2-47a3-adff-7c4239db66c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204008101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.4204008101
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2163088773
Short name T801
Test name
Test status
Simulation time 29079305 ps
CPU time 0.83 seconds
Started Mar 05 12:41:09 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 196840 kb
Host smart-9d5ea5f7-1e84-493b-9bc6-beae0058c58f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163088773 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2163088773
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1185276938
Short name T824
Test name
Test status
Simulation time 163057217 ps
CPU time 1.54 seconds
Started Mar 05 12:41:02 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 198440 kb
Host smart-8bafd278-2ca7-41a9-b923-cd9123d2f6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185276938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1185276938
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1804842874
Short name T50
Test name
Test status
Simulation time 198989064 ps
CPU time 0.89 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 197484 kb
Host smart-0c0999cf-5907-4370-9c94-7978d1756ac1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804842874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1804842874
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2721899199
Short name T766
Test name
Test status
Simulation time 19739783 ps
CPU time 0.64 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 194716 kb
Host smart-a122c5cd-982c-490b-8143-099928ac2801
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721899199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2721899199
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.559924911
Short name T821
Test name
Test status
Simulation time 181299293 ps
CPU time 2.5 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 198392 kb
Host smart-ca2a4f53-a676-4798-be54-d326c69a684e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559924911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.559924911
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2687980230
Short name T769
Test name
Test status
Simulation time 18153293 ps
CPU time 0.62 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 195048 kb
Host smart-2cd5c035-775a-4431-81cc-07693a24e42a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687980230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2687980230
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1787909935
Short name T714
Test name
Test status
Simulation time 21823718 ps
CPU time 0.7 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 198272 kb
Host smart-d1468155-826d-49d6-a180-c585d9950afd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787909935 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1787909935
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.80315714
Short name T92
Test name
Test status
Simulation time 34819128 ps
CPU time 0.57 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 193720 kb
Host smart-60f3bf06-ccc5-42ec-a596-ff968fdf8e78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80315714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.80315714
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1307116951
Short name T829
Test name
Test status
Simulation time 47797373 ps
CPU time 0.56 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 194144 kb
Host smart-1c7e8ab8-f56d-4bce-b422-9a9eb56aeee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307116951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1307116951
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3369745500
Short name T792
Test name
Test status
Simulation time 18734412 ps
CPU time 0.8 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 196988 kb
Host smart-bd060272-d7f7-49d6-b55a-74d759acda86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369745500 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3369745500
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1208940629
Short name T734
Test name
Test status
Simulation time 54964560 ps
CPU time 2.74 seconds
Started Mar 05 12:41:01 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 198440 kb
Host smart-82a18dd8-5e57-4479-98b5-8cb75af2a365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208940629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1208940629
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2903945471
Short name T827
Test name
Test status
Simulation time 69082026 ps
CPU time 1.04 seconds
Started Mar 05 12:40:47 PM PST 24
Finished Mar 05 12:40:48 PM PST 24
Peak memory 197880 kb
Host smart-31790929-168d-458d-8078-97427ef2424f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903945471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2903945471
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2310711188
Short name T798
Test name
Test status
Simulation time 48211251 ps
CPU time 0.58 seconds
Started Mar 05 12:41:15 PM PST 24
Finished Mar 05 12:41:16 PM PST 24
Peak memory 194756 kb
Host smart-46ea23c0-bc98-46c0-a61b-f302a134d21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310711188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2310711188
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.130359670
Short name T768
Test name
Test status
Simulation time 37525610 ps
CPU time 0.56 seconds
Started Mar 05 12:41:14 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 194004 kb
Host smart-3bda835a-d11b-4253-a614-f0d2036cba93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130359670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.130359670
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4262075868
Short name T738
Test name
Test status
Simulation time 12266902 ps
CPU time 0.56 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 194764 kb
Host smart-650f788f-610a-431b-ad7e-da7d1a2ad8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262075868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4262075868
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2056484736
Short name T756
Test name
Test status
Simulation time 44550345 ps
CPU time 0.57 seconds
Started Mar 05 12:41:02 PM PST 24
Finished Mar 05 12:41:03 PM PST 24
Peak memory 194180 kb
Host smart-f45e0e62-14f6-4e99-bf08-4b3512e937d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056484736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2056484736
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.764738822
Short name T806
Test name
Test status
Simulation time 63126926 ps
CPU time 0.56 seconds
Started Mar 05 12:41:17 PM PST 24
Finished Mar 05 12:41:18 PM PST 24
Peak memory 194756 kb
Host smart-bcc09757-b324-416e-99e2-e01743dc7fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764738822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.764738822
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2009087266
Short name T789
Test name
Test status
Simulation time 64436867 ps
CPU time 0.59 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 194136 kb
Host smart-5f39962e-af78-403c-802d-6c7337e2c612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009087266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2009087266
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.643370028
Short name T782
Test name
Test status
Simulation time 13464921 ps
CPU time 0.57 seconds
Started Mar 05 12:40:51 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 194068 kb
Host smart-f68ab538-1052-44f5-91e8-6da683cc5ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643370028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.643370028
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3263154956
Short name T732
Test name
Test status
Simulation time 35719443 ps
CPU time 0.58 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 194220 kb
Host smart-d2ee7a7d-57ef-4bd0-a1b4-cb2b0861640a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263154956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3263154956
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2599925912
Short name T772
Test name
Test status
Simulation time 13174899 ps
CPU time 0.63 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:06 PM PST 24
Peak memory 194076 kb
Host smart-237f9fe8-027a-47e4-9434-4fc65ad40b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599925912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2599925912
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1206983973
Short name T762
Test name
Test status
Simulation time 13652449 ps
CPU time 0.59 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:40:38 PM PST 24
Peak memory 194204 kb
Host smart-f4f5a88b-e3cb-4532-87ca-6cc04de8d60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206983973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1206983973
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3824371521
Short name T741
Test name
Test status
Simulation time 63227497 ps
CPU time 0.67 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 195504 kb
Host smart-b98339d5-a416-4e40-aa09-df0b862fb639
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824371521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3824371521
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2751197423
Short name T78
Test name
Test status
Simulation time 314726503 ps
CPU time 2.89 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 198424 kb
Host smart-3329da4c-409b-4541-99cc-6b9ef390fffd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751197423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2751197423
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3129521207
Short name T758
Test name
Test status
Simulation time 34132500 ps
CPU time 0.65 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 195404 kb
Host smart-85cffd97-1892-44a1-bdf9-b1a5497ca5ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129521207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3129521207
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3591586508
Short name T820
Test name
Test status
Simulation time 71258064 ps
CPU time 0.98 seconds
Started Mar 05 12:40:41 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 198392 kb
Host smart-6cc01099-bea7-4bab-871b-1aeef833207d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591586508 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3591586508
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.104098827
Short name T781
Test name
Test status
Simulation time 13846792 ps
CPU time 0.57 seconds
Started Mar 05 12:40:41 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 195016 kb
Host smart-50188186-84a8-44ac-a2a7-4166811cf93d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104098827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.104098827
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3890179762
Short name T723
Test name
Test status
Simulation time 14677652 ps
CPU time 0.6 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 194164 kb
Host smart-f734c8a1-a0d2-4016-92e8-8172f72e2f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890179762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3890179762
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3678760392
Short name T81
Test name
Test status
Simulation time 61049964 ps
CPU time 0.83 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 197444 kb
Host smart-d6b9340c-8bba-4123-a84e-01ad9cda9d71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678760392 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3678760392
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3199072429
Short name T786
Test name
Test status
Simulation time 242928211 ps
CPU time 1.56 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:57 PM PST 24
Peak memory 198480 kb
Host smart-5e1ddd5c-80da-4a38-82a8-03264c51ec85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199072429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3199072429
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2302347133
Short name T46
Test name
Test status
Simulation time 332793107 ps
CPU time 1.39 seconds
Started Mar 05 12:41:04 PM PST 24
Finished Mar 05 12:41:07 PM PST 24
Peak memory 198504 kb
Host smart-c24ca815-50e1-4318-a32d-432ff104c2f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302347133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2302347133
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3787829123
Short name T803
Test name
Test status
Simulation time 25349707 ps
CPU time 0.63 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 194208 kb
Host smart-f4b5fa9b-2557-4581-b515-4365a5bb3fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787829123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3787829123
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1804243468
Short name T799
Test name
Test status
Simulation time 15996111 ps
CPU time 0.63 seconds
Started Mar 05 12:41:06 PM PST 24
Finished Mar 05 12:41:07 PM PST 24
Peak memory 194828 kb
Host smart-f04d6d22-a18f-4c31-9d36-af2276876650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804243468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1804243468
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2120259441
Short name T745
Test name
Test status
Simulation time 44666753 ps
CPU time 0.57 seconds
Started Mar 05 12:40:47 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 194808 kb
Host smart-1284900a-27bd-45b1-87a1-87ec36cd2015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120259441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2120259441
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.417825938
Short name T754
Test name
Test status
Simulation time 46462396 ps
CPU time 0.57 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 194844 kb
Host smart-39d10c6c-7329-4932-9ae9-7a537738c33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417825938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.417825938
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.109408192
Short name T791
Test name
Test status
Simulation time 13172890 ps
CPU time 0.57 seconds
Started Mar 05 12:41:02 PM PST 24
Finished Mar 05 12:41:03 PM PST 24
Peak memory 194080 kb
Host smart-a624edb8-4ba4-425a-a883-a248fd688cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109408192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.109408192
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3995965755
Short name T711
Test name
Test status
Simulation time 47232160 ps
CPU time 0.6 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 194772 kb
Host smart-85ff9085-c88b-46c0-8626-bfe5701b8af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995965755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3995965755
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3675905773
Short name T819
Test name
Test status
Simulation time 20342670 ps
CPU time 0.58 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 194068 kb
Host smart-211a0f84-3d53-42be-92c5-e10f583b31a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675905773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3675905773
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.860800513
Short name T833
Test name
Test status
Simulation time 23725783 ps
CPU time 0.59 seconds
Started Mar 05 12:41:05 PM PST 24
Finished Mar 05 12:41:06 PM PST 24
Peak memory 194064 kb
Host smart-12175f07-3c35-4243-80c7-9e134bf80312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860800513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.860800513
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.858536339
Short name T743
Test name
Test status
Simulation time 16987601 ps
CPU time 0.61 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 194192 kb
Host smart-796b34e6-05ff-4523-ace8-db253e066a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858536339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.858536339
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3882987775
Short name T706
Test name
Test status
Simulation time 18726411 ps
CPU time 0.63 seconds
Started Mar 05 12:41:15 PM PST 24
Finished Mar 05 12:41:17 PM PST 24
Peak memory 194192 kb
Host smart-0c36de65-3d1f-4d46-b3fa-01acf703b57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882987775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3882987775
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.905084382
Short name T82
Test name
Test status
Simulation time 14589755 ps
CPU time 0.76 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:40:58 PM PST 24
Peak memory 196780 kb
Host smart-ed8f4689-e494-4f64-afbb-6bdcbb485ccb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905084382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.905084382
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1086783452
Short name T95
Test name
Test status
Simulation time 325903129 ps
CPU time 3.33 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:57 PM PST 24
Peak memory 198404 kb
Host smart-61628f14-0228-4ec6-90df-4bfc98fae051
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086783452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1086783452
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1233731333
Short name T731
Test name
Test status
Simulation time 46016726 ps
CPU time 0.57 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 194800 kb
Host smart-dd27c0fe-c883-4d9c-9d59-95ee05d0222b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233731333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1233731333
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1322143040
Short name T793
Test name
Test status
Simulation time 87952520 ps
CPU time 1.38 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:57 PM PST 24
Peak memory 198524 kb
Host smart-d80d0d9b-e784-4a95-a49e-16de2aeb648f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322143040 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1322143040
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4234597484
Short name T817
Test name
Test status
Simulation time 80890572 ps
CPU time 0.58 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 194164 kb
Host smart-a91eb299-c3b9-4bbe-adfa-0f02c018a941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234597484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4234597484
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4184465610
Short name T800
Test name
Test status
Simulation time 35631060 ps
CPU time 0.82 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 196728 kb
Host smart-00bb69fc-7c74-4781-afca-1152db692d65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184465610 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4184465610
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1532878778
Short name T713
Test name
Test status
Simulation time 196751998 ps
CPU time 1.33 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 198472 kb
Host smart-ff9d03c7-b87d-424c-b56d-d8998f24e039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532878778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1532878778
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2777813823
Short name T809
Test name
Test status
Simulation time 43366311 ps
CPU time 0.85 seconds
Started Mar 05 12:40:47 PM PST 24
Finished Mar 05 12:40:48 PM PST 24
Peak memory 197368 kb
Host smart-52217492-de1b-49df-9f55-dc8ca4fe9fc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777813823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2777813823
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.96620108
Short name T797
Test name
Test status
Simulation time 48943887 ps
CPU time 0.6 seconds
Started Mar 05 12:41:04 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 194180 kb
Host smart-1c1ae9c3-f21e-4706-bcc5-cea60a0c5b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96620108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.96620108
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1413786018
Short name T722
Test name
Test status
Simulation time 162855817 ps
CPU time 0.58 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 194152 kb
Host smart-b7c6424b-d6e5-4947-a888-86a71ac5b311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413786018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1413786018
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2625035951
Short name T779
Test name
Test status
Simulation time 17135255 ps
CPU time 0.59 seconds
Started Mar 05 12:41:13 PM PST 24
Finished Mar 05 12:41:15 PM PST 24
Peak memory 194136 kb
Host smart-9e6a4492-289c-4e93-93e5-a62dbd109d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625035951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2625035951
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1011849576
Short name T735
Test name
Test status
Simulation time 15980905 ps
CPU time 0.63 seconds
Started Mar 05 12:40:58 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 194196 kb
Host smart-f98c78c9-3556-4a65-9e9e-6a84cfb1db89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011849576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1011849576
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1261836553
Short name T739
Test name
Test status
Simulation time 16935646 ps
CPU time 0.63 seconds
Started Mar 05 12:41:09 PM PST 24
Finished Mar 05 12:41:10 PM PST 24
Peak memory 194148 kb
Host smart-0a769933-9f4a-41d5-9f92-31216bd50b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261836553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1261836553
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2941974191
Short name T771
Test name
Test status
Simulation time 30433441 ps
CPU time 0.66 seconds
Started Mar 05 12:40:51 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 194868 kb
Host smart-cfa2d77d-10a4-4ed1-b047-c410e8e6e512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941974191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2941974191
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2673491598
Short name T780
Test name
Test status
Simulation time 96077808 ps
CPU time 0.6 seconds
Started Mar 05 12:41:04 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 194096 kb
Host smart-30ba1198-71a3-4ba2-b47b-596a107a6b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673491598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2673491598
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4280995997
Short name T751
Test name
Test status
Simulation time 13128384 ps
CPU time 0.58 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 194164 kb
Host smart-bfbd7030-11c1-4384-b170-ebfe80cad629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280995997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4280995997
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4129279543
Short name T761
Test name
Test status
Simulation time 28097935 ps
CPU time 0.62 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 194132 kb
Host smart-e3257086-19e9-4636-b3f4-f3a6e34ba39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129279543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4129279543
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2954797345
Short name T705
Test name
Test status
Simulation time 16039633 ps
CPU time 0.59 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:40:53 PM PST 24
Peak memory 194196 kb
Host smart-cfe74cdd-6b2b-40d9-9d10-de1bc747db1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954797345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2954797345
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3645148932
Short name T796
Test name
Test status
Simulation time 101427209 ps
CPU time 1.28 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 198580 kb
Host smart-35f31f12-f727-4473-ac65-fe910b46fd2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645148932 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3645148932
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2586038229
Short name T89
Test name
Test status
Simulation time 71142939 ps
CPU time 0.63 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 195176 kb
Host smart-93236ae0-1df1-4e71-85fd-a4c17d1bda02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586038229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2586038229
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2615355969
Short name T760
Test name
Test status
Simulation time 37273979 ps
CPU time 0.66 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 194836 kb
Host smart-0dac2101-4c27-4849-af59-3315bddfd4ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615355969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2615355969
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4218053568
Short name T86
Test name
Test status
Simulation time 15689831 ps
CPU time 0.63 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 195012 kb
Host smart-c2a88e71-6df6-4d1d-b4ba-e817e23d1d14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218053568 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4218053568
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3625383674
Short name T765
Test name
Test status
Simulation time 134277074 ps
CPU time 1.95 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 198508 kb
Host smart-e834d499-3867-4f93-b08d-fd7152e3e11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625383674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3625383674
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3170946034
Short name T815
Test name
Test status
Simulation time 153149791 ps
CPU time 0.9 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 197680 kb
Host smart-ceda7275-b120-4814-ac4f-19a32bdbc329
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170946034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3170946034
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2910154502
Short name T807
Test name
Test status
Simulation time 24126954 ps
CPU time 0.73 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 198412 kb
Host smart-284097a3-c825-43de-a0a8-8887d7da91ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910154502 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2910154502
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3394855289
Short name T724
Test name
Test status
Simulation time 41960426 ps
CPU time 0.61 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 195120 kb
Host smart-c10a39bb-2f97-4e29-9282-e37a2459d109
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394855289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3394855289
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1552901197
Short name T708
Test name
Test status
Simulation time 14781749 ps
CPU time 0.59 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 194176 kb
Host smart-c712bb10-b716-494f-9dda-d743c24ddc47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552901197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1552901197
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.867492646
Short name T770
Test name
Test status
Simulation time 440051166 ps
CPU time 0.88 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 197928 kb
Host smart-a0fd65cb-c022-4c18-a4e8-a5072884a770
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867492646 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.867492646
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2048008992
Short name T729
Test name
Test status
Simulation time 62860882 ps
CPU time 2.4 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 198488 kb
Host smart-a709d8b5-8de3-4968-98aa-d7fff538618e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048008992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2048008992
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3577883742
Short name T785
Test name
Test status
Simulation time 84953867 ps
CPU time 1.12 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 198528 kb
Host smart-7d647033-8d4c-4c63-b2f7-e8d29a661356
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577883742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3577883742
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4131629373
Short name T825
Test name
Test status
Simulation time 57890567 ps
CPU time 1.31 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 198584 kb
Host smart-93db045a-0483-4a38-999c-afe567018e81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131629373 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4131629373
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2521395364
Short name T88
Test name
Test status
Simulation time 16845576 ps
CPU time 0.63 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:40:32 PM PST 24
Peak memory 195336 kb
Host smart-b953ee84-da06-45a6-a33d-c720801483bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521395364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2521395364
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.742395098
Short name T740
Test name
Test status
Simulation time 40677195 ps
CPU time 0.55 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 194112 kb
Host smart-d1fea39d-6142-4fc0-b98a-44a320cc1543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742395098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.742395098
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2129149670
Short name T812
Test name
Test status
Simulation time 218067881 ps
CPU time 0.66 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 195284 kb
Host smart-8fa4401c-73f4-448f-9bdb-d2cea77c35ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129149670 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2129149670
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.991561641
Short name T802
Test name
Test status
Simulation time 581359950 ps
CPU time 2.87 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 198600 kb
Host smart-015c37a8-dc6b-4d0e-99c3-259d1d576290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991561641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.991561641
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3288253836
Short name T747
Test name
Test status
Simulation time 423620206 ps
CPU time 0.87 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:37 PM PST 24
Peak memory 198400 kb
Host smart-a8afbcd3-3bb8-406f-9a57-aa20610ee688
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288253836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3288253836
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2234453947
Short name T721
Test name
Test status
Simulation time 135374895 ps
CPU time 1.04 seconds
Started Mar 05 12:41:01 PM PST 24
Finished Mar 05 12:41:02 PM PST 24
Peak memory 198492 kb
Host smart-d173e040-50de-41d1-a5e8-647758232722
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234453947 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2234453947
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2586963517
Short name T795
Test name
Test status
Simulation time 35239773 ps
CPU time 0.58 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 195740 kb
Host smart-ef53e5e1-b09b-4234-95bf-af440407d8c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586963517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2586963517
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1915790322
Short name T784
Test name
Test status
Simulation time 49868775 ps
CPU time 0.62 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 194312 kb
Host smart-b754f00e-8690-4a45-9e13-66fe9d904dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915790322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1915790322
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3261047977
Short name T100
Test name
Test status
Simulation time 33844237 ps
CPU time 0.66 seconds
Started Mar 05 12:40:58 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 195784 kb
Host smart-4c6bb974-0dea-4116-a6b3-459a39ca57d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261047977 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3261047977
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2407234656
Short name T834
Test name
Test status
Simulation time 111845156 ps
CPU time 2.31 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:43 PM PST 24
Peak memory 198508 kb
Host smart-3088fb23-ae09-4924-8a6c-8ab38b0a136f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407234656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2407234656
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.152751841
Short name T48
Test name
Test status
Simulation time 49431273 ps
CPU time 0.89 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:40:32 PM PST 24
Peak memory 197640 kb
Host smart-4c79d606-df7f-4d3c-addf-c18b2fadc9b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152751841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.152751841
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4044273953
Short name T707
Test name
Test status
Simulation time 150429910 ps
CPU time 0.96 seconds
Started Mar 05 12:41:09 PM PST 24
Finished Mar 05 12:41:10 PM PST 24
Peak memory 198428 kb
Host smart-cb130c8a-d83a-463e-99d9-502a608377c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044273953 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4044273953
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1348040741
Short name T742
Test name
Test status
Simulation time 11874336 ps
CPU time 0.58 seconds
Started Mar 05 12:40:41 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 195008 kb
Host smart-e898a0ec-ff64-4a05-bdaa-82cbe360486f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348040741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1348040741
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3431862895
Short name T759
Test name
Test status
Simulation time 14669148 ps
CPU time 0.59 seconds
Started Mar 05 12:40:59 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 194156 kb
Host smart-823bf91a-f8d3-434e-9ae5-81d897effce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431862895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3431862895
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1510786075
Short name T101
Test name
Test status
Simulation time 34113699 ps
CPU time 0.8 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 196548 kb
Host smart-a2200ea4-b5d1-46b2-a65d-e49b36cda22b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510786075 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1510786075
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2710782397
Short name T718
Test name
Test status
Simulation time 94832592 ps
CPU time 2.4 seconds
Started Mar 05 12:40:51 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 198440 kb
Host smart-276d19d8-7d59-41ff-8fec-5d40e7033734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710782397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2710782397
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2476151042
Short name T728
Test name
Test status
Simulation time 648880037 ps
CPU time 1.16 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 198512 kb
Host smart-30316a9e-5682-4968-8ba3-b524b3e2fb07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476151042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2476151042
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1475608324
Short name T190
Test name
Test status
Simulation time 19312059 ps
CPU time 0.56 seconds
Started Mar 05 12:58:58 PM PST 24
Finished Mar 05 12:58:58 PM PST 24
Peak memory 194100 kb
Host smart-c1bb6f92-52b0-43b8-bd66-c85e102fbb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475608324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1475608324
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2690786592
Short name T383
Test name
Test status
Simulation time 35105584 ps
CPU time 0.81 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:42 PM PST 24
Peak memory 196364 kb
Host smart-29382af4-baa7-4d25-8fcc-d3b528ba7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690786592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2690786592
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.467188831
Short name T117
Test name
Test status
Simulation time 565194260 ps
CPU time 7.35 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:49 PM PST 24
Peak memory 196972 kb
Host smart-1df699ab-24a7-4f2f-b109-5b403b2fd092
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467188831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.467188831
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3943480612
Short name T31
Test name
Test status
Simulation time 63609794 ps
CPU time 0.92 seconds
Started Mar 05 12:58:42 PM PST 24
Finished Mar 05 12:58:43 PM PST 24
Peak memory 196908 kb
Host smart-9891fd3f-b08a-4134-b343-31c8f98354ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943480612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3943480612
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.155526383
Short name T109
Test name
Test status
Simulation time 218825313 ps
CPU time 0.93 seconds
Started Mar 05 12:58:43 PM PST 24
Finished Mar 05 12:58:44 PM PST 24
Peak memory 195988 kb
Host smart-7c2efb1a-b33e-4e0a-b625-e7de9050dd14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155526383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.155526383
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1298045663
Short name T160
Test name
Test status
Simulation time 307183387 ps
CPU time 2.97 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:44 PM PST 24
Peak memory 197992 kb
Host smart-84adbbfe-6323-4d9f-81b6-a7880705cb7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298045663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1298045663
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4119370602
Short name T571
Test name
Test status
Simulation time 406643286 ps
CPU time 2.21 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:44 PM PST 24
Peak memory 197600 kb
Host smart-43231643-5ec3-4b1a-b309-79523de455f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119370602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4119370602
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4012900220
Short name T172
Test name
Test status
Simulation time 27335600 ps
CPU time 0.77 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:42 PM PST 24
Peak memory 196680 kb
Host smart-f5e078fd-47fa-43be-8425-05284ade4d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012900220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4012900220
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3149768319
Short name T704
Test name
Test status
Simulation time 291458666 ps
CPU time 0.81 seconds
Started Mar 05 12:58:41 PM PST 24
Finished Mar 05 12:58:42 PM PST 24
Peak memory 196644 kb
Host smart-38af3f48-ad4e-45ed-b381-8527164d4365
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149768319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3149768319
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2051782008
Short name T412
Test name
Test status
Simulation time 1547746026 ps
CPU time 5.62 seconds
Started Mar 05 12:58:42 PM PST 24
Finished Mar 05 12:58:48 PM PST 24
Peak memory 198120 kb
Host smart-b5c0da5e-d7fa-40cb-90e6-3e66f70e8150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051782008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2051782008
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3521298192
Short name T51
Test name
Test status
Simulation time 289852706 ps
CPU time 0.93 seconds
Started Mar 05 12:58:57 PM PST 24
Finished Mar 05 12:58:58 PM PST 24
Peak memory 215024 kb
Host smart-7d43b859-065d-4500-8baa-2336361751b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521298192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3521298192
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.423233741
Short name T60
Test name
Test status
Simulation time 87141822 ps
CPU time 0.99 seconds
Started Mar 05 12:58:38 PM PST 24
Finished Mar 05 12:58:39 PM PST 24
Peak memory 196368 kb
Host smart-61a01da6-248d-4369-bb3b-104ce8d63345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423233741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.423233741
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.619057955
Short name T632
Test name
Test status
Simulation time 47242222 ps
CPU time 1.36 seconds
Started Mar 05 12:58:45 PM PST 24
Finished Mar 05 12:58:47 PM PST 24
Peak memory 196784 kb
Host smart-610cd0a2-1a3b-4e40-a7de-c237d37e99cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619057955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.619057955
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1072670029
Short name T237
Test name
Test status
Simulation time 20017410077 ps
CPU time 240.87 seconds
Started Mar 05 12:58:42 PM PST 24
Finished Mar 05 01:02:43 PM PST 24
Peak memory 198344 kb
Host smart-33252474-d7a9-400e-bb6d-06a9b4c5f64c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072670029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1072670029
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3670533506
Short name T179
Test name
Test status
Simulation time 15030810 ps
CPU time 0.55 seconds
Started Mar 05 12:58:51 PM PST 24
Finished Mar 05 12:58:52 PM PST 24
Peak memory 194096 kb
Host smart-1baa2031-a30b-4066-8f69-75f9a3920105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670533506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3670533506
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4121389895
Short name T397
Test name
Test status
Simulation time 20109610 ps
CPU time 0.69 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 194176 kb
Host smart-d2265e0a-6d4a-40f1-bf13-8b7a36756901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121389895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4121389895
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1063558345
Short name T502
Test name
Test status
Simulation time 927453634 ps
CPU time 12.03 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:59:06 PM PST 24
Peak memory 196424 kb
Host smart-b54bf9ba-f048-42ec-b69c-0b0da171c411
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063558345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1063558345
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.776863382
Short name T180
Test name
Test status
Simulation time 133440337 ps
CPU time 1.05 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:53 PM PST 24
Peak memory 196720 kb
Host smart-a99d2721-2144-4c9d-9770-7001560b8403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776863382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.776863382
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.693314209
Short name T335
Test name
Test status
Simulation time 193292091 ps
CPU time 1.09 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195924 kb
Host smart-1cd5395d-d131-46d4-ac40-c608174a53a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693314209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.693314209
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1905978720
Short name T367
Test name
Test status
Simulation time 163478080 ps
CPU time 3.28 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 196464 kb
Host smart-1384347d-133b-4f94-9cbf-98b669aaa78a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905978720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1905978720
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1828038935
Short name T205
Test name
Test status
Simulation time 106509040 ps
CPU time 2.14 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 196108 kb
Host smart-d049b083-8b50-423e-a09a-5dc4e5891448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828038935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1828038935
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3723261301
Short name T526
Test name
Test status
Simulation time 15565361 ps
CPU time 0.7 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 196200 kb
Host smart-e356b765-e0a7-4973-91dd-25de84f83d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723261301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3723261301
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2821038537
Short name T289
Test name
Test status
Simulation time 74152506 ps
CPU time 0.75 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 195488 kb
Host smart-cabfa35d-4d20-41e7-96ff-eedf12b01161
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821038537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2821038537
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3162014347
Short name T166
Test name
Test status
Simulation time 733673838 ps
CPU time 5.62 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:59 PM PST 24
Peak memory 198068 kb
Host smart-517532e3-d218-4b58-9476-b842032bfe90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162014347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3162014347
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.808848726
Short name T52
Test name
Test status
Simulation time 36391579 ps
CPU time 0.81 seconds
Started Mar 05 12:58:58 PM PST 24
Finished Mar 05 12:58:59 PM PST 24
Peak memory 213796 kb
Host smart-9b3277d0-e643-4573-90ea-1719eae4dad4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808848726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.808848726
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3165922356
Short name T639
Test name
Test status
Simulation time 41810756 ps
CPU time 1.33 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:56 PM PST 24
Peak memory 198120 kb
Host smart-fa20cd90-625c-4930-8ccb-5cf5f54e4a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165922356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3165922356
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.281914290
Short name T494
Test name
Test status
Simulation time 67527869 ps
CPU time 1.17 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:53 PM PST 24
Peak memory 195908 kb
Host smart-ba3e0ae1-5bde-4f6d-847e-25bf915a97fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281914290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.281914290
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.700939463
Short name T658
Test name
Test status
Simulation time 50146458598 ps
CPU time 159.35 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 01:01:33 PM PST 24
Peak memory 198360 kb
Host smart-b060fb50-dde4-4960-9f60-306e344c3f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700939463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.700939463
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1901855072
Short name T371
Test name
Test status
Simulation time 36323101 ps
CPU time 0.56 seconds
Started Mar 05 12:59:30 PM PST 24
Finished Mar 05 12:59:31 PM PST 24
Peak memory 194996 kb
Host smart-92bb2947-a072-4593-9e65-bc7971bff65e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901855072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1901855072
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3185864596
Short name T424
Test name
Test status
Simulation time 63383337 ps
CPU time 0.85 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 195336 kb
Host smart-36775a04-fb26-46e9-bc66-c2250cb31a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185864596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3185864596
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3151569158
Short name T185
Test name
Test status
Simulation time 1117706361 ps
CPU time 19.37 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 196832 kb
Host smart-5539dead-bd7c-462d-867d-f900331eb347
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151569158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3151569158
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3984917989
Short name T530
Test name
Test status
Simulation time 222422668 ps
CPU time 0.79 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 195812 kb
Host smart-d756e7db-178c-4c4d-8682-699d621c30ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984917989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3984917989
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4102888664
Short name T518
Test name
Test status
Simulation time 51823717 ps
CPU time 1.26 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 195808 kb
Host smart-471cdd02-17b2-41dd-a7ad-d502091c2c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102888664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4102888664
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3645188479
Short name T451
Test name
Test status
Simulation time 338827162 ps
CPU time 3 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:37 PM PST 24
Peak memory 198208 kb
Host smart-e6b176f2-db60-470b-a321-36912b9aa159
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645188479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3645188479
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.950152846
Short name T460
Test name
Test status
Simulation time 149066465 ps
CPU time 3.24 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:37 PM PST 24
Peak memory 195900 kb
Host smart-e26517b7-a1df-4c61-a7d3-0e0f358d5bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950152846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
950152846
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3171622952
Short name T388
Test name
Test status
Simulation time 66934399 ps
CPU time 1.33 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 197084 kb
Host smart-f7743f97-3502-4f95-a077-183ecc5486bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171622952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3171622952
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1350555209
Short name T418
Test name
Test status
Simulation time 24114783 ps
CPU time 0.95 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 196064 kb
Host smart-18bdd94b-883f-43fe-bad4-c40fc3a26ffe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350555209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1350555209
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1401147915
Short name T59
Test name
Test status
Simulation time 227502788 ps
CPU time 1.35 seconds
Started Mar 05 12:59:34 PM PST 24
Finished Mar 05 12:59:36 PM PST 24
Peak memory 198144 kb
Host smart-0515ae96-7ee4-4e71-b67a-7b1439c9596a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401147915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1401147915
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.996107374
Short name T643
Test name
Test status
Simulation time 49904383 ps
CPU time 1.01 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 195900 kb
Host smart-7a03b539-29e0-443b-a9eb-3a97dbc0078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996107374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.996107374
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1895531059
Short name T322
Test name
Test status
Simulation time 25144036 ps
CPU time 0.86 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 195436 kb
Host smart-b9782bed-65cf-46bc-a365-43e5a1c09948
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895531059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1895531059
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1544816448
Short name T369
Test name
Test status
Simulation time 15599327907 ps
CPU time 176.99 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 01:02:28 PM PST 24
Peak memory 198300 kb
Host smart-dd6c8c10-b1c8-4cb5-bc01-7b82c49a7620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544816448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1544816448
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2846647071
Short name T699
Test name
Test status
Simulation time 15064100 ps
CPU time 0.57 seconds
Started Mar 05 12:59:38 PM PST 24
Finished Mar 05 12:59:39 PM PST 24
Peak memory 194148 kb
Host smart-009373c7-2284-41e3-99c4-b89ddacf93e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846647071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2846647071
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3185823064
Short name T515
Test name
Test status
Simulation time 33326390 ps
CPU time 0.77 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:34 PM PST 24
Peak memory 196076 kb
Host smart-25203606-7410-467f-906e-1b6b640e564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185823064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3185823064
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1543439082
Short name T413
Test name
Test status
Simulation time 165982262 ps
CPU time 5.2 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:37 PM PST 24
Peak memory 196112 kb
Host smart-3e097bd2-88dd-4580-b7ce-5575780bd8a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543439082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1543439082
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3809953822
Short name T474
Test name
Test status
Simulation time 576411410 ps
CPU time 0.93 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 196536 kb
Host smart-f0cbcb82-aba4-4140-9088-9d5453bd809f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809953822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3809953822
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.937505120
Short name T284
Test name
Test status
Simulation time 22922310 ps
CPU time 0.78 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:34 PM PST 24
Peak memory 195428 kb
Host smart-3581fcd2-d7cc-436b-a7e6-f3db36775a83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937505120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.937505120
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3469196618
Short name T479
Test name
Test status
Simulation time 70700980 ps
CPU time 0.98 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 196064 kb
Host smart-e38ca597-8731-49c2-b790-aa6706d81a3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469196618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3469196618
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3591248831
Short name T213
Test name
Test status
Simulation time 231546578 ps
CPU time 3.28 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:36 PM PST 24
Peak memory 198200 kb
Host smart-5effec64-bb44-48b9-b2bf-7f4642bc7a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591248831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3591248831
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.698748889
Short name T154
Test name
Test status
Simulation time 79593680 ps
CPU time 0.96 seconds
Started Mar 05 12:59:38 PM PST 24
Finished Mar 05 12:59:40 PM PST 24
Peak memory 196648 kb
Host smart-0440986f-5036-4560-bbbb-6bbb36b93915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698748889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.698748889
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2022860251
Short name T617
Test name
Test status
Simulation time 41877339 ps
CPU time 1.09 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:35 PM PST 24
Peak memory 196084 kb
Host smart-d05d5b87-d5de-427c-83c0-1430c04c5313
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022860251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2022860251
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2476605102
Short name T450
Test name
Test status
Simulation time 786509896 ps
CPU time 3.38 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:36 PM PST 24
Peak memory 198184 kb
Host smart-7f48845f-6412-4e48-97fa-b10560384b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476605102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2476605102
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3556336385
Short name T602
Test name
Test status
Simulation time 167655783 ps
CPU time 1.38 seconds
Started Mar 05 12:59:30 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 196792 kb
Host smart-8838546a-ff7c-4f5b-8dc3-348def09cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556336385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3556336385
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2602580177
Short name T177
Test name
Test status
Simulation time 131092565 ps
CPU time 1.47 seconds
Started Mar 05 12:59:30 PM PST 24
Finished Mar 05 12:59:32 PM PST 24
Peak memory 198124 kb
Host smart-01a98d92-4876-4277-9392-52f80679e41e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602580177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2602580177
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2702319228
Short name T696
Test name
Test status
Simulation time 14940978307 ps
CPU time 169.31 seconds
Started Mar 05 12:59:31 PM PST 24
Finished Mar 05 01:02:21 PM PST 24
Peak memory 198272 kb
Host smart-477139da-45af-47e3-8863-c0e191c4e7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702319228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2702319228
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.875660273
Short name T43
Test name
Test status
Simulation time 38632870 ps
CPU time 0.57 seconds
Started Mar 05 12:59:39 PM PST 24
Finished Mar 05 12:59:40 PM PST 24
Peak memory 194100 kb
Host smart-d0556ede-bb5e-4bda-bc31-29aa1efe56f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875660273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.875660273
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2535654689
Short name T345
Test name
Test status
Simulation time 33729522 ps
CPU time 0.81 seconds
Started Mar 05 12:59:40 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 195316 kb
Host smart-2bd44ed6-0266-4c37-ac70-5e4fff5dbd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535654689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2535654689
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2711675596
Short name T557
Test name
Test status
Simulation time 2580457892 ps
CPU time 21.91 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 01:00:06 PM PST 24
Peak memory 198268 kb
Host smart-0c10626f-dae0-4284-9675-573c048421bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711675596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2711675596
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.800113664
Short name T547
Test name
Test status
Simulation time 101164162 ps
CPU time 0.96 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:44 PM PST 24
Peak memory 197952 kb
Host smart-c0ce6bc9-e91a-4775-8507-59219652986a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800113664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.800113664
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2573373225
Short name T659
Test name
Test status
Simulation time 399838675 ps
CPU time 1.25 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:43 PM PST 24
Peak memory 196944 kb
Host smart-5525b59b-b136-4e2f-9fb3-b27200dc84de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573373225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2573373225
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3556930169
Short name T416
Test name
Test status
Simulation time 748174120 ps
CPU time 1.93 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 198220 kb
Host smart-b0b98387-f032-49d6-a53e-e6ca2053c58d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556930169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3556930169
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2714526245
Short name T417
Test name
Test status
Simulation time 77021485 ps
CPU time 2.24 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:47 PM PST 24
Peak memory 197372 kb
Host smart-232dacd4-f39f-46a2-a014-d24720a63c11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714526245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2714526245
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.953692931
Short name T623
Test name
Test status
Simulation time 24463210 ps
CPU time 0.68 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 194316 kb
Host smart-490236ec-24aa-4b19-9096-896cf4359e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953692931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.953692931
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4177944340
Short name T386
Test name
Test status
Simulation time 50492181 ps
CPU time 0.95 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:44 PM PST 24
Peak memory 196736 kb
Host smart-230ba267-2204-4a19-90f9-8afacfa9c711
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177944340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.4177944340
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1083362691
Short name T58
Test name
Test status
Simulation time 28930241 ps
CPU time 1.33 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 198012 kb
Host smart-3b53c143-aff9-4793-b9c2-d1744420f2cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083362691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1083362691
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1035576168
Short name T485
Test name
Test status
Simulation time 56539651 ps
CPU time 1.21 seconds
Started Mar 05 12:59:40 PM PST 24
Finished Mar 05 12:59:41 PM PST 24
Peak memory 195612 kb
Host smart-8efe97b2-d26d-410b-bfe2-d156fb176938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035576168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1035576168
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1751815066
Short name T248
Test name
Test status
Simulation time 32622773 ps
CPU time 0.93 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:43 PM PST 24
Peak memory 195640 kb
Host smart-a0b3f91d-23e0-47cb-840d-abc8468bbf53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751815066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1751815066
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3260104181
Short name T278
Test name
Test status
Simulation time 25677795603 ps
CPU time 91 seconds
Started Mar 05 12:59:48 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 198364 kb
Host smart-a0a7e294-ff15-423f-9dd0-6e0d2c0deaf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260104181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3260104181
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1787365558
Short name T34
Test name
Test status
Simulation time 903472796322 ps
CPU time 1359.81 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 01:22:22 PM PST 24
Peak memory 206664 kb
Host smart-34552048-8aff-49e3-b37c-c1e1db2cbce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1787365558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1787365558
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2960874390
Short name T361
Test name
Test status
Simulation time 11936598 ps
CPU time 0.59 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 194760 kb
Host smart-02be1efc-9178-4057-8789-389cf73e5598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960874390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2960874390
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4249362728
Short name T245
Test name
Test status
Simulation time 25842596 ps
CPU time 0.59 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 193876 kb
Host smart-5caa27b3-904d-4ba8-82c7-21dfa193d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249362728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4249362728
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2652805526
Short name T233
Test name
Test status
Simulation time 2796437608 ps
CPU time 22 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 01:00:07 PM PST 24
Peak memory 197220 kb
Host smart-7683fd46-9f54-4068-982b-c51676101e7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652805526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2652805526
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3165628941
Short name T14
Test name
Test status
Simulation time 53142579 ps
CPU time 0.76 seconds
Started Mar 05 12:59:40 PM PST 24
Finished Mar 05 12:59:41 PM PST 24
Peak memory 196028 kb
Host smart-0c761b9b-e4c9-4ffd-bf16-1271abc04958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165628941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3165628941
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3883714546
Short name T241
Test name
Test status
Simulation time 950228409 ps
CPU time 1.06 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:44 PM PST 24
Peak memory 196040 kb
Host smart-1c9b9057-4a83-405b-949a-9b45b3783751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883714546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3883714546
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2359210228
Short name T681
Test name
Test status
Simulation time 73875283 ps
CPU time 2.43 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:47 PM PST 24
Peak memory 198096 kb
Host smart-49b4dab4-5424-41ff-bfff-cb93f85a348c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359210228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2359210228
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3281230823
Short name T676
Test name
Test status
Simulation time 128443380 ps
CPU time 1.02 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:43 PM PST 24
Peak memory 195452 kb
Host smart-255819b2-dc20-453b-ba14-a1e2eef4cb43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281230823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3281230823
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.222284870
Short name T551
Test name
Test status
Simulation time 24592817 ps
CPU time 0.69 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 194324 kb
Host smart-cf7a8cb2-d8ca-43de-88dd-0348b3805b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222284870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.222284870
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1402472427
Short name T151
Test name
Test status
Simulation time 33650857 ps
CPU time 1.22 seconds
Started Mar 05 12:59:40 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 195940 kb
Host smart-cf876a23-2b16-448a-ace5-27e4bd855209
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402472427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1402472427
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2826730545
Short name T9
Test name
Test status
Simulation time 1090481065 ps
CPU time 5.42 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 198108 kb
Host smart-a52257b8-a27e-493c-8ae9-f9197ac3f24a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826730545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2826730545
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2986618744
Short name T469
Test name
Test status
Simulation time 525606945 ps
CPU time 1.42 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 196752 kb
Host smart-e55b82fd-153a-46b6-a163-f42cbbb66323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986618744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2986618744
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2162844735
Short name T288
Test name
Test status
Simulation time 29346753 ps
CPU time 0.88 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:44 PM PST 24
Peak memory 197172 kb
Host smart-c5fc0d1f-93f5-440d-880f-faf69f75447e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162844735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2162844735
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2200133468
Short name T372
Test name
Test status
Simulation time 9305194205 ps
CPU time 49.42 seconds
Started Mar 05 12:59:40 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 198364 kb
Host smart-46a9e1cc-e9be-402d-82f5-357fafc73750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200133468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2200133468
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3278373536
Short name T148
Test name
Test status
Simulation time 20574552 ps
CPU time 0.63 seconds
Started Mar 05 12:59:45 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 194108 kb
Host smart-31c4e0f4-ca42-4ec6-a801-a7abfe564131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278373536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3278373536
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2985973095
Short name T675
Test name
Test status
Simulation time 174197801 ps
CPU time 0.84 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 197352 kb
Host smart-6141cb3c-800b-455b-a340-f4484e075493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985973095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2985973095
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1882251987
Short name T168
Test name
Test status
Simulation time 726490786 ps
CPU time 24.31 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 01:00:07 PM PST 24
Peak memory 197080 kb
Host smart-f68c45c8-a744-4357-8b10-234f835fb9d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882251987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1882251987
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2829926582
Short name T420
Test name
Test status
Simulation time 106003928 ps
CPU time 0.98 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 197256 kb
Host smart-475b931d-cbc0-4d82-bbf6-1b66b91524ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829926582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2829926582
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3316671305
Short name T363
Test name
Test status
Simulation time 336544204 ps
CPU time 1.39 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 198172 kb
Host smart-3eaba152-45df-410b-94e7-373f5435d61b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316671305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3316671305
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2177455007
Short name T125
Test name
Test status
Simulation time 182742249 ps
CPU time 1.94 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 198016 kb
Host smart-b7d9cb8b-8f41-4f1b-9828-8ce5c98b3471
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177455007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2177455007
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3256896474
Short name T318
Test name
Test status
Simulation time 263103330 ps
CPU time 2.04 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 196964 kb
Host smart-4ec13458-f663-49cb-b482-44050016f234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256896474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3256896474
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1196934718
Short name T569
Test name
Test status
Simulation time 31143768 ps
CPU time 1.05 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 196228 kb
Host smart-1adbbd11-c0ee-439b-a940-0d50184ec0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196934718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1196934718
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3147811495
Short name T480
Test name
Test status
Simulation time 24028394 ps
CPU time 0.88 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 195572 kb
Host smart-8f39ee5c-e924-46c5-a41b-b2bc2fe72120
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147811495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3147811495
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3114993520
Short name T231
Test name
Test status
Simulation time 112663748 ps
CPU time 5.12 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:48 PM PST 24
Peak memory 198116 kb
Host smart-a18b3418-09d7-4067-a7b4-469ddc4033b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114993520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3114993520
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3017659748
Short name T216
Test name
Test status
Simulation time 137216869 ps
CPU time 1.05 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 196700 kb
Host smart-75a506c6-2de8-4fa6-aa3d-9218d7755d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017659748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3017659748
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1848433148
Short name T182
Test name
Test status
Simulation time 881737936 ps
CPU time 1.2 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:43 PM PST 24
Peak memory 196324 kb
Host smart-81dd983a-4d55-41e2-a307-5f01572cebd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848433148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1848433148
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3933339063
Short name T448
Test name
Test status
Simulation time 7258713276 ps
CPU time 177.94 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 01:02:41 PM PST 24
Peak memory 198336 kb
Host smart-f1e99a28-ee7d-46f4-8fc3-d352c40708a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933339063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3933339063
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.4114690267
Short name T63
Test name
Test status
Simulation time 99381015444 ps
CPU time 2282.44 seconds
Started Mar 05 12:59:45 PM PST 24
Finished Mar 05 01:37:48 PM PST 24
Peak memory 198452 kb
Host smart-0dba1d01-90ee-4d97-8207-d40b434cd0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4114690267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.4114690267
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1579336284
Short name T437
Test name
Test status
Simulation time 45285952 ps
CPU time 0.61 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 194996 kb
Host smart-d03c276d-a95a-45a8-9cc9-444c241c0ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579336284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1579336284
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2367612124
Short name T435
Test name
Test status
Simulation time 14504850 ps
CPU time 0.59 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 193904 kb
Host smart-9a0b85a8-37ee-41c8-94e0-d3ba72e8e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367612124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2367612124
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4028886731
Short name T176
Test name
Test status
Simulation time 4597885423 ps
CPU time 27.35 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 01:00:11 PM PST 24
Peak memory 197648 kb
Host smart-5200f86f-1ba5-4d03-a80c-dc9b0035cc77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028886731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4028886731
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.122825266
Short name T276
Test name
Test status
Simulation time 64865414 ps
CPU time 0.88 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 197248 kb
Host smart-6482e51b-69eb-4e65-9839-5925f9490f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122825266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.122825266
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2458652629
Short name T576
Test name
Test status
Simulation time 104072296 ps
CPU time 1.32 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 197224 kb
Host smart-66419eeb-4084-4860-bc9c-8fe6b2841bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458652629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2458652629
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1509072559
Short name T221
Test name
Test status
Simulation time 93343861 ps
CPU time 3.67 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:48 PM PST 24
Peak memory 198252 kb
Host smart-89a3c4e9-8cef-4cdf-8550-f7897788b9eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509072559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1509072559
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1617806468
Short name T193
Test name
Test status
Simulation time 183498229 ps
CPU time 1.59 seconds
Started Mar 05 12:59:45 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 196084 kb
Host smart-7f0e703d-9ed7-4412-98bf-101d68679f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617806468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1617806468
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.889591926
Short name T568
Test name
Test status
Simulation time 58445086 ps
CPU time 0.68 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 195004 kb
Host smart-62f52e38-4b03-4d0b-b8ad-6891634009e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889591926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.889591926
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2754188371
Short name T281
Test name
Test status
Simulation time 19994551 ps
CPU time 0.88 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 196696 kb
Host smart-46fc0695-0bec-4cab-ad03-063a578e323f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754188371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2754188371
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1899119231
Short name T471
Test name
Test status
Simulation time 118430968 ps
CPU time 2.12 seconds
Started Mar 05 12:59:42 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 198068 kb
Host smart-08666e2a-afde-49ac-bf2e-a8dccf7f1bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899119231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1899119231
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1672832686
Short name T504
Test name
Test status
Simulation time 560985010 ps
CPU time 1.45 seconds
Started Mar 05 12:59:41 PM PST 24
Finished Mar 05 12:59:42 PM PST 24
Peak memory 198092 kb
Host smart-4fdc9506-c1bb-42d9-b012-4b6b4a249304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672832686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1672832686
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1427669612
Short name T489
Test name
Test status
Simulation time 152467978 ps
CPU time 1.51 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 12:59:46 PM PST 24
Peak memory 196904 kb
Host smart-a110851c-05d9-40de-93f1-1e39f63259c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427669612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1427669612
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1640165423
Short name T111
Test name
Test status
Simulation time 19661057722 ps
CPU time 119.5 seconds
Started Mar 05 12:59:44 PM PST 24
Finished Mar 05 01:01:43 PM PST 24
Peak memory 198348 kb
Host smart-dd5432e2-95c0-4d5c-a9c0-58b266c4194d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640165423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1640165423
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3839336497
Short name T433
Test name
Test status
Simulation time 59388338 ps
CPU time 0.59 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 194308 kb
Host smart-d2c3036a-8e31-4f39-ab90-917533c50e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839336497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3839336497
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3990913317
Short name T338
Test name
Test status
Simulation time 18981779 ps
CPU time 0.62 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 194676 kb
Host smart-da760ca2-d4a9-4701-b7cc-1d6140c612de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990913317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3990913317
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2322753908
Short name T626
Test name
Test status
Simulation time 6187617294 ps
CPU time 10.35 seconds
Started Mar 05 12:59:48 PM PST 24
Finished Mar 05 12:59:58 PM PST 24
Peak memory 196700 kb
Host smart-a08974da-15ae-4583-b515-9bf8c8a0cc26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322753908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2322753908
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4146742975
Short name T470
Test name
Test status
Simulation time 33719312 ps
CPU time 0.68 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 12:59:55 PM PST 24
Peak memory 194668 kb
Host smart-2e487a97-e9e3-431e-97e0-1637132ade45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146742975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4146742975
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3138375392
Short name T332
Test name
Test status
Simulation time 100884382 ps
CPU time 1.41 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 12:59:55 PM PST 24
Peak memory 198172 kb
Host smart-e28b1984-536b-4743-a9fa-6baf375eb95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138375392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3138375392
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3882435542
Short name T13
Test name
Test status
Simulation time 413685937 ps
CPU time 2.78 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:52 PM PST 24
Peak memory 198172 kb
Host smart-dc97e27b-6068-4f88-8740-e27941458b72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882435542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3882435542
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.38644344
Short name T147
Test name
Test status
Simulation time 80543405 ps
CPU time 2.34 seconds
Started Mar 05 12:59:53 PM PST 24
Finished Mar 05 12:59:56 PM PST 24
Peak memory 196976 kb
Host smart-2fe92a0d-c384-45a0-8afc-a6cf2b653446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.38644344
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1795075063
Short name T398
Test name
Test status
Simulation time 15343756 ps
CPU time 0.61 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 194408 kb
Host smart-b75d44ed-6ce1-46b5-a5c0-59867b011567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795075063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1795075063
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4165853180
Short name T165
Test name
Test status
Simulation time 175504788 ps
CPU time 1.07 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 196056 kb
Host smart-0ca08b06-103c-45cb-9869-8876bd8ae84a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165853180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4165853180
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2027352830
Short name T227
Test name
Test status
Simulation time 54351390 ps
CPU time 2.48 seconds
Started Mar 05 12:59:47 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 198044 kb
Host smart-af092fd6-b366-4640-84ee-c9664cf61051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027352830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2027352830
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1544234214
Short name T208
Test name
Test status
Simulation time 189012739 ps
CPU time 1.26 seconds
Started Mar 05 12:59:43 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 195696 kb
Host smart-f64ed526-2e3c-40de-8edd-fbd4feffd768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544234214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1544234214
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1724122929
Short name T377
Test name
Test status
Simulation time 132248861 ps
CPU time 1.06 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 12:59:55 PM PST 24
Peak memory 195544 kb
Host smart-795c417f-d1b5-40b2-bea5-91284e9052a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724122929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1724122929
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.630818626
Short name T6
Test name
Test status
Simulation time 13148326617 ps
CPU time 138.18 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 01:02:11 PM PST 24
Peak memory 198272 kb
Host smart-f15acddc-bb83-41b8-8459-f872b54a30a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630818626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.630818626
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1040664002
Short name T67
Test name
Test status
Simulation time 37805901152 ps
CPU time 513.92 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 01:08:23 PM PST 24
Peak memory 198428 kb
Host smart-5db54889-fced-4f3d-a3f8-6094cd60e5d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1040664002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1040664002
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.626348515
Short name T392
Test name
Test status
Simulation time 19073116 ps
CPU time 0.59 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 194192 kb
Host smart-2cb5bb43-0286-4369-bd90-17ac5bd4900f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626348515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.626348515
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1630539952
Short name T438
Test name
Test status
Simulation time 75738420 ps
CPU time 0.68 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 194260 kb
Host smart-bbe580dd-eb6f-469c-875d-f688c12d8203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630539952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1630539952
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2400285489
Short name T112
Test name
Test status
Simulation time 288786962 ps
CPU time 14.22 seconds
Started Mar 05 12:59:48 PM PST 24
Finished Mar 05 01:00:02 PM PST 24
Peak memory 196980 kb
Host smart-ca8ce079-9533-4625-b731-835b0211f693
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400285489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2400285489
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2995392251
Short name T680
Test name
Test status
Simulation time 432980129 ps
CPU time 0.98 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 197960 kb
Host smart-8156b4c0-0260-4790-9a9b-a6c0f1988ebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995392251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2995392251
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3959851661
Short name T612
Test name
Test status
Simulation time 1020026988 ps
CPU time 1.23 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 196048 kb
Host smart-93f42c6b-66ec-4fb2-b886-3a1eb9c41ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959851661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3959851661
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.11230995
Short name T163
Test name
Test status
Simulation time 96662089 ps
CPU time 4.01 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:56 PM PST 24
Peak memory 198120 kb
Host smart-95bdf452-e44d-4d6d-9a2f-580b200c9575
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.gpio_intr_with_filter_rand_intr_event.11230995
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3641932270
Short name T350
Test name
Test status
Simulation time 532483507 ps
CPU time 3.15 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 197120 kb
Host smart-b6ba349a-89ba-429f-b790-4149b8413823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641932270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3641932270
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3933952607
Short name T54
Test name
Test status
Simulation time 107326579 ps
CPU time 1.1 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:53 PM PST 24
Peak memory 196932 kb
Host smart-6a9e51fa-1fb0-4690-8c43-f7d98373daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933952607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3933952607
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.572376997
Short name T340
Test name
Test status
Simulation time 27996852 ps
CPU time 0.86 seconds
Started Mar 05 12:59:53 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 195604 kb
Host smart-61e65c2d-1635-4f4f-bc29-f1b702e84da0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572376997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.572376997
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3315359650
Short name T195
Test name
Test status
Simulation time 40599593 ps
CPU time 1.93 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 198104 kb
Host smart-420c94bd-baae-43e1-83e6-eba474effd35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315359650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3315359650
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1586106896
Short name T649
Test name
Test status
Simulation time 73481756 ps
CPU time 1.25 seconds
Started Mar 05 12:59:48 PM PST 24
Finished Mar 05 12:59:49 PM PST 24
Peak memory 196824 kb
Host smart-d6336341-fb35-48d1-865e-86c6a025657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586106896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1586106896
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3002773249
Short name T537
Test name
Test status
Simulation time 305302380 ps
CPU time 1 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 196684 kb
Host smart-74fc9a2f-f3a0-4899-897e-3c4b38f5d0ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002773249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3002773249
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3644483854
Short name T523
Test name
Test status
Simulation time 12851573059 ps
CPU time 185.44 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 01:03:00 PM PST 24
Peak memory 198012 kb
Host smart-d1abc8e4-507b-4328-ab31-26320fd49f21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644483854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3644483854
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.844206878
Short name T122
Test name
Test status
Simulation time 14131285 ps
CPU time 0.56 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:53 PM PST 24
Peak memory 194076 kb
Host smart-83503be7-aaa9-4e65-a5e7-f5054c1ad510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844206878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.844206878
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2380523258
Short name T544
Test name
Test status
Simulation time 40990933 ps
CPU time 0.57 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 193916 kb
Host smart-c2c071f0-30bc-421a-82b2-413e3bdc81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380523258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2380523258
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3810535218
Short name T390
Test name
Test status
Simulation time 385507108 ps
CPU time 20.05 seconds
Started Mar 05 12:59:51 PM PST 24
Finished Mar 05 01:00:11 PM PST 24
Peak memory 197328 kb
Host smart-194d4eab-3aac-46b9-b5de-1b0ee6bf1425
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810535218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3810535218
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1984899724
Short name T203
Test name
Test status
Simulation time 160549623 ps
CPU time 0.99 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:53 PM PST 24
Peak memory 196832 kb
Host smart-8e94c751-0397-437a-a8c3-4f7ed98c196d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984899724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1984899724
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.493342753
Short name T425
Test name
Test status
Simulation time 58865915 ps
CPU time 0.96 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:50 PM PST 24
Peak memory 196108 kb
Host smart-0871ff47-a344-4d99-9bcb-f9b0d7d97e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493342753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.493342753
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3532191170
Short name T368
Test name
Test status
Simulation time 109557015 ps
CPU time 2.01 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 198160 kb
Host smart-489ea680-825e-4f6e-9679-08b6367c899e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532191170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3532191170
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2518709576
Short name T285
Test name
Test status
Simulation time 353965094 ps
CPU time 3.35 seconds
Started Mar 05 12:59:51 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 197432 kb
Host smart-93692953-eb78-407c-83ca-dfa763048cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518709576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2518709576
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4090492529
Short name T423
Test name
Test status
Simulation time 173791091 ps
CPU time 1.03 seconds
Started Mar 05 12:59:51 PM PST 24
Finished Mar 05 12:59:53 PM PST 24
Peak memory 196232 kb
Host smart-aad56a5f-b586-4352-b5ba-6ad1eb14df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090492529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4090492529
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1155369217
Short name T606
Test name
Test status
Simulation time 25764559 ps
CPU time 0.8 seconds
Started Mar 05 12:59:54 PM PST 24
Finished Mar 05 12:59:55 PM PST 24
Peak memory 195628 kb
Host smart-fa9eec55-a55c-42af-a3ea-97678385e24d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155369217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1155369217
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1942837755
Short name T137
Test name
Test status
Simulation time 48461593 ps
CPU time 1.27 seconds
Started Mar 05 12:59:49 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 197932 kb
Host smart-9f10e586-f815-4478-8329-0fbc55164a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942837755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1942837755
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.144779172
Short name T142
Test name
Test status
Simulation time 245009229 ps
CPU time 0.99 seconds
Started Mar 05 12:59:48 PM PST 24
Finished Mar 05 12:59:49 PM PST 24
Peak memory 195576 kb
Host smart-a2e411d3-b102-4927-bfee-203458c449ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144779172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.144779172
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3955809255
Short name T26
Test name
Test status
Simulation time 31313371 ps
CPU time 0.93 seconds
Started Mar 05 12:59:53 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 196576 kb
Host smart-f27e19ac-051d-44c1-a659-af95996cdb6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955809255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3955809255
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4072516596
Short name T590
Test name
Test status
Simulation time 60722437332 ps
CPU time 149.64 seconds
Started Mar 05 12:59:53 PM PST 24
Finished Mar 05 01:02:23 PM PST 24
Peak memory 198224 kb
Host smart-7d5d4757-c9ac-4d3d-a01a-2663d2a2e430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072516596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4072516596
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1809202886
Short name T202
Test name
Test status
Simulation time 13991263 ps
CPU time 0.54 seconds
Started Mar 05 12:59:56 PM PST 24
Finished Mar 05 12:59:57 PM PST 24
Peak memory 192820 kb
Host smart-324bd54d-e737-44dd-93e7-727ca984e7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809202886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1809202886
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.892064067
Short name T655
Test name
Test status
Simulation time 179169808 ps
CPU time 0.88 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:04 PM PST 24
Peak memory 197080 kb
Host smart-1307c13e-d26d-4144-8ff8-e35b2966d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892064067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.892064067
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.737745987
Short name T389
Test name
Test status
Simulation time 416982593 ps
CPU time 21.95 seconds
Started Mar 05 12:59:59 PM PST 24
Finished Mar 05 01:00:21 PM PST 24
Peak memory 198124 kb
Host smart-e88b7635-f731-4828-b778-9a8fad6b3e0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737745987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.737745987
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2278713251
Short name T429
Test name
Test status
Simulation time 40482768 ps
CPU time 0.82 seconds
Started Mar 05 12:59:58 PM PST 24
Finished Mar 05 12:59:59 PM PST 24
Peak memory 195976 kb
Host smart-cb32b0f7-35d9-4c36-adba-8f24fd0a2066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278713251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2278713251
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3520528177
Short name T458
Test name
Test status
Simulation time 235234694 ps
CPU time 0.96 seconds
Started Mar 05 12:59:58 PM PST 24
Finished Mar 05 12:59:59 PM PST 24
Peak memory 196808 kb
Host smart-4bd2067b-ae7a-479d-b969-a5859094a65f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520528177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3520528177
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3580594388
Short name T432
Test name
Test status
Simulation time 84507778 ps
CPU time 3.24 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:07 PM PST 24
Peak memory 196452 kb
Host smart-4ebcb116-b04b-4286-9d41-cffaa307f05f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580594388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3580594388
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3638203240
Short name T487
Test name
Test status
Simulation time 245147581 ps
CPU time 1.14 seconds
Started Mar 05 01:00:01 PM PST 24
Finished Mar 05 01:00:03 PM PST 24
Peak memory 197568 kb
Host smart-a784bb9c-5d87-4d07-92ce-183260d3340a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638203240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3638203240
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2775273124
Short name T401
Test name
Test status
Simulation time 343293547 ps
CPU time 1.17 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 197136 kb
Host smart-2af6f8a2-4e3c-486a-8027-4bc1fb15f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775273124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2775273124
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3216192455
Short name T517
Test name
Test status
Simulation time 94104892 ps
CPU time 1.23 seconds
Started Mar 05 12:59:58 PM PST 24
Finished Mar 05 12:59:59 PM PST 24
Peak memory 197276 kb
Host smart-2013a943-61ec-44dc-a846-8e00277b443f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216192455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3216192455
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3093463973
Short name T679
Test name
Test status
Simulation time 87816543 ps
CPU time 1.53 seconds
Started Mar 05 01:00:05 PM PST 24
Finished Mar 05 01:00:06 PM PST 24
Peak memory 198148 kb
Host smart-3f6f4979-c318-4c6b-8f3f-e7231bc9f095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093463973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3093463973
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3505213108
Short name T236
Test name
Test status
Simulation time 47203505 ps
CPU time 1.31 seconds
Started Mar 05 12:59:52 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 196876 kb
Host smart-39e8f26a-d42e-4805-bc16-f8e2e56b25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505213108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3505213108
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1979203659
Short name T355
Test name
Test status
Simulation time 64935344 ps
CPU time 0.89 seconds
Started Mar 05 12:59:50 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 195804 kb
Host smart-d1ac85b8-eb99-4a27-a1f0-bcbc3fa54c25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979203659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1979203659
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1613269849
Short name T599
Test name
Test status
Simulation time 4108555406 ps
CPU time 23.9 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 198304 kb
Host smart-6cd59760-60d8-46b6-be72-212975fed50e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613269849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1613269849
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1265371959
Short name T611
Test name
Test status
Simulation time 37854492 ps
CPU time 0.58 seconds
Started Mar 05 12:59:00 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 194856 kb
Host smart-dad6ff64-b246-422e-a9f7-f95ec10070a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265371959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1265371959
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4173797918
Short name T447
Test name
Test status
Simulation time 63226068 ps
CPU time 0.69 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195184 kb
Host smart-87951430-a410-403c-aefc-4967fb6efb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173797918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4173797918
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1745254907
Short name T567
Test name
Test status
Simulation time 44762174 ps
CPU time 0.91 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 196336 kb
Host smart-27587ffc-755d-4102-b815-d5b7b9ac34aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745254907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1745254907
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3556231459
Short name T508
Test name
Test status
Simulation time 135335954 ps
CPU time 2.78 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 198216 kb
Host smart-3ffd4f30-f3ec-44f5-b75e-7a57431181fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556231459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3556231459
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2811718530
Short name T616
Test name
Test status
Simulation time 60982921 ps
CPU time 1.78 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 196624 kb
Host smart-cce1a2cf-531c-43db-a3a3-ff85272fe95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811718530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2811718530
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.766686104
Short name T267
Test name
Test status
Simulation time 32401399 ps
CPU time 0.73 seconds
Started Mar 05 12:58:57 PM PST 24
Finished Mar 05 12:58:58 PM PST 24
Peak memory 195428 kb
Host smart-b7bbb659-d2b7-4557-a2b2-4b60fc220e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766686104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.766686104
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3067110894
Short name T376
Test name
Test status
Simulation time 56029968 ps
CPU time 1.26 seconds
Started Mar 05 12:58:55 PM PST 24
Finished Mar 05 12:58:57 PM PST 24
Peak memory 196984 kb
Host smart-dbf80233-4d17-4c88-9706-ab5cf18c3415
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067110894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3067110894
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1274959518
Short name T492
Test name
Test status
Simulation time 332548093 ps
CPU time 4.16 seconds
Started Mar 05 12:58:57 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 198116 kb
Host smart-4ee635d7-098b-48d0-ac55-dbc8a6f21334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274959518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1274959518
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1864777962
Short name T41
Test name
Test status
Simulation time 256706965 ps
CPU time 0.91 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 213768 kb
Host smart-0709e947-31c3-471d-b5c5-3127ac1a0ac3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864777962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1864777962
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.884031996
Short name T354
Test name
Test status
Simulation time 56396826 ps
CPU time 1.02 seconds
Started Mar 05 12:58:55 PM PST 24
Finished Mar 05 12:58:56 PM PST 24
Peak memory 195836 kb
Host smart-b8e2878d-7ee6-4137-8123-090c75feceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884031996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.884031996
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2549710127
Short name T513
Test name
Test status
Simulation time 79950684 ps
CPU time 1.13 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195636 kb
Host smart-9e0ae8c9-6b1e-46fa-88e1-19ca48df35b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549710127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2549710127
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2510855909
Short name T304
Test name
Test status
Simulation time 3118556222 ps
CPU time 75.09 seconds
Started Mar 05 12:58:55 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 198348 kb
Host smart-6ad95d6a-4101-450f-9c43-a2aae3c57809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510855909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2510855909
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.428619224
Short name T553
Test name
Test status
Simulation time 191643685120 ps
CPU time 838.33 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 01:12:51 PM PST 24
Peak memory 198444 kb
Host smart-57504d9c-7e13-4629-8df4-b9de78faa9f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=428619224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.428619224
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.750191574
Short name T452
Test name
Test status
Simulation time 62437308 ps
CPU time 0.58 seconds
Started Mar 05 01:00:01 PM PST 24
Finished Mar 05 01:00:02 PM PST 24
Peak memory 194312 kb
Host smart-1a43374d-d3c0-48db-b8d4-e3cd7684042f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750191574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.750191574
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1190340894
Short name T678
Test name
Test status
Simulation time 31717183 ps
CPU time 0.73 seconds
Started Mar 05 01:00:04 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 195936 kb
Host smart-0fbf4411-3921-4742-8841-aa8829933d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190340894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1190340894
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2799599782
Short name T201
Test name
Test status
Simulation time 329500744 ps
CPU time 17.49 seconds
Started Mar 05 01:00:01 PM PST 24
Finished Mar 05 01:00:20 PM PST 24
Peak memory 197016 kb
Host smart-1fe36102-8092-4abd-894f-f6514ba3ffd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799599782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2799599782
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2158156345
Short name T358
Test name
Test status
Simulation time 22576623 ps
CPU time 0.64 seconds
Started Mar 05 01:00:00 PM PST 24
Finished Mar 05 01:00:02 PM PST 24
Peak memory 194536 kb
Host smart-8920effd-120c-4600-96a1-200e32485fc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158156345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2158156345
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2458833337
Short name T648
Test name
Test status
Simulation time 41832794 ps
CPU time 1.25 seconds
Started Mar 05 01:00:02 PM PST 24
Finished Mar 05 01:00:04 PM PST 24
Peak memory 196212 kb
Host smart-c0e5c6ef-cd45-4935-87ca-0166c7229717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458833337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2458833337
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1782382955
Short name T197
Test name
Test status
Simulation time 65021006 ps
CPU time 2.65 seconds
Started Mar 05 12:59:57 PM PST 24
Finished Mar 05 01:00:00 PM PST 24
Peak memory 198172 kb
Host smart-856ab59c-a708-47fd-961a-f60f3608e22b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782382955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1782382955
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.917691881
Short name T211
Test name
Test status
Simulation time 100917530 ps
CPU time 0.98 seconds
Started Mar 05 01:00:04 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 195524 kb
Host smart-3e9cec35-4345-40a5-b049-8a6eb03485f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917691881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
917691881
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.391855808
Short name T597
Test name
Test status
Simulation time 94994699 ps
CPU time 0.73 seconds
Started Mar 05 01:00:00 PM PST 24
Finished Mar 05 01:00:02 PM PST 24
Peak memory 195288 kb
Host smart-73e11a3f-c1c0-4ed2-947d-99de299b3633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391855808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.391855808
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3793676483
Short name T121
Test name
Test status
Simulation time 250762298 ps
CPU time 1.43 seconds
Started Mar 05 01:00:04 PM PST 24
Finished Mar 05 01:00:06 PM PST 24
Peak memory 198144 kb
Host smart-9cd2b4a5-5807-409f-8be5-e3651a9d37c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793676483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3793676483
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3406998549
Short name T164
Test name
Test status
Simulation time 177206640 ps
CPU time 3.24 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:07 PM PST 24
Peak memory 198092 kb
Host smart-d3eeed5b-531b-49fa-869e-5a315e94b6e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406998549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3406998549
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2631546375
Short name T159
Test name
Test status
Simulation time 219198639 ps
CPU time 1.18 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 196696 kb
Host smart-04f29599-7ce7-489a-af53-ca802ec347ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631546375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2631546375
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1449333529
Short name T275
Test name
Test status
Simulation time 283560152 ps
CPU time 1.31 seconds
Started Mar 05 12:59:59 PM PST 24
Finished Mar 05 01:00:00 PM PST 24
Peak memory 195624 kb
Host smart-188aeaff-5b4e-4480-8865-b5f5ccac2b2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449333529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1449333529
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3949246626
Short name T123
Test name
Test status
Simulation time 19706595635 ps
CPU time 173.1 seconds
Started Mar 05 01:00:04 PM PST 24
Finished Mar 05 01:02:57 PM PST 24
Peak memory 198348 kb
Host smart-579357c5-c45c-452b-9119-d8027169f451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949246626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3949246626
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1530828783
Short name T464
Test name
Test status
Simulation time 29483984 ps
CPU time 0.58 seconds
Started Mar 05 01:00:11 PM PST 24
Finished Mar 05 01:00:12 PM PST 24
Peak memory 194728 kb
Host smart-a3c9c520-7b3d-487c-9027-6f78c9d33560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530828783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1530828783
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1751232156
Short name T560
Test name
Test status
Simulation time 129408687 ps
CPU time 0.86 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:04 PM PST 24
Peak memory 195356 kb
Host smart-b501e415-11c5-4375-9aa3-3e0dc5f63d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751232156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1751232156
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3351702162
Short name T525
Test name
Test status
Simulation time 2893270099 ps
CPU time 16.44 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 196080 kb
Host smart-105eb637-d7eb-46cd-b64e-4f5bcf945ac4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351702162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3351702162
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3363385415
Short name T427
Test name
Test status
Simulation time 49836447 ps
CPU time 0.69 seconds
Started Mar 05 01:00:12 PM PST 24
Finished Mar 05 01:00:13 PM PST 24
Peak memory 195368 kb
Host smart-a2f479ed-1898-4b29-8b81-14f3e13bfff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363385415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3363385415
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1676566842
Short name T326
Test name
Test status
Simulation time 487883455 ps
CPU time 1.36 seconds
Started Mar 05 01:00:01 PM PST 24
Finished Mar 05 01:00:03 PM PST 24
Peak memory 197220 kb
Host smart-34d4425b-5b73-41fe-a17d-2703c3f649ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676566842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1676566842
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.510535211
Short name T73
Test name
Test status
Simulation time 216571306 ps
CPU time 2.26 seconds
Started Mar 05 01:00:11 PM PST 24
Finished Mar 05 01:00:13 PM PST 24
Peak memory 198084 kb
Host smart-7af0bd9c-c82e-4463-9ef7-02f426a5cd3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510535211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.510535211
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1834303315
Short name T584
Test name
Test status
Simulation time 549289985 ps
CPU time 2.71 seconds
Started Mar 05 01:00:08 PM PST 24
Finished Mar 05 01:00:11 PM PST 24
Peak memory 196836 kb
Host smart-27347bde-03c3-481e-9937-066bbd42c860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834303315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1834303315
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.220124326
Short name T586
Test name
Test status
Simulation time 78914173 ps
CPU time 0.92 seconds
Started Mar 05 01:00:01 PM PST 24
Finished Mar 05 01:00:03 PM PST 24
Peak memory 196596 kb
Host smart-74064a9b-347b-4c28-b64f-39fe58068193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220124326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.220124326
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3638772590
Short name T687
Test name
Test status
Simulation time 44347467 ps
CPU time 1.01 seconds
Started Mar 05 12:59:59 PM PST 24
Finished Mar 05 01:00:00 PM PST 24
Peak memory 196132 kb
Host smart-17ab9aa7-fe9a-4581-8365-162e0605e6a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638772590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3638772590
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2318608047
Short name T7
Test name
Test status
Simulation time 361123958 ps
CPU time 4.24 seconds
Started Mar 05 01:00:08 PM PST 24
Finished Mar 05 01:00:12 PM PST 24
Peak memory 198084 kb
Host smart-88ca1f51-4f32-486c-9b91-8bf1be493465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318608047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2318608047
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2737967650
Short name T615
Test name
Test status
Simulation time 118277516 ps
CPU time 1.26 seconds
Started Mar 05 01:00:02 PM PST 24
Finished Mar 05 01:00:04 PM PST 24
Peak memory 196952 kb
Host smart-5648db0d-636a-45c3-be84-8628ca151105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737967650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2737967650
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3776477606
Short name T114
Test name
Test status
Simulation time 132388142 ps
CPU time 1.15 seconds
Started Mar 05 01:00:03 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 196580 kb
Host smart-b24e9d44-3c6f-46f6-b19f-06e3358befd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776477606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3776477606
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.345197306
Short name T497
Test name
Test status
Simulation time 81265691227 ps
CPU time 129.48 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:02:19 PM PST 24
Peak memory 198280 kb
Host smart-4fad06dc-3872-4e8e-b4b5-cfddd7ca0d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345197306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.345197306
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.730625889
Short name T69
Test name
Test status
Simulation time 143132514185 ps
CPU time 1196.44 seconds
Started Mar 05 01:00:10 PM PST 24
Finished Mar 05 01:20:07 PM PST 24
Peak memory 198480 kb
Host smart-c28bb61e-1052-4bfa-9386-1fc75559e8aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=730625889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.730625889
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3986096564
Short name T274
Test name
Test status
Simulation time 50256538 ps
CPU time 0.58 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 194216 kb
Host smart-ac7ee65b-79af-4fcb-ac1e-eade32a9d53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986096564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3986096564
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2254823837
Short name T181
Test name
Test status
Simulation time 162369941 ps
CPU time 0.78 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 196052 kb
Host smart-e3a5f94b-c8c6-4bfa-b4d4-130549ed0fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254823837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2254823837
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1424659323
Short name T192
Test name
Test status
Simulation time 1425323827 ps
CPU time 11.99 seconds
Started Mar 05 01:00:11 PM PST 24
Finished Mar 05 01:00:23 PM PST 24
Peak memory 196884 kb
Host smart-00b99ebd-5dba-485a-a212-a6f9244eb8b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424659323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1424659323
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1010033763
Short name T607
Test name
Test status
Simulation time 203734393 ps
CPU time 0.96 seconds
Started Mar 05 01:00:11 PM PST 24
Finished Mar 05 01:00:12 PM PST 24
Peak memory 196976 kb
Host smart-3b6617a2-9a0f-4ce5-b7d4-50a30e0f2370
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010033763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1010033763
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.446183896
Short name T342
Test name
Test status
Simulation time 28082007 ps
CPU time 0.74 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 195092 kb
Host smart-1f3ec487-9845-4feb-973f-dcbb0d6d2f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446183896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.446183896
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3592616411
Short name T262
Test name
Test status
Simulation time 93257366 ps
CPU time 3.75 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:13 PM PST 24
Peak memory 198016 kb
Host smart-e5a8c688-c14a-43c0-b50a-e0cdc638a197
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592616411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3592616411
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1826249836
Short name T135
Test name
Test status
Simulation time 312313654 ps
CPU time 2.62 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:00:16 PM PST 24
Peak memory 197376 kb
Host smart-28c4af8b-d371-48d2-b9a9-a426be60a465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826249836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1826249836
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.233097780
Short name T454
Test name
Test status
Simulation time 26521849 ps
CPU time 0.65 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 194352 kb
Host smart-a027a21c-3dba-4be6-985c-7c6b2fd98717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233097780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.233097780
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1942288382
Short name T297
Test name
Test status
Simulation time 24718706 ps
CPU time 0.69 seconds
Started Mar 05 01:00:08 PM PST 24
Finished Mar 05 01:00:09 PM PST 24
Peak memory 194380 kb
Host smart-f0192179-2ae8-4764-a342-7bf26004a186
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942288382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1942288382
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1584569204
Short name T538
Test name
Test status
Simulation time 237681265 ps
CPU time 2.9 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:12 PM PST 24
Peak memory 198092 kb
Host smart-173060da-30e6-48fd-9dff-90259267bc85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584569204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1584569204
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.532407600
Short name T689
Test name
Test status
Simulation time 92731834 ps
CPU time 0.97 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:00:15 PM PST 24
Peak memory 195404 kb
Host smart-f6b7d83b-a69d-49b5-95e5-dfced8bd4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532407600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.532407600
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2370053071
Short name T384
Test name
Test status
Simulation time 43090141 ps
CPU time 0.83 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:00:15 PM PST 24
Peak memory 195384 kb
Host smart-b9a04252-eec7-4c4f-a76f-53ed2c01956f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370053071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2370053071
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2733976008
Short name T313
Test name
Test status
Simulation time 13943507930 ps
CPU time 133.15 seconds
Started Mar 05 01:00:12 PM PST 24
Finished Mar 05 01:02:26 PM PST 24
Peak memory 198268 kb
Host smart-87a4930a-8281-4c6a-9de8-8e2cbad4749c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733976008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2733976008
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.850845208
Short name T220
Test name
Test status
Simulation time 14821577 ps
CPU time 0.58 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:00:15 PM PST 24
Peak memory 193992 kb
Host smart-ba5208ce-ae2f-423a-9ee9-a3f50f3ba1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850845208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.850845208
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.598161567
Short name T695
Test name
Test status
Simulation time 81980921 ps
CPU time 0.76 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 195452 kb
Host smart-3d78cb15-f28d-4a5d-a22a-70a6c4fd4257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598161567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.598161567
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.271895252
Short name T153
Test name
Test status
Simulation time 438600820 ps
CPU time 22.75 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:32 PM PST 24
Peak memory 195700 kb
Host smart-395c5039-c75f-4789-8719-5def5abfd475
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271895252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.271895252
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3353053965
Short name T463
Test name
Test status
Simulation time 31217173 ps
CPU time 0.74 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 195896 kb
Host smart-3c980416-022c-4f52-9cb2-f51e4b072acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353053965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3353053965
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2469890236
Short name T131
Test name
Test status
Simulation time 414736395 ps
CPU time 1.39 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 196604 kb
Host smart-7656eda4-b91c-4b91-b079-1fb7e417dc24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469890236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2469890236
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1427295875
Short name T139
Test name
Test status
Simulation time 39413577 ps
CPU time 0.95 seconds
Started Mar 05 01:00:10 PM PST 24
Finished Mar 05 01:00:11 PM PST 24
Peak memory 196996 kb
Host smart-ae905ba3-eecc-4d7d-88a1-b858e331a643
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427295875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1427295875
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3123912599
Short name T244
Test name
Test status
Simulation time 382259973 ps
CPU time 1.34 seconds
Started Mar 05 01:00:10 PM PST 24
Finished Mar 05 01:00:12 PM PST 24
Peak memory 196944 kb
Host smart-af49c608-9726-492d-9905-13cb351b48f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123912599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3123912599
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.377280549
Short name T483
Test name
Test status
Simulation time 78982286 ps
CPU time 0.86 seconds
Started Mar 05 01:00:10 PM PST 24
Finished Mar 05 01:00:11 PM PST 24
Peak memory 195952 kb
Host smart-c866853d-a11d-48f1-8352-7d775144ddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377280549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.377280549
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1842536342
Short name T271
Test name
Test status
Simulation time 22550269 ps
CPU time 0.9 seconds
Started Mar 05 01:00:08 PM PST 24
Finished Mar 05 01:00:09 PM PST 24
Peak memory 196020 kb
Host smart-21f643f6-ac76-4db5-b82c-386ac2e63dbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842536342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1842536342
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3958980061
Short name T500
Test name
Test status
Simulation time 256663085 ps
CPU time 4.32 seconds
Started Mar 05 01:00:11 PM PST 24
Finished Mar 05 01:00:15 PM PST 24
Peak memory 198036 kb
Host smart-ebcb0889-6403-428f-a947-12226fc641d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958980061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3958980061
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3460385396
Short name T76
Test name
Test status
Simulation time 171208823 ps
CPU time 1.38 seconds
Started Mar 05 01:00:09 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 196872 kb
Host smart-4bb4a03e-be73-4751-b549-2d7e1a69d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460385396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3460385396
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1186115229
Short name T170
Test name
Test status
Simulation time 49681696 ps
CPU time 1.35 seconds
Started Mar 05 01:00:13 PM PST 24
Finished Mar 05 01:00:14 PM PST 24
Peak memory 196900 kb
Host smart-a481a56f-567c-4ae7-aa31-4cca8fb8dd66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186115229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1186115229
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.174612289
Short name T287
Test name
Test status
Simulation time 8997249768 ps
CPU time 178.37 seconds
Started Mar 05 01:00:15 PM PST 24
Finished Mar 05 01:03:13 PM PST 24
Peak memory 198320 kb
Host smart-1d1aa9c2-04d9-40a7-8a91-f7d42e1bf5bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174612289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.174612289
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1596310368
Short name T666
Test name
Test status
Simulation time 46186958218 ps
CPU time 682.39 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:11:37 PM PST 24
Peak memory 198532 kb
Host smart-51534978-273c-45f5-9133-a082b31b7921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1596310368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1596310368
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1457634824
Short name T664
Test name
Test status
Simulation time 24461174 ps
CPU time 0.73 seconds
Started Mar 05 01:00:18 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 194140 kb
Host smart-f9432695-b76f-4fe3-9e08-133df65a3c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457634824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1457634824
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1435823834
Short name T692
Test name
Test status
Simulation time 471450703 ps
CPU time 15.36 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:32 PM PST 24
Peak memory 197072 kb
Host smart-3fb362d8-2b24-420e-886b-7928f428cbf9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435823834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1435823834
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.123744910
Short name T604
Test name
Test status
Simulation time 107270978 ps
CPU time 0.85 seconds
Started Mar 05 01:00:18 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 196060 kb
Host smart-87dfca62-4d2d-49f8-9ceb-c22b8fa9cdc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123744910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.123744910
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2131176782
Short name T222
Test name
Test status
Simulation time 277184633 ps
CPU time 1.25 seconds
Started Mar 05 01:00:14 PM PST 24
Finished Mar 05 01:00:16 PM PST 24
Peak memory 196740 kb
Host smart-ba5d90bd-f6bb-43ca-a372-18591f8de968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131176782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2131176782
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.777029768
Short name T409
Test name
Test status
Simulation time 46806882 ps
CPU time 1.8 seconds
Started Mar 05 01:00:16 PM PST 24
Finished Mar 05 01:00:17 PM PST 24
Peak memory 196580 kb
Host smart-42a5d590-2e72-484b-a4af-e4ce3af52921
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777029768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.777029768
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1286625996
Short name T476
Test name
Test status
Simulation time 100225307 ps
CPU time 1.34 seconds
Started Mar 05 01:00:22 PM PST 24
Finished Mar 05 01:00:24 PM PST 24
Peak memory 195928 kb
Host smart-bca97de0-7602-4754-9aef-b4c65e1a6d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286625996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1286625996
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2322317836
Short name T548
Test name
Test status
Simulation time 27877670 ps
CPU time 0.74 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 195228 kb
Host smart-1840bded-c9b1-49cf-9d24-525775de9311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322317836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2322317836
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2722888155
Short name T394
Test name
Test status
Simulation time 24614963 ps
CPU time 0.86 seconds
Started Mar 05 01:00:20 PM PST 24
Finished Mar 05 01:00:21 PM PST 24
Peak memory 196588 kb
Host smart-90b43b4e-6252-42a3-a563-c5c852d31007
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722888155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2722888155
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1514945300
Short name T57
Test name
Test status
Simulation time 352517026 ps
CPU time 1.79 seconds
Started Mar 05 01:00:18 PM PST 24
Finished Mar 05 01:00:20 PM PST 24
Peak memory 197980 kb
Host smart-0b8f21f9-ed3f-463e-840f-9ffa9e9839ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514945300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1514945300
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3046753160
Short name T667
Test name
Test status
Simulation time 506672835 ps
CPU time 1.46 seconds
Started Mar 05 01:00:15 PM PST 24
Finished Mar 05 01:00:16 PM PST 24
Peak memory 196924 kb
Host smart-5f2910d4-5361-437b-8989-d6e5bd422aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046753160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3046753160
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3034049889
Short name T428
Test name
Test status
Simulation time 98023079 ps
CPU time 1.3 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:18 PM PST 24
Peak memory 196840 kb
Host smart-f0846b98-a709-4a5d-9899-6ea4187e4296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034049889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3034049889
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3575060653
Short name T189
Test name
Test status
Simulation time 15091486933 ps
CPU time 59.22 seconds
Started Mar 05 01:00:22 PM PST 24
Finished Mar 05 01:01:21 PM PST 24
Peak memory 198180 kb
Host smart-1b44f3c3-157a-4e78-b7d2-99d34537eee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575060653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3575060653
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3057976042
Short name T64
Test name
Test status
Simulation time 74125716065 ps
CPU time 1151.48 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 198224 kb
Host smart-b259ea9a-eca9-42c6-82a5-77351f8b873e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3057976042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3057976042
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2346094529
Short name T261
Test name
Test status
Simulation time 19274257 ps
CPU time 0.57 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:18 PM PST 24
Peak memory 194084 kb
Host smart-6e9a5b75-f03b-4d11-873c-c0b003d53d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346094529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2346094529
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2705056372
Short name T542
Test name
Test status
Simulation time 112353004 ps
CPU time 0.93 seconds
Started Mar 05 01:00:16 PM PST 24
Finished Mar 05 01:00:17 PM PST 24
Peak memory 196584 kb
Host smart-d6f5bab9-c4fa-4dd9-af69-796a92236b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705056372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2705056372
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1412277371
Short name T565
Test name
Test status
Simulation time 110739099 ps
CPU time 5.7 seconds
Started Mar 05 01:00:15 PM PST 24
Finished Mar 05 01:00:21 PM PST 24
Peak memory 195672 kb
Host smart-84a3fa40-3d98-4b9e-b502-d2cf6d94e09c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412277371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1412277371
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1503531060
Short name T592
Test name
Test status
Simulation time 72971490 ps
CPU time 1.06 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 196700 kb
Host smart-78c54f5b-2da4-4715-8e39-1aa210480205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503531060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1503531060
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1891147348
Short name T605
Test name
Test status
Simulation time 117655645 ps
CPU time 0.82 seconds
Started Mar 05 01:00:13 PM PST 24
Finished Mar 05 01:00:14 PM PST 24
Peak memory 196252 kb
Host smart-0f23899c-6e62-4342-b80a-404ff528019b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891147348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1891147348
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2076950283
Short name T290
Test name
Test status
Simulation time 64162635 ps
CPU time 2.53 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 197344 kb
Host smart-ac37a130-f1a1-422c-bf97-0f4fd7a9196a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076950283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2076950283
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2548233695
Short name T11
Test name
Test status
Simulation time 163791009 ps
CPU time 2.51 seconds
Started Mar 05 01:00:15 PM PST 24
Finished Mar 05 01:00:18 PM PST 24
Peak memory 198148 kb
Host smart-da76c5fb-619d-4b65-a883-2dc96379023c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548233695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2548233695
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1569670021
Short name T242
Test name
Test status
Simulation time 138720603 ps
CPU time 1.3 seconds
Started Mar 05 01:00:18 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 197000 kb
Host smart-67f5d7ba-c390-42da-99a2-4f5b77a43930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569670021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1569670021
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.579797357
Short name T653
Test name
Test status
Simulation time 105726054 ps
CPU time 1.11 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:00:24 PM PST 24
Peak memory 196512 kb
Host smart-74781c86-2d5e-4434-8105-6cf5c6b865a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579797357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.579797357
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4073971241
Short name T347
Test name
Test status
Simulation time 140812133 ps
CPU time 3.46 seconds
Started Mar 05 01:00:18 PM PST 24
Finished Mar 05 01:00:22 PM PST 24
Peak memory 197920 kb
Host smart-785fc694-5de0-4d62-a474-f8fc5135c420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073971241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4073971241
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3318462650
Short name T472
Test name
Test status
Simulation time 104230863 ps
CPU time 0.8 seconds
Started Mar 05 01:00:15 PM PST 24
Finished Mar 05 01:00:16 PM PST 24
Peak memory 195864 kb
Host smart-90846e81-8f67-4b46-8f17-18bdd2a28cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318462650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3318462650
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2692999580
Short name T150
Test name
Test status
Simulation time 152632331 ps
CPU time 0.75 seconds
Started Mar 05 01:00:17 PM PST 24
Finished Mar 05 01:00:19 PM PST 24
Peak memory 195076 kb
Host smart-67d7561b-95d5-4f76-9671-05a493f794fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692999580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2692999580
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2945324790
Short name T330
Test name
Test status
Simulation time 223836001188 ps
CPU time 157.72 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:03:02 PM PST 24
Peak memory 198336 kb
Host smart-ede92464-6265-4f04-8ac7-48f122481704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945324790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2945324790
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.4202571007
Short name T35
Test name
Test status
Simulation time 339964339987 ps
CPU time 1807.64 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:30:31 PM PST 24
Peak memory 198492 kb
Host smart-c6e0d713-1259-4717-9a5d-adcf00c8d51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4202571007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.4202571007
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2871265930
Short name T77
Test name
Test status
Simulation time 13500207 ps
CPU time 0.57 seconds
Started Mar 05 01:00:25 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 194756 kb
Host smart-39f6942e-7511-44c7-87d3-81e454ae1c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871265930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2871265930
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3402158164
Short name T225
Test name
Test status
Simulation time 53514006 ps
CPU time 0.76 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 195312 kb
Host smart-9725eef3-319a-4ca0-a46e-c6005550393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402158164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3402158164
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1100714817
Short name T315
Test name
Test status
Simulation time 1617760483 ps
CPU time 14.56 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 197048 kb
Host smart-09c31150-e4d8-4a9d-b385-9f68e6180d04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100714817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1100714817
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3368893618
Short name T622
Test name
Test status
Simulation time 38617445 ps
CPU time 0.61 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 194656 kb
Host smart-ebac5b1f-471d-437a-b67f-2bc9a24455f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368893618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3368893618
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2397472979
Short name T674
Test name
Test status
Simulation time 89683624 ps
CPU time 0.84 seconds
Started Mar 05 01:00:31 PM PST 24
Finished Mar 05 01:00:31 PM PST 24
Peak memory 195496 kb
Host smart-a699ac1a-8b97-4768-80ee-d7754177e51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397472979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2397472979
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4096270766
Short name T106
Test name
Test status
Simulation time 1632627253 ps
CPU time 3.54 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 196616 kb
Host smart-8f909074-bbba-4479-a9a0-4fe9ba28ef7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096270766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4096270766
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2937856578
Short name T56
Test name
Test status
Simulation time 112972728 ps
CPU time 3 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 198172 kb
Host smart-7f10f715-00fb-4833-90f8-940559104843
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937856578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2937856578
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1995592557
Short name T370
Test name
Test status
Simulation time 61879972 ps
CPU time 1.3 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 196016 kb
Host smart-ad3839b4-67c6-4bc6-a655-dd57ec284ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995592557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1995592557
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3026668970
Short name T457
Test name
Test status
Simulation time 49699791 ps
CPU time 0.72 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 195944 kb
Host smart-528c8b3b-8e44-4e21-be04-eff72e6b7ca8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026668970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3026668970
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1977991233
Short name T577
Test name
Test status
Simulation time 97803602 ps
CPU time 4.67 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:00:29 PM PST 24
Peak memory 198088 kb
Host smart-b0ae1067-5401-417b-9282-4e9c7f6f03f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977991233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1977991233
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3987403486
Short name T210
Test name
Test status
Simulation time 124823176 ps
CPU time 1.02 seconds
Started Mar 05 01:00:22 PM PST 24
Finished Mar 05 01:00:23 PM PST 24
Peak memory 195568 kb
Host smart-fed14f53-54ae-40b4-bfd6-8e76ef52784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987403486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3987403486
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2738303684
Short name T466
Test name
Test status
Simulation time 67868152 ps
CPU time 1.44 seconds
Started Mar 05 01:00:23 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 196796 kb
Host smart-a199f0f7-2369-41aa-a562-93dfc3690f4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738303684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2738303684
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2067398582
Short name T700
Test name
Test status
Simulation time 145112921123 ps
CPU time 218.8 seconds
Started Mar 05 01:00:33 PM PST 24
Finished Mar 05 01:04:12 PM PST 24
Peak memory 198192 kb
Host smart-cd2fd21d-c1ea-4da3-8812-5b4080945ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067398582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2067398582
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1812119087
Short name T224
Test name
Test status
Simulation time 20442882 ps
CPU time 0.58 seconds
Started Mar 05 01:00:25 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 193992 kb
Host smart-e9eba0b5-90f2-4677-b5ac-81a6e8514246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812119087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1812119087
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3728048825
Short name T395
Test name
Test status
Simulation time 21811341 ps
CPU time 0.7 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 194776 kb
Host smart-224a43bc-c625-4d6b-93d2-f6e023e54cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728048825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3728048825
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3026241556
Short name T662
Test name
Test status
Simulation time 1299524920 ps
CPU time 22.3 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 197112 kb
Host smart-f1677280-c3ac-45d4-854b-acdeb35f0b84
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026241556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3026241556
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.119084562
Short name T178
Test name
Test status
Simulation time 213366166 ps
CPU time 0.98 seconds
Started Mar 05 01:00:25 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 196620 kb
Host smart-a8d740d6-a1e1-485a-9497-1bbc842f5df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119084562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.119084562
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3630156116
Short name T232
Test name
Test status
Simulation time 600774704 ps
CPU time 1.32 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 197352 kb
Host smart-5dc25ca1-ad77-4790-a069-da437bba39b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630156116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3630156116
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.920284028
Short name T443
Test name
Test status
Simulation time 413601064 ps
CPU time 3.52 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 196412 kb
Host smart-c63f99f8-f12f-4d40-a41e-ee07faab2883
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920284028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.920284028
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1182904773
Short name T556
Test name
Test status
Simulation time 387697764 ps
CPU time 2.99 seconds
Started Mar 05 01:00:30 PM PST 24
Finished Mar 05 01:00:33 PM PST 24
Peak memory 197020 kb
Host smart-acf48800-b682-4e8b-950d-09a610ea324a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182904773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1182904773
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2248979838
Short name T156
Test name
Test status
Simulation time 57204665 ps
CPU time 0.99 seconds
Started Mar 05 01:00:29 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 195948 kb
Host smart-ad2378c2-6e87-442a-a1dc-2f95696bcaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248979838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2248979838
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1788013243
Short name T503
Test name
Test status
Simulation time 77426844 ps
CPU time 1.02 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 196112 kb
Host smart-f92a4402-7e1d-4cea-8b50-d436e48a5554
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788013243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1788013243
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1745712589
Short name T677
Test name
Test status
Simulation time 310523740 ps
CPU time 3.55 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 198188 kb
Host smart-9caeb86b-0dd9-46c2-97db-6a2f232621e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745712589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1745712589
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1542885544
Short name T400
Test name
Test status
Simulation time 33183637 ps
CPU time 0.94 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 197048 kb
Host smart-28dbf18c-7786-450b-bac8-18312414fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542885544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1542885544
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4131357353
Short name T301
Test name
Test status
Simulation time 124936251 ps
CPU time 1.07 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 195940 kb
Host smart-40dfbefc-891c-4679-810a-e9652a55688b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131357353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4131357353
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1249173211
Short name T15
Test name
Test status
Simulation time 44906671925 ps
CPU time 204.28 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:03:51 PM PST 24
Peak memory 198316 kb
Host smart-f06b2cf5-1434-4709-af3f-06ea26cffeb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249173211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1249173211
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2807687956
Short name T344
Test name
Test status
Simulation time 14432714 ps
CPU time 0.67 seconds
Started Mar 05 01:00:28 PM PST 24
Finished Mar 05 01:00:29 PM PST 24
Peak memory 194280 kb
Host smart-e7179b54-676b-4719-b20c-c983cbe1b712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807687956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2807687956
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2773560489
Short name T115
Test name
Test status
Simulation time 19048385 ps
CPU time 0.67 seconds
Started Mar 05 01:00:25 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 194260 kb
Host smart-e3e0ebc5-ecad-403d-a367-0e336ff1df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773560489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2773560489
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3383583819
Short name T21
Test name
Test status
Simulation time 4185643356 ps
CPU time 28.53 seconds
Started Mar 05 01:00:29 PM PST 24
Finished Mar 05 01:00:58 PM PST 24
Peak memory 197268 kb
Host smart-ffc0284b-6f88-4b72-8c49-8f08c1108302
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383583819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3383583819
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3752689439
Short name T600
Test name
Test status
Simulation time 140390245 ps
CPU time 0.72 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:00:25 PM PST 24
Peak memory 194896 kb
Host smart-8ec8ba25-a6eb-4696-956d-a0139af24a8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752689439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3752689439
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3629996882
Short name T645
Test name
Test status
Simulation time 362243682 ps
CPU time 1.37 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 197268 kb
Host smart-7097cda5-d035-419a-9923-0d3cd68542a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629996882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3629996882
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.995413196
Short name T449
Test name
Test status
Simulation time 63753922 ps
CPU time 2.41 seconds
Started Mar 05 01:00:31 PM PST 24
Finished Mar 05 01:00:34 PM PST 24
Peak memory 197828 kb
Host smart-08222ca1-0db6-4c3b-9311-ccf7f5ff55a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995413196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.995413196
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2964043821
Short name T234
Test name
Test status
Simulation time 582255871 ps
CPU time 3.3 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 197304 kb
Host smart-90f1a989-7ec0-49e8-b97c-3c2c710a186f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964043821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2964043821
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3765551405
Short name T23
Test name
Test status
Simulation time 37487641 ps
CPU time 0.77 seconds
Started Mar 05 01:00:25 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 194428 kb
Host smart-67d2e589-f9a4-48b3-a930-68d88f4db5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765551405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3765551405
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2007268951
Short name T439
Test name
Test status
Simulation time 37655264 ps
CPU time 0.9 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 196664 kb
Host smart-7f3a6382-d1e2-4ab6-9247-ee1bcc9d5115
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007268951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2007268951
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_smoke.440875997
Short name T252
Test name
Test status
Simulation time 131527743 ps
CPU time 1.07 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 196648 kb
Host smart-fa3d453f-6003-4c99-8a6e-b407d487d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440875997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.440875997
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.257250576
Short name T661
Test name
Test status
Simulation time 146402516 ps
CPU time 0.97 seconds
Started Mar 05 01:00:29 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 195872 kb
Host smart-da291b00-a49e-4525-a203-9bb7bf4ca042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257250576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.257250576
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1866680211
Short name T549
Test name
Test status
Simulation time 36563993258 ps
CPU time 205.33 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:03:52 PM PST 24
Peak memory 198304 kb
Host smart-86bf864a-9f12-421b-a8ce-1c1f5295ca8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866680211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1866680211
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3619733086
Short name T694
Test name
Test status
Simulation time 41724947 ps
CPU time 0.58 seconds
Started Mar 05 01:00:35 PM PST 24
Finished Mar 05 01:00:36 PM PST 24
Peak memory 194092 kb
Host smart-7f050858-0f3a-4f59-ad4c-392219f1e990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619733086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3619733086
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4184029562
Short name T405
Test name
Test status
Simulation time 38876862 ps
CPU time 0.69 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 194816 kb
Host smart-22174151-7d7b-41a5-ba1d-63691ace07d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184029562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4184029562
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4098978382
Short name T292
Test name
Test status
Simulation time 528411803 ps
CPU time 17.5 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:44 PM PST 24
Peak memory 196420 kb
Host smart-1141509a-1766-47ab-a8f1-555d2841f475
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098978382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4098978382
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3919083616
Short name T140
Test name
Test status
Simulation time 89259128 ps
CPU time 0.86 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 197024 kb
Host smart-50f4d20d-8994-4c59-a88a-33207561a268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919083616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3919083616
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1380805107
Short name T266
Test name
Test status
Simulation time 101631977 ps
CPU time 0.82 seconds
Started Mar 05 01:00:28 PM PST 24
Finished Mar 05 01:00:29 PM PST 24
Peak memory 196888 kb
Host smart-5a9ff9fa-3faa-4314-b527-643a7b1c09cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380805107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1380805107
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3468223623
Short name T501
Test name
Test status
Simulation time 110981156 ps
CPU time 1.4 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 196700 kb
Host smart-a647cdd8-a3fd-44db-8fa5-6afe3ea5a50f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468223623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3468223623
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2931378096
Short name T294
Test name
Test status
Simulation time 106052146 ps
CPU time 2.09 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 197504 kb
Host smart-1b8990fd-ec87-42f2-ab1f-008d601ef1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931378096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2931378096
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1737180110
Short name T431
Test name
Test status
Simulation time 234648126 ps
CPU time 0.71 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 196216 kb
Host smart-e1f4f745-be1a-45f4-aa86-ca0c64996141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737180110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1737180110
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2626380818
Short name T357
Test name
Test status
Simulation time 80147030 ps
CPU time 1.23 seconds
Started Mar 05 01:00:27 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 197180 kb
Host smart-5898ec44-99b0-4ff5-85bc-e02747fee1f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626380818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2626380818
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2798429543
Short name T640
Test name
Test status
Simulation time 114101800 ps
CPU time 3.06 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:29 PM PST 24
Peak memory 198080 kb
Host smart-f68cf8c9-f6e6-44d2-a51e-3a73c2734e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798429543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2798429543
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2967144563
Short name T468
Test name
Test status
Simulation time 89325113 ps
CPU time 1.53 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:28 PM PST 24
Peak memory 198064 kb
Host smart-a3806cbd-3483-4344-87f7-8b107ffd3b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967144563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2967144563
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3394656647
Short name T307
Test name
Test status
Simulation time 126560179 ps
CPU time 1.19 seconds
Started Mar 05 01:00:26 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 195912 kb
Host smart-51d42cb3-33b0-46ba-8870-42c418277b5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394656647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3394656647
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2350235556
Short name T207
Test name
Test status
Simulation time 24447087217 ps
CPU time 154.98 seconds
Started Mar 05 01:00:24 PM PST 24
Finished Mar 05 01:03:00 PM PST 24
Peak memory 198312 kb
Host smart-61eddaf8-fd64-4b2f-8e7a-f01d0261ffcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350235556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2350235556
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1951761942
Short name T204
Test name
Test status
Simulation time 12045554 ps
CPU time 0.57 seconds
Started Mar 05 12:59:00 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 194096 kb
Host smart-b9271169-758c-4108-a7f8-c9541261301c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951761942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1951761942
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2773975101
Short name T641
Test name
Test status
Simulation time 330297435 ps
CPU time 0.77 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195988 kb
Host smart-c2510848-2adf-4815-9a0f-dd8b77e62ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773975101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2773975101
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.873698828
Short name T238
Test name
Test status
Simulation time 933609115 ps
CPU time 11.41 seconds
Started Mar 05 12:58:55 PM PST 24
Finished Mar 05 12:59:06 PM PST 24
Peak memory 196664 kb
Host smart-648847ed-e83b-49b9-add4-e07c3184fb9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873698828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.873698828
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2810978784
Short name T333
Test name
Test status
Simulation time 67844562 ps
CPU time 0.94 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:05 PM PST 24
Peak memory 197108 kb
Host smart-1e527d50-0951-4bb3-aa3f-ba4b9e19226e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810978784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2810978784
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3455673865
Short name T625
Test name
Test status
Simulation time 40005866 ps
CPU time 0.68 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 194308 kb
Host smart-564c6edd-ce0d-469b-88bc-ccf878db9074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455673865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3455673865
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4248847482
Short name T477
Test name
Test status
Simulation time 264310126 ps
CPU time 2.72 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 198112 kb
Host smart-264e1936-12b9-4901-8f5a-7355152a9874
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248847482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4248847482
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.60701244
Short name T352
Test name
Test status
Simulation time 116968821 ps
CPU time 0.89 seconds
Started Mar 05 12:58:51 PM PST 24
Finished Mar 05 12:58:52 PM PST 24
Peak memory 195088 kb
Host smart-40b7027d-dfbd-4007-809b-a90b9611169e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60701244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.60701244
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1663906783
Short name T118
Test name
Test status
Simulation time 19034692 ps
CPU time 0.74 seconds
Started Mar 05 12:58:54 PM PST 24
Finished Mar 05 12:58:55 PM PST 24
Peak memory 195468 kb
Host smart-467f6049-81f1-4aff-8a3f-46a66442c068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663906783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1663906783
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3962649140
Short name T688
Test name
Test status
Simulation time 209559317 ps
CPU time 1.22 seconds
Started Mar 05 12:58:52 PM PST 24
Finished Mar 05 12:58:53 PM PST 24
Peak memory 197156 kb
Host smart-ddaec2ee-0522-4273-aa5c-9c1ada9c064d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962649140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3962649140
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2807099
Short name T690
Test name
Test status
Simulation time 288549656 ps
CPU time 3.98 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:06 PM PST 24
Peak memory 198136 kb
Host smart-c6e6172c-2f1e-4675-9d92-67d4c66565e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random
_long_reg_writes_reg_reads.2807099
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2436894724
Short name T42
Test name
Test status
Simulation time 89495539 ps
CPU time 0.94 seconds
Started Mar 05 12:59:01 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 214876 kb
Host smart-2df3322f-a8c0-4b90-9bce-8fe9007253df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436894724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2436894724
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1953233805
Short name T444
Test name
Test status
Simulation time 233215025 ps
CPU time 1.08 seconds
Started Mar 05 12:58:53 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195768 kb
Host smart-0ac8bc91-0013-4a60-8e00-b1fbd7c61937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953233805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1953233805
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2918580731
Short name T317
Test name
Test status
Simulation time 31002810 ps
CPU time 0.91 seconds
Started Mar 05 12:58:56 PM PST 24
Finished Mar 05 12:58:57 PM PST 24
Peak memory 196256 kb
Host smart-f6f0e76f-a313-4f9f-b18e-1d0ab57eb2ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918580731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2918580731
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2870680292
Short name T524
Test name
Test status
Simulation time 3532814800 ps
CPU time 46.66 seconds
Started Mar 05 12:58:58 PM PST 24
Finished Mar 05 12:59:45 PM PST 24
Peak memory 198300 kb
Host smart-d8dd5893-e2cd-4b40-b5b4-30f9efb3ef8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870680292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2870680292
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3908302407
Short name T65
Test name
Test status
Simulation time 221100043210 ps
CPU time 2478.45 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 01:40:23 PM PST 24
Peak memory 198476 kb
Host smart-8474c52c-f580-4945-a59d-65ef5858bfd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3908302407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3908302407
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4106351844
Short name T402
Test name
Test status
Simulation time 14317804 ps
CPU time 0.62 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 195000 kb
Host smart-12f49f0f-2647-4526-8f2b-56589bab5c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106351844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4106351844
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3527906944
Short name T29
Test name
Test status
Simulation time 77420357 ps
CPU time 0.75 seconds
Started Mar 05 01:00:39 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 195368 kb
Host smart-1144e3db-ef35-4593-a2ee-94069b41de81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527906944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3527906944
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2338252752
Short name T268
Test name
Test status
Simulation time 690236401 ps
CPU time 23.31 seconds
Started Mar 05 01:00:39 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 196884 kb
Host smart-7fdf72b0-387b-40e7-834c-d3a6cf024a76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338252752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2338252752
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2245205891
Short name T381
Test name
Test status
Simulation time 37718774 ps
CPU time 0.75 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 194772 kb
Host smart-7ab9c8ee-6c34-4e93-b5eb-209ac47daac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245205891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2245205891
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.619108738
Short name T505
Test name
Test status
Simulation time 73097542 ps
CPU time 1.27 seconds
Started Mar 05 01:00:34 PM PST 24
Finished Mar 05 01:00:35 PM PST 24
Peak memory 197016 kb
Host smart-428a48cc-61cb-4810-984d-93f083611deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619108738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.619108738
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1220212491
Short name T629
Test name
Test status
Simulation time 43247098 ps
CPU time 1.03 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 196392 kb
Host smart-7c82fd98-0915-4d1a-8d80-49c7cde3ecba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220212491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1220212491
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2126972116
Short name T61
Test name
Test status
Simulation time 77396724 ps
CPU time 1.67 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 196024 kb
Host smart-6dc60806-e6d8-4c19-b7a2-f1cb821b98b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126972116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2126972116
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1501029445
Short name T219
Test name
Test status
Simulation time 87732949 ps
CPU time 0.95 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 195912 kb
Host smart-d3ef9ac4-fc54-48a1-9315-4860da33c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501029445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1501029445
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.894397859
Short name T235
Test name
Test status
Simulation time 55993261 ps
CPU time 1.26 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 195972 kb
Host smart-52c2605c-967c-4389-9f2b-ba05642a6199
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894397859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.894397859
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3099218190
Short name T421
Test name
Test status
Simulation time 170315252 ps
CPU time 2.26 seconds
Started Mar 05 01:00:34 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 198220 kb
Host smart-8b02906b-26d1-4cd0-9315-fedd3a9e5f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099218190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3099218190
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1724704285
Short name T628
Test name
Test status
Simulation time 304761105 ps
CPU time 1.3 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 196548 kb
Host smart-ead3b135-9fa6-48ec-b1eb-880c5f19d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724704285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1724704285
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2320453191
Short name T175
Test name
Test status
Simulation time 113444731 ps
CPU time 1.21 seconds
Started Mar 05 01:00:35 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 196376 kb
Host smart-bfc0b103-20d6-4535-9957-bff5627ce9d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320453191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2320453191
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3902925331
Short name T5
Test name
Test status
Simulation time 110162631228 ps
CPU time 148.68 seconds
Started Mar 05 01:00:40 PM PST 24
Finished Mar 05 01:03:09 PM PST 24
Peak memory 198332 kb
Host smart-cc8b6a56-6d02-4bf3-bc30-063be517c8f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902925331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3902925331
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3948282818
Short name T12
Test name
Test status
Simulation time 12901298 ps
CPU time 0.61 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 194348 kb
Host smart-d418a855-4e44-4a24-b8ca-30c1505c3507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948282818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3948282818
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1022207681
Short name T314
Test name
Test status
Simulation time 495176172 ps
CPU time 0.85 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 196532 kb
Host smart-d52486b4-bd9a-445f-b434-6e68394a8fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022207681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1022207681
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1334473547
Short name T254
Test name
Test status
Simulation time 494822761 ps
CPU time 13.51 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 195676 kb
Host smart-49aeb2c0-4899-4232-97b9-e044889fed60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334473547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1334473547
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3169895704
Short name T543
Test name
Test status
Simulation time 205242832 ps
CPU time 0.84 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 196644 kb
Host smart-6a0a27e5-3204-4c6f-a1b8-fc5291271814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169895704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3169895704
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1634780822
Short name T71
Test name
Test status
Simulation time 90486080 ps
CPU time 1.53 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 197080 kb
Host smart-851a32e6-00a6-450b-869d-c3d884193f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634780822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1634780822
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.421107107
Short name T223
Test name
Test status
Simulation time 53717604 ps
CPU time 2.36 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 198132 kb
Host smart-21cf0885-a981-4880-ae06-3451d5630c7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421107107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.421107107
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1695294015
Short name T295
Test name
Test status
Simulation time 1870173138 ps
CPU time 2.81 seconds
Started Mar 05 01:00:40 PM PST 24
Finished Mar 05 01:00:43 PM PST 24
Peak memory 198232 kb
Host smart-364189bf-36db-4df5-8360-ec68440f8f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695294015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1695294015
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.896510158
Short name T644
Test name
Test status
Simulation time 179150154 ps
CPU time 0.77 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 195360 kb
Host smart-5368456c-9d95-407e-93b2-8c312203abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896510158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.896510158
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4119056058
Short name T481
Test name
Test status
Simulation time 51433978 ps
CPU time 1.04 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 196084 kb
Host smart-d93a2d77-9128-418a-8059-12a58f3d0cca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119056058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4119056058
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3823741323
Short name T467
Test name
Test status
Simulation time 265595344 ps
CPU time 5.99 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:42 PM PST 24
Peak memory 198044 kb
Host smart-07b12456-14ad-4cc8-92ed-535bb4cb14f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823741323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3823741323
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2915569521
Short name T62
Test name
Test status
Simulation time 474538417 ps
CPU time 1.33 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 195820 kb
Host smart-56658cd5-5217-470e-a7a9-da4ca6775338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915569521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2915569521
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3652273635
Short name T194
Test name
Test status
Simulation time 198268578 ps
CPU time 1.16 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 195984 kb
Host smart-e502f148-df5e-49b4-a731-5467bd6080da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652273635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3652273635
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4249128145
Short name T430
Test name
Test status
Simulation time 17271659430 ps
CPU time 233.72 seconds
Started Mar 05 01:00:34 PM PST 24
Finished Mar 05 01:04:28 PM PST 24
Peak memory 198272 kb
Host smart-094fe0de-9e65-40c0-a73f-1d90ed7498d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249128145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4249128145
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.832484721
Short name T316
Test name
Test status
Simulation time 32555182 ps
CPU time 0.55 seconds
Started Mar 05 01:00:35 PM PST 24
Finished Mar 05 01:00:36 PM PST 24
Peak memory 194060 kb
Host smart-e08408cb-1fb9-467e-8b3d-6f8ae4f9adcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832484721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.832484721
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3385932423
Short name T633
Test name
Test status
Simulation time 89510670 ps
CPU time 0.67 seconds
Started Mar 05 01:00:43 PM PST 24
Finished Mar 05 01:00:44 PM PST 24
Peak memory 194812 kb
Host smart-88d18cfb-28a4-4c76-8596-8ea4ddaf5cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385932423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3385932423
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1620427796
Short name T246
Test name
Test status
Simulation time 238110010 ps
CPU time 10.69 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:48 PM PST 24
Peak memory 198148 kb
Host smart-af46ff7c-a2ba-463d-9b9b-680e30ac68db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620427796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1620427796
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.354151195
Short name T459
Test name
Test status
Simulation time 86329042 ps
CPU time 1.1 seconds
Started Mar 05 01:00:40 PM PST 24
Finished Mar 05 01:00:41 PM PST 24
Peak memory 197848 kb
Host smart-69c4fd60-c3be-466b-8a3a-c948e49be8a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354151195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.354151195
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.940981033
Short name T610
Test name
Test status
Simulation time 28745963 ps
CPU time 0.75 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 196344 kb
Host smart-28f92d7c-8d0d-4ad9-ac74-b94169897835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940981033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.940981033
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2659193509
Short name T188
Test name
Test status
Simulation time 89057900 ps
CPU time 3.54 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:42 PM PST 24
Peak memory 198204 kb
Host smart-c107a525-e89b-4fd9-8c79-4762bbdffae5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659193509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2659193509
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2275377894
Short name T520
Test name
Test status
Simulation time 542992359 ps
CPU time 1.43 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 196816 kb
Host smart-e2a4446d-cbf4-48fb-9af2-d58b267e7084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275377894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2275377894
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3607136113
Short name T362
Test name
Test status
Simulation time 318127368 ps
CPU time 0.92 seconds
Started Mar 05 01:00:38 PM PST 24
Finished Mar 05 01:00:39 PM PST 24
Peak memory 195904 kb
Host smart-a66bc141-7e0d-4422-893a-ce0cdc377ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607136113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3607136113
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.589065023
Short name T619
Test name
Test status
Simulation time 288755892 ps
CPU time 1.44 seconds
Started Mar 05 01:00:37 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 198068 kb
Host smart-ba122c77-e8e8-4404-a81d-4d25c23b45f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589065023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.589065023
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1213715110
Short name T378
Test name
Test status
Simulation time 123125854 ps
CPU time 3.09 seconds
Started Mar 05 01:00:39 PM PST 24
Finished Mar 05 01:00:42 PM PST 24
Peak memory 198112 kb
Host smart-247f0970-4933-4b59-81cb-0176ab4beb6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213715110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1213715110
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2976752417
Short name T510
Test name
Test status
Simulation time 120716860 ps
CPU time 1.31 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 198136 kb
Host smart-21a9e6a9-a568-4cd2-8605-28cd43f6e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976752417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2976752417
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1295711426
Short name T296
Test name
Test status
Simulation time 83124182 ps
CPU time 1.15 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 196636 kb
Host smart-025d1231-09ba-4f20-88f4-6dc5aed5edb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295711426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1295711426
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1900730940
Short name T270
Test name
Test status
Simulation time 14356575448 ps
CPU time 160.79 seconds
Started Mar 05 01:00:40 PM PST 24
Finished Mar 05 01:03:21 PM PST 24
Peak memory 198364 kb
Host smart-63c94912-a55d-450e-94e3-0cdfe188e13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900730940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1900730940
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.662378575
Short name T328
Test name
Test status
Simulation time 14524450 ps
CPU time 0.64 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:49 PM PST 24
Peak memory 194004 kb
Host smart-514c97c6-65c8-4632-9a05-1f197fe5a642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662378575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.662378575
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.182871777
Short name T348
Test name
Test status
Simulation time 26637048 ps
CPU time 0.83 seconds
Started Mar 05 01:00:42 PM PST 24
Finished Mar 05 01:00:43 PM PST 24
Peak memory 195316 kb
Host smart-b893df17-5586-4b75-941f-3bab21704c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182871777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.182871777
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3760793601
Short name T186
Test name
Test status
Simulation time 206735180 ps
CPU time 7.74 seconds
Started Mar 05 01:00:43 PM PST 24
Finished Mar 05 01:00:51 PM PST 24
Peak memory 198140 kb
Host smart-74351b2c-0197-490a-b8aa-736a5746a5ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760793601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3760793601
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.270395721
Short name T575
Test name
Test status
Simulation time 74153780 ps
CPU time 0.79 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:52 PM PST 24
Peak memory 195700 kb
Host smart-9680e9a0-2e80-424b-82f6-294d16f70fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270395721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.270395721
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2376955129
Short name T311
Test name
Test status
Simulation time 112623942 ps
CPU time 0.82 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 195492 kb
Host smart-8a5966d5-1971-4a73-b4d9-8eb195ac5fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376955129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2376955129
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2175514672
Short name T529
Test name
Test status
Simulation time 464483248 ps
CPU time 2.67 seconds
Started Mar 05 01:00:44 PM PST 24
Finished Mar 05 01:00:47 PM PST 24
Peak memory 198096 kb
Host smart-be64989c-2eb5-484d-af78-94ab5d2a9af5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175514672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2175514672
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4078218401
Short name T582
Test name
Test status
Simulation time 361650612 ps
CPU time 1.98 seconds
Started Mar 05 01:00:44 PM PST 24
Finished Mar 05 01:00:46 PM PST 24
Peak memory 197116 kb
Host smart-bdcb1ebb-3e08-4cb8-b3b9-dce45d42c0a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078218401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4078218401
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.585374190
Short name T130
Test name
Test status
Simulation time 63123924 ps
CPU time 0.85 seconds
Started Mar 05 01:00:39 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 197420 kb
Host smart-d303c783-5d10-488b-820d-a2962b78b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585374190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.585374190
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3336917481
Short name T462
Test name
Test status
Simulation time 68835410 ps
CPU time 1.1 seconds
Started Mar 05 01:00:42 PM PST 24
Finished Mar 05 01:00:43 PM PST 24
Peak memory 196012 kb
Host smart-54e24756-9359-47fb-9015-e9a8fe9bfdb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336917481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3336917481
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1419227359
Short name T595
Test name
Test status
Simulation time 1122778430 ps
CPU time 4.85 seconds
Started Mar 05 01:00:44 PM PST 24
Finished Mar 05 01:00:49 PM PST 24
Peak memory 198004 kb
Host smart-7e714d62-752d-4f9d-b2e2-c1faceab0d14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419227359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1419227359
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3199063981
Short name T196
Test name
Test status
Simulation time 157631833 ps
CPU time 0.94 seconds
Started Mar 05 01:00:36 PM PST 24
Finished Mar 05 01:00:37 PM PST 24
Peak memory 196268 kb
Host smart-2e6d50f4-274e-404c-a223-4424f396615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199063981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3199063981
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3377713426
Short name T329
Test name
Test status
Simulation time 891897988 ps
CPU time 1.37 seconds
Started Mar 05 01:00:34 PM PST 24
Finished Mar 05 01:00:35 PM PST 24
Peak memory 195652 kb
Host smart-bcb3383d-63c3-4c3b-a014-60cc217bf747
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377713426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3377713426
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4146599085
Short name T169
Test name
Test status
Simulation time 4470248847 ps
CPU time 64.28 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:01:53 PM PST 24
Peak memory 198296 kb
Host smart-30ce1f4d-3ada-42df-bda8-a3a7f2f01f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146599085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4146599085
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1842584893
Short name T618
Test name
Test status
Simulation time 12315623 ps
CPU time 0.64 seconds
Started Mar 05 01:00:47 PM PST 24
Finished Mar 05 01:00:48 PM PST 24
Peak memory 195044 kb
Host smart-5152accd-48cc-4d4a-816d-ef2c187c92cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842584893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1842584893
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.94802422
Short name T578
Test name
Test status
Simulation time 48882796 ps
CPU time 0.62 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:52 PM PST 24
Peak memory 194796 kb
Host smart-3c328942-53eb-4488-9d4b-49091382f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94802422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.94802422
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1541911035
Short name T184
Test name
Test status
Simulation time 3962653329 ps
CPU time 26.88 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 198204 kb
Host smart-43957ab2-a3fa-425f-9ca6-093e22bb1d98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541911035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1541911035
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.568161801
Short name T303
Test name
Test status
Simulation time 53850813 ps
CPU time 0.71 seconds
Started Mar 05 01:00:47 PM PST 24
Finished Mar 05 01:00:48 PM PST 24
Peak memory 195324 kb
Host smart-93ce9c67-dd94-4a56-9738-61bb1cf93968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568161801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.568161801
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2602219091
Short name T323
Test name
Test status
Simulation time 147259727 ps
CPU time 1.31 seconds
Started Mar 05 01:00:54 PM PST 24
Finished Mar 05 01:00:56 PM PST 24
Peak memory 197032 kb
Host smart-54260480-0d91-4b78-b174-f85a41b6c54b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602219091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2602219091
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1361382998
Short name T298
Test name
Test status
Simulation time 38693659 ps
CPU time 1.61 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:53 PM PST 24
Peak memory 196420 kb
Host smart-a02a19b7-3acf-4421-9e6f-6e8a54f816cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361382998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1361382998
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2030332783
Short name T279
Test name
Test status
Simulation time 246521058 ps
CPU time 1.45 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 196096 kb
Host smart-5178937d-8e65-4ab9-92ff-47c66c571b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030332783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2030332783
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.734558676
Short name T647
Test name
Test status
Simulation time 72412803 ps
CPU time 1.35 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:53 PM PST 24
Peak memory 198164 kb
Host smart-bc66b51d-07ca-404e-91c3-e920a3922f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734558676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.734558676
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.283567914
Short name T646
Test name
Test status
Simulation time 151923069 ps
CPU time 0.94 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:53 PM PST 24
Peak memory 196864 kb
Host smart-e524d647-3a02-4d12-a034-ac9249e21db9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283567914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.283567914
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1963720496
Short name T74
Test name
Test status
Simulation time 223169076 ps
CPU time 4.88 seconds
Started Mar 05 01:00:49 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 198140 kb
Host smart-18573fe0-8eb9-4966-b784-f5f5860f4552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963720496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1963720496
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.552675439
Short name T493
Test name
Test status
Simulation time 190318028 ps
CPU time 1.47 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:52 PM PST 24
Peak memory 198048 kb
Host smart-ed5103b4-f18f-467f-a572-faa934c97670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552675439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.552675439
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2530837140
Short name T594
Test name
Test status
Simulation time 272962523 ps
CPU time 1.19 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 195964 kb
Host smart-090cf66c-ec83-4507-9675-cb262ae051cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530837140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2530837140
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.303586459
Short name T514
Test name
Test status
Simulation time 67921979260 ps
CPU time 182.89 seconds
Started Mar 05 01:00:54 PM PST 24
Finished Mar 05 01:03:57 PM PST 24
Peak memory 198164 kb
Host smart-aa9a534e-978c-4a51-87e0-6aea0c7a2d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303586459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.303586459
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1134233628
Short name T533
Test name
Test status
Simulation time 28086310 ps
CPU time 0.54 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:53 PM PST 24
Peak memory 194096 kb
Host smart-f33fd48e-5be1-48a2-b3bd-35a188e3fc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134233628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1134233628
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2213518116
Short name T310
Test name
Test status
Simulation time 26420875 ps
CPU time 0.82 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:49 PM PST 24
Peak memory 195420 kb
Host smart-dbe722ad-a1f2-4586-a4a1-da1897926396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213518116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2213518116
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4022881211
Short name T630
Test name
Test status
Simulation time 3922869934 ps
CPU time 18.36 seconds
Started Mar 05 01:00:49 PM PST 24
Finished Mar 05 01:01:08 PM PST 24
Peak memory 196944 kb
Host smart-5372125a-0e77-4151-8d0a-0a001d91b22e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022881211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4022881211
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2113784934
Short name T531
Test name
Test status
Simulation time 88205368 ps
CPU time 0.75 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 196636 kb
Host smart-560af0eb-05c4-4ec9-b21f-570f2c45f98a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113784934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2113784934
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3066881507
Short name T593
Test name
Test status
Simulation time 300662735 ps
CPU time 1.19 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:52 PM PST 24
Peak memory 196152 kb
Host smart-b9dad474-50fd-4b56-810b-7780f28a8ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066881507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3066881507
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1927934062
Short name T414
Test name
Test status
Simulation time 904265520 ps
CPU time 3.47 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:55 PM PST 24
Peak memory 198152 kb
Host smart-7edc19d0-0c11-4433-95c1-b21c9ed5fffc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927934062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1927934062
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1674624263
Short name T113
Test name
Test status
Simulation time 180313054 ps
CPU time 1.9 seconds
Started Mar 05 01:00:47 PM PST 24
Finished Mar 05 01:00:49 PM PST 24
Peak memory 196260 kb
Host smart-52b35c8b-b1b1-4240-8c41-c98ed821a3f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674624263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1674624263
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1309227405
Short name T343
Test name
Test status
Simulation time 87491104 ps
CPU time 0.97 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 196124 kb
Host smart-f4bc3877-6efe-4322-9389-54b42478d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309227405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1309227405
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.571896943
Short name T365
Test name
Test status
Simulation time 107394883 ps
CPU time 1.04 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:00:52 PM PST 24
Peak memory 196824 kb
Host smart-cf95fb27-099d-4bc9-bc0e-482b83303252
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571896943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.571896943
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3269553739
Short name T601
Test name
Test status
Simulation time 320196036 ps
CPU time 4.2 seconds
Started Mar 05 01:00:49 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 198100 kb
Host smart-0d0569ec-fd19-4fc2-a07e-455419a00724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269553739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3269553739
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3315671557
Short name T558
Test name
Test status
Simulation time 152375731 ps
CPU time 1.24 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 198136 kb
Host smart-ac6f9068-d940-4538-868b-b57cb643704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315671557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3315671557
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.372053761
Short name T691
Test name
Test status
Simulation time 78478057 ps
CPU time 1.37 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 196780 kb
Host smart-bbdf896d-e835-48e8-b5cd-531b1b2f1e72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372053761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.372053761
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2772325198
Short name T652
Test name
Test status
Simulation time 27951828700 ps
CPU time 169.3 seconds
Started Mar 05 01:00:50 PM PST 24
Finished Mar 05 01:03:39 PM PST 24
Peak memory 198324 kb
Host smart-4a19faf5-dfca-472b-ae50-181a60fb9c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772325198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2772325198
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1392925955
Short name T19
Test name
Test status
Simulation time 54478240 ps
CPU time 0.6 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 194080 kb
Host smart-c64d1c82-df71-4968-85f1-9bd48bbe2ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392925955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1392925955
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4154812617
Short name T588
Test name
Test status
Simulation time 26042941 ps
CPU time 0.64 seconds
Started Mar 05 01:00:49 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 193976 kb
Host smart-244d23b2-73bc-40e5-8423-7304ce8b137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154812617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4154812617
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3052728207
Short name T561
Test name
Test status
Simulation time 670382825 ps
CPU time 7.41 seconds
Started Mar 05 01:01:04 PM PST 24
Finished Mar 05 01:01:12 PM PST 24
Peak memory 198012 kb
Host smart-eed9321a-6d25-453d-bde5-2480340bc79f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052728207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3052728207
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3864796853
Short name T546
Test name
Test status
Simulation time 90530835 ps
CPU time 0.76 seconds
Started Mar 05 01:00:59 PM PST 24
Finished Mar 05 01:01:00 PM PST 24
Peak memory 195852 kb
Host smart-2ca3aa05-fc8e-41f8-933a-6df42bb18c12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864796853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3864796853
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2664510248
Short name T585
Test name
Test status
Simulation time 171106140 ps
CPU time 0.77 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 195556 kb
Host smart-89a7e910-6552-4193-9e52-ee3b9458e8b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664510248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2664510248
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2207594929
Short name T410
Test name
Test status
Simulation time 208554771 ps
CPU time 2.64 seconds
Started Mar 05 01:00:59 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 198116 kb
Host smart-f9273093-30e8-442c-82e0-02a40970fc9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207594929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2207594929
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3084290750
Short name T404
Test name
Test status
Simulation time 431268039 ps
CPU time 2.74 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:05 PM PST 24
Peak memory 197112 kb
Host smart-b489cc16-4dce-49ea-b570-526919ca575c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084290750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3084290750
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2091371097
Short name T144
Test name
Test status
Simulation time 91777464 ps
CPU time 1.02 seconds
Started Mar 05 01:00:48 PM PST 24
Finished Mar 05 01:00:49 PM PST 24
Peak memory 196020 kb
Host smart-804ec4de-5ce2-4841-a4ec-fb4eca975069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091371097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2091371097
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1859241811
Short name T596
Test name
Test status
Simulation time 239067922 ps
CPU time 1.2 seconds
Started Mar 05 01:00:51 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 198040 kb
Host smart-8ea67e0c-3c75-4d8f-9af0-d918a689b473
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859241811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1859241811
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1347787726
Short name T446
Test name
Test status
Simulation time 87196133 ps
CPU time 4.26 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:05 PM PST 24
Peak memory 198108 kb
Host smart-28888220-aafc-4667-a2d8-eece447cac58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347787726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1347787726
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1817204708
Short name T255
Test name
Test status
Simulation time 161289651 ps
CPU time 1.3 seconds
Started Mar 05 01:00:49 PM PST 24
Finished Mar 05 01:00:50 PM PST 24
Peak memory 195632 kb
Host smart-5dcd2123-b42d-4fbb-9337-87f8fa4e8664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817204708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1817204708
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3536017834
Short name T257
Test name
Test status
Simulation time 37898529 ps
CPU time 0.74 seconds
Started Mar 05 01:00:52 PM PST 24
Finished Mar 05 01:00:54 PM PST 24
Peak memory 194224 kb
Host smart-80cab6d9-f20a-4fef-b7fd-6043d9d003a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536017834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3536017834
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.371852480
Short name T528
Test name
Test status
Simulation time 58242247731 ps
CPU time 182.96 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:04:03 PM PST 24
Peak memory 198312 kb
Host smart-46ac6e57-585d-4aed-a988-eaf9dd78c26f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371852480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.371852480
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.315953416
Short name T636
Test name
Test status
Simulation time 80382987030 ps
CPU time 1500.73 seconds
Started Mar 05 01:01:07 PM PST 24
Finished Mar 05 01:26:08 PM PST 24
Peak memory 198448 kb
Host smart-f93a5888-e138-4c14-a998-7e31fc86c341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=315953416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.315953416
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3088922680
Short name T239
Test name
Test status
Simulation time 47792146 ps
CPU time 0.57 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:00 PM PST 24
Peak memory 194764 kb
Host smart-198a73ed-6cad-4392-9e46-928d26f745b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088922680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3088922680
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2052595227
Short name T396
Test name
Test status
Simulation time 81883603 ps
CPU time 0.96 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 197320 kb
Host smart-bff627d1-bc41-41c7-b530-efca7863d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052595227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2052595227
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2786509839
Short name T532
Test name
Test status
Simulation time 1452855347 ps
CPU time 27.24 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 198056 kb
Host smart-fca41d4f-fa21-4bbd-a593-f1a218429890
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786509839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2786509839
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2281152661
Short name T672
Test name
Test status
Simulation time 28011060 ps
CPU time 0.68 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 195248 kb
Host smart-1e2dcd29-b761-4a66-8305-ff4f17d06aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281152661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2281152661
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2748834124
Short name T550
Test name
Test status
Simulation time 30507433 ps
CPU time 0.9 seconds
Started Mar 05 01:00:59 PM PST 24
Finished Mar 05 01:01:00 PM PST 24
Peak memory 196616 kb
Host smart-5973f6d5-8ada-48d9-b9b5-8363e5422577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748834124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2748834124
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4060566940
Short name T280
Test name
Test status
Simulation time 28731309 ps
CPU time 1.26 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 198180 kb
Host smart-d042bd68-984e-4f10-b7db-7db4175642b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060566940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4060566940
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2193714775
Short name T325
Test name
Test status
Simulation time 383413655 ps
CPU time 2.21 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 197208 kb
Host smart-e857a8a2-2444-4945-ad68-fafecd133c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193714775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2193714775
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3110383023
Short name T411
Test name
Test status
Simulation time 70596883 ps
CPU time 0.71 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 196220 kb
Host smart-b74fc6e8-4eef-429a-ad38-06c68fe7bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110383023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3110383023
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1544937352
Short name T536
Test name
Test status
Simulation time 163743015 ps
CPU time 0.76 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:06 PM PST 24
Peak memory 195360 kb
Host smart-f4641636-184b-49f7-9db5-312eba0c4acf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544937352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1544937352
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1717654010
Short name T44
Test name
Test status
Simulation time 275008776 ps
CPU time 4.78 seconds
Started Mar 05 01:01:03 PM PST 24
Finished Mar 05 01:01:08 PM PST 24
Peak memory 198012 kb
Host smart-003a1984-9ef5-4e33-a474-85528c1ad021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717654010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1717654010
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1494217924
Short name T475
Test name
Test status
Simulation time 131382320 ps
CPU time 1.04 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 195868 kb
Host smart-51cff48c-86eb-4b6c-bd5b-6246d6a1141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494217924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1494217924
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.825968385
Short name T453
Test name
Test status
Simulation time 65784447 ps
CPU time 1.12 seconds
Started Mar 05 01:01:07 PM PST 24
Finished Mar 05 01:01:09 PM PST 24
Peak memory 195872 kb
Host smart-49212203-cf3f-4285-a3d9-281cface80e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825968385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.825968385
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2787014851
Short name T359
Test name
Test status
Simulation time 30633553862 ps
CPU time 120.42 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:03:02 PM PST 24
Peak memory 198312 kb
Host smart-05fa86ad-1c12-4844-964b-f18bc879c300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787014851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2787014851
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1579120558
Short name T259
Test name
Test status
Simulation time 123832224 ps
CPU time 0.61 seconds
Started Mar 05 01:00:59 PM PST 24
Finished Mar 05 01:01:00 PM PST 24
Peak memory 194080 kb
Host smart-e0336867-fa5e-432a-b5ac-c5a1a6ec9a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579120558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1579120558
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2144581011
Short name T187
Test name
Test status
Simulation time 57811070 ps
CPU time 0.72 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 194152 kb
Host smart-c7c620a3-d6a1-443d-8489-514ff0e8a581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144581011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2144581011
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1553616361
Short name T499
Test name
Test status
Simulation time 1922098006 ps
CPU time 4.2 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:10 PM PST 24
Peak memory 195760 kb
Host smart-15f905e6-473d-47e0-8bea-b57a0c6db0af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553616361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1553616361
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1101853417
Short name T247
Test name
Test status
Simulation time 58409672 ps
CPU time 0.81 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:06 PM PST 24
Peak memory 196604 kb
Host smart-d8c55db7-2547-4d35-b988-8a8505242cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101853417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1101853417
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.4125683850
Short name T286
Test name
Test status
Simulation time 254122399 ps
CPU time 1.08 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 196900 kb
Host smart-0c2d227a-26dd-4d0a-a0d6-97bae1e95188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125683850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.4125683850
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3924492612
Short name T272
Test name
Test status
Simulation time 116545182 ps
CPU time 1.39 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:06 PM PST 24
Peak memory 196560 kb
Host smart-08c27946-28f1-4dc2-b3cc-88d0b2f7169d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924492612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3924492612
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.104520237
Short name T614
Test name
Test status
Simulation time 303514443 ps
CPU time 3.42 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:05 PM PST 24
Peak memory 197072 kb
Host smart-e93efbd8-000e-4c2f-b23b-fbaf8c229a67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104520237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
104520237
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.608974681
Short name T419
Test name
Test status
Simulation time 29914528 ps
CPU time 0.69 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 195100 kb
Host smart-d8fc8e33-0c37-4c38-88e3-fb393839058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608974681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.608974681
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3214077922
Short name T293
Test name
Test status
Simulation time 25210806 ps
CPU time 0.98 seconds
Started Mar 05 01:01:03 PM PST 24
Finished Mar 05 01:01:04 PM PST 24
Peak memory 195796 kb
Host smart-f2517df9-bbf1-487e-81ba-880257d007a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214077922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3214077922
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.333770707
Short name T521
Test name
Test status
Simulation time 645590000 ps
CPU time 2.51 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:07 PM PST 24
Peak memory 198048 kb
Host smart-8f3abbfa-1c5e-4a1c-8e58-0ca3c16f494b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333770707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.333770707
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1278643533
Short name T283
Test name
Test status
Simulation time 204315882 ps
CPU time 0.9 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 196508 kb
Host smart-14a5cf16-af96-4573-86ab-d9024ef78395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278643533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1278643533
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3785968449
Short name T291
Test name
Test status
Simulation time 182594217 ps
CPU time 0.92 seconds
Started Mar 05 01:01:07 PM PST 24
Finished Mar 05 01:01:08 PM PST 24
Peak memory 195952 kb
Host smart-7d9d525b-b35b-4a41-894c-000e2d6e02c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785968449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3785968449
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1208947728
Short name T498
Test name
Test status
Simulation time 18881548293 ps
CPU time 113.56 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:02:59 PM PST 24
Peak memory 198304 kb
Host smart-7cf0cdd3-72b7-4d0a-bdbf-6f3a76ea86df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208947728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1208947728
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1655705290
Short name T635
Test name
Test status
Simulation time 85201717178 ps
CPU time 2018.05 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:34:41 PM PST 24
Peak memory 198500 kb
Host smart-d78e02fe-b10a-44d2-a158-a15441414096
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1655705290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1655705290
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1488161612
Short name T308
Test name
Test status
Simulation time 18897284 ps
CPU time 0.57 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 194784 kb
Host smart-a9d66d8b-97eb-40aa-9ed5-bd8590b035ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488161612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1488161612
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.473435372
Short name T671
Test name
Test status
Simulation time 123085673 ps
CPU time 0.86 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 197416 kb
Host smart-e16512d0-77be-4a0e-af52-bf9c5cce7a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473435372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.473435372
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1899273607
Short name T183
Test name
Test status
Simulation time 134604924 ps
CPU time 4.42 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:07 PM PST 24
Peak memory 196832 kb
Host smart-877aba61-af13-4cf1-815f-19aa7c0e14a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899273607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1899273607
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.4153121130
Short name T20
Test name
Test status
Simulation time 83295610 ps
CPU time 1.01 seconds
Started Mar 05 01:01:03 PM PST 24
Finished Mar 05 01:01:05 PM PST 24
Peak memory 197924 kb
Host smart-ecb13b5e-ef0d-4b66-81df-490e1e34d082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153121130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.4153121130
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3172662764
Short name T146
Test name
Test status
Simulation time 42983652 ps
CPU time 1.27 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 196928 kb
Host smart-ff1a3811-3411-4aef-8b1e-854080fe548c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172662764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3172662764
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2011371457
Short name T511
Test name
Test status
Simulation time 79138871 ps
CPU time 3.05 seconds
Started Mar 05 01:01:03 PM PST 24
Finished Mar 05 01:01:07 PM PST 24
Peak memory 197364 kb
Host smart-5b41ca89-e297-4f76-a82e-707e9b0fd919
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011371457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2011371457
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.545333636
Short name T408
Test name
Test status
Simulation time 24736108 ps
CPU time 1.07 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 195612 kb
Host smart-f7f06c1c-0a7f-4e14-889a-67f013063294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545333636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
545333636
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2388836055
Short name T663
Test name
Test status
Simulation time 23602485 ps
CPU time 0.97 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 196128 kb
Host smart-51c41ce0-5261-49aa-a92d-5a05060ec48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388836055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2388836055
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2096162807
Short name T240
Test name
Test status
Simulation time 468680432 ps
CPU time 2.03 seconds
Started Mar 05 01:01:01 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 198096 kb
Host smart-25b8ad30-2fd9-49c1-8189-0304be2bd3f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096162807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2096162807
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4264877229
Short name T155
Test name
Test status
Simulation time 108579900 ps
CPU time 1.56 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:07 PM PST 24
Peak memory 196824 kb
Host smart-f1e50dbb-644a-45d1-a0c1-0be2f91126c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264877229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4264877229
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1112910814
Short name T669
Test name
Test status
Simulation time 75177108 ps
CPU time 1.26 seconds
Started Mar 05 01:01:00 PM PST 24
Finished Mar 05 01:01:01 PM PST 24
Peak memory 196904 kb
Host smart-0e0ccff5-452a-40fe-8df5-c40ad8d3917b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112910814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1112910814
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1530625531
Short name T685
Test name
Test status
Simulation time 49201180008 ps
CPU time 111.31 seconds
Started Mar 05 01:01:04 PM PST 24
Finished Mar 05 01:02:56 PM PST 24
Peak memory 198244 kb
Host smart-6041b870-3250-4a14-b770-7d6ff612c72e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530625531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1530625531
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1023311731
Short name T349
Test name
Test status
Simulation time 21502745 ps
CPU time 0.56 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:04 PM PST 24
Peak memory 194116 kb
Host smart-41505a5e-6671-47a6-be87-447ea8cdc964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023311731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1023311731
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2437582753
Short name T399
Test name
Test status
Simulation time 80603279 ps
CPU time 0.77 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:03 PM PST 24
Peak memory 196124 kb
Host smart-104e0484-c5a8-4191-b310-3cf9ea018e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437582753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2437582753
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3203302788
Short name T157
Test name
Test status
Simulation time 1096967846 ps
CPU time 16.43 seconds
Started Mar 05 12:59:09 PM PST 24
Finished Mar 05 12:59:26 PM PST 24
Peak memory 198144 kb
Host smart-6160621a-d396-4cbd-815c-ac63d922d443
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203302788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3203302788
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3323996958
Short name T339
Test name
Test status
Simulation time 63805536 ps
CPU time 0.88 seconds
Started Mar 05 12:59:01 PM PST 24
Finished Mar 05 12:59:03 PM PST 24
Peak memory 196680 kb
Host smart-2b744dc1-0214-4b86-bdde-e590ea07547b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323996958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3323996958
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1126773462
Short name T336
Test name
Test status
Simulation time 1401566977 ps
CPU time 1.49 seconds
Started Mar 05 12:59:00 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 197312 kb
Host smart-48cbc4ef-9546-40d4-90ad-bf7a9860f4f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126773462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1126773462
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3396593267
Short name T486
Test name
Test status
Simulation time 66087595 ps
CPU time 2.66 seconds
Started Mar 05 12:59:09 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 196576 kb
Host smart-33b968f1-a6ef-48f6-a160-c1c816548675
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396593267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3396593267
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3757948966
Short name T598
Test name
Test status
Simulation time 120490080 ps
CPU time 2.69 seconds
Started Mar 05 12:59:04 PM PST 24
Finished Mar 05 12:59:07 PM PST 24
Peak memory 196904 kb
Host smart-1108058e-3cd0-4d8a-b821-d2aa64820626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757948966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3757948966
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3792488581
Short name T110
Test name
Test status
Simulation time 118532100 ps
CPU time 1.19 seconds
Started Mar 05 12:59:01 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 198144 kb
Host smart-aeea8d08-b344-424c-bf85-60b9b8abc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792488581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3792488581
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.544331887
Short name T218
Test name
Test status
Simulation time 43676776 ps
CPU time 0.9 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:04 PM PST 24
Peak memory 196776 kb
Host smart-42469d15-777f-40c3-83a3-e68142e19a68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544331887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.544331887
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3944378474
Short name T564
Test name
Test status
Simulation time 30591130 ps
CPU time 1.45 seconds
Started Mar 05 12:58:59 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 198140 kb
Host smart-75eca21e-4171-492c-a1a8-289c60f410cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944378474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3944378474
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.1087719640
Short name T273
Test name
Test status
Simulation time 116236165 ps
CPU time 0.83 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:03 PM PST 24
Peak memory 195988 kb
Host smart-083f035f-b721-428a-a6a3-f057f8ebd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087719640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1087719640
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.143444871
Short name T249
Test name
Test status
Simulation time 135881355 ps
CPU time 1.04 seconds
Started Mar 05 12:59:01 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 195880 kb
Host smart-7c78b808-c82e-4c8b-b932-6234283f14d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143444871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.143444871
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.694321053
Short name T522
Test name
Test status
Simulation time 10286671713 ps
CPU time 150.64 seconds
Started Mar 05 12:59:08 PM PST 24
Finished Mar 05 01:01:39 PM PST 24
Peak memory 198320 kb
Host smart-cda3761f-cc07-40a2-aa2c-98dac3130395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694321053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.694321053
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.118332075
Short name T426
Test name
Test status
Simulation time 40481815 ps
CPU time 0.59 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 194020 kb
Host smart-28b8e6a9-f02c-4d04-adfd-b099f693daa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118332075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.118332075
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2545222411
Short name T555
Test name
Test status
Simulation time 32972482 ps
CPU time 0.86 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 195304 kb
Host smart-4b832326-c647-4f0e-8f5e-705718f5016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545222411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2545222411
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3436121006
Short name T253
Test name
Test status
Simulation time 2944277216 ps
CPU time 24.25 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:36 PM PST 24
Peak memory 197020 kb
Host smart-711e475b-316b-492b-84e4-227327a964a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436121006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3436121006
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1386774593
Short name T18
Test name
Test status
Simulation time 127421107 ps
CPU time 0.97 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:12 PM PST 24
Peak memory 196728 kb
Host smart-128c3431-488d-4b85-94e9-3aa49a75e56b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386774593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1386774593
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1438286714
Short name T30
Test name
Test status
Simulation time 33844126 ps
CPU time 0.67 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 194320 kb
Host smart-e1566778-1551-4193-bcdd-cd3e7f05f763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438286714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1438286714
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4126387820
Short name T379
Test name
Test status
Simulation time 236112714 ps
CPU time 2.6 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:20 PM PST 24
Peak memory 198128 kb
Host smart-47d20c74-6c18-4be8-8901-78c9bfa5342a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126387820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4126387820
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.309106056
Short name T269
Test name
Test status
Simulation time 358553705 ps
CPU time 1.56 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 196168 kb
Host smart-44a449fa-1f89-4ccd-8818-c350bf40c9c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309106056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
309106056
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3238562937
Short name T107
Test name
Test status
Simulation time 462077076 ps
CPU time 1.25 seconds
Started Mar 05 01:01:04 PM PST 24
Finished Mar 05 01:01:06 PM PST 24
Peak memory 197172 kb
Host smart-65de36f8-bc93-4e3a-84e2-64fba1bbf80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238562937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3238562937
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.82965031
Short name T382
Test name
Test status
Simulation time 29198777 ps
CPU time 0.63 seconds
Started Mar 05 01:01:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 194208 kb
Host smart-575e4644-ef2b-4c1a-bd74-24fc053c6b86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82965031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup_
pulldown.82965031
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2766528288
Short name T701
Test name
Test status
Simulation time 3635608366 ps
CPU time 3.4 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 197164 kb
Host smart-2342d392-9445-4a0d-8389-bc77690ccc38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766528288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2766528288
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2826477293
Short name T473
Test name
Test status
Simulation time 141404955 ps
CPU time 1.41 seconds
Started Mar 05 01:01:04 PM PST 24
Finished Mar 05 01:01:05 PM PST 24
Peak memory 198104 kb
Host smart-4cef68e2-8430-4015-83a8-19d760b3c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826477293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2826477293
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4177146300
Short name T300
Test name
Test status
Simulation time 157940683 ps
CPU time 0.73 seconds
Started Mar 05 01:01:05 PM PST 24
Finished Mar 05 01:01:06 PM PST 24
Peak memory 195024 kb
Host smart-881e310d-5c0e-412c-9043-053674b8a7df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177146300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4177146300
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.646094281
Short name T258
Test name
Test status
Simulation time 28769603727 ps
CPU time 109.65 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:03:07 PM PST 24
Peak memory 198248 kb
Host smart-a8bc2c92-79c4-41a3-94d3-9ed22ad7d17a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646094281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.646094281
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2957901910
Short name T161
Test name
Test status
Simulation time 33861133 ps
CPU time 0.56 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 194072 kb
Host smart-017bb87a-2780-4077-bab2-995d6bc40a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957901910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2957901910
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2749570319
Short name T455
Test name
Test status
Simulation time 35578738 ps
CPU time 0.71 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 195008 kb
Host smart-13ebcc41-13ca-4f3c-9d7b-ae96fb388cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749570319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2749570319
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.654605002
Short name T484
Test name
Test status
Simulation time 224133080 ps
CPU time 11.36 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:24 PM PST 24
Peak memory 197980 kb
Host smart-f90f47c7-2fb1-4283-87dc-05fff8405d5f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654605002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.654605002
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3989918560
Short name T668
Test name
Test status
Simulation time 109407021 ps
CPU time 0.69 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 194752 kb
Host smart-e71c4bee-ed4f-4c32-985c-45eaa28a030d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989918560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3989918560
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1635925987
Short name T173
Test name
Test status
Simulation time 166322600 ps
CPU time 1.38 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:12 PM PST 24
Peak memory 197088 kb
Host smart-bd91474c-bbc8-41bb-9a53-cb992c4f87b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635925987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1635925987
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1486423828
Short name T75
Test name
Test status
Simulation time 74913915 ps
CPU time 3.14 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 198176 kb
Host smart-baffdab7-e754-47b3-8cf0-6b309496b7e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486423828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1486423828
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.681891604
Short name T656
Test name
Test status
Simulation time 466317380 ps
CPU time 2.73 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:15 PM PST 24
Peak memory 197200 kb
Host smart-ac5263af-3e82-46e1-93d0-9737dbc325e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681891604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
681891604
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1406143073
Short name T199
Test name
Test status
Simulation time 135382754 ps
CPU time 1.35 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 197084 kb
Host smart-9ff9ea79-fa19-4cb9-8bf4-5a050efd0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406143073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1406143073
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3351110131
Short name T545
Test name
Test status
Simulation time 315698913 ps
CPU time 1.35 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 197088 kb
Host smart-31a8c5d5-0d77-40ea-b7e2-69ffd5f04dd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351110131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3351110131
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.949220777
Short name T334
Test name
Test status
Simulation time 159198560 ps
CPU time 3.81 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:20 PM PST 24
Peak memory 197968 kb
Host smart-44b109e4-71b3-4576-b16d-871f7c25a2b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949220777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.949220777
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4201985008
Short name T613
Test name
Test status
Simulation time 78272490 ps
CPU time 0.82 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 195268 kb
Host smart-b9c4325f-8472-4232-ab78-bce226bb32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201985008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4201985008
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1313337406
Short name T670
Test name
Test status
Simulation time 213019478 ps
CPU time 1.23 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 196508 kb
Host smart-180d2829-4377-4334-8e32-8642fdaed661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313337406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1313337406
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3661260435
Short name T351
Test name
Test status
Simulation time 16011575601 ps
CPU time 121.73 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:03:17 PM PST 24
Peak memory 198304 kb
Host smart-86c548ff-abb5-478b-a3c1-889dbfc10328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661260435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3661260435
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2152586870
Short name T374
Test name
Test status
Simulation time 84726947 ps
CPU time 0.63 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 193988 kb
Host smart-f032b0d7-8e9e-43be-9024-4655ba1e7d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152586870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2152586870
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.542527384
Short name T608
Test name
Test status
Simulation time 38274817 ps
CPU time 0.67 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 194908 kb
Host smart-ed267a0b-02f3-423f-b81a-3728a956c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542527384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.542527384
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3218863617
Short name T72
Test name
Test status
Simulation time 1904244204 ps
CPU time 26.16 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:44 PM PST 24
Peak memory 196444 kb
Host smart-cdb4c0f4-3f6d-41c5-b3f2-633d02f64727
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218863617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3218863617
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3058730494
Short name T516
Test name
Test status
Simulation time 68109848 ps
CPU time 0.95 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:15 PM PST 24
Peak memory 197140 kb
Host smart-c1cd76dd-3645-4366-88c7-f2c20e58a03a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058730494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3058730494
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2109339819
Short name T697
Test name
Test status
Simulation time 35079854 ps
CPU time 0.93 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 196612 kb
Host smart-7f7bbcbf-9221-484a-9c06-afd3ab1f423d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109339819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2109339819
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1187020119
Short name T152
Test name
Test status
Simulation time 87328313 ps
CPU time 3.65 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 198024 kb
Host smart-54f0a663-b7ef-4b85-b28f-630188240cdd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187020119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1187020119
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3881596990
Short name T200
Test name
Test status
Simulation time 135523790 ps
CPU time 2.31 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 195884 kb
Host smart-af61e7da-d159-412e-99d2-b500085124db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881596990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3881596990
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.85749947
Short name T346
Test name
Test status
Simulation time 55610582 ps
CPU time 0.77 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 196168 kb
Host smart-d13f1e3c-7ca8-4d62-ad61-e940d4b53bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85749947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.85749947
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2030376179
Short name T581
Test name
Test status
Simulation time 141591158 ps
CPU time 0.81 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 196064 kb
Host smart-6990bfde-4ad5-4198-bb9e-4d484d71d0e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030376179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2030376179
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3598938624
Short name T631
Test name
Test status
Simulation time 532684856 ps
CPU time 5.35 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 198092 kb
Host smart-09c16090-5e7f-446e-8f8e-02222856a2ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598938624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3598938624
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.233650764
Short name T17
Test name
Test status
Simulation time 392359348 ps
CPU time 0.99 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 196660 kb
Host smart-d1346d62-b8c0-4447-b31a-f11702d8a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233650764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.233650764
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1467443367
Short name T55
Test name
Test status
Simulation time 62426336 ps
CPU time 1.27 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:12 PM PST 24
Peak memory 197012 kb
Host smart-98944d40-bec7-47f4-9c20-460c3cd8ab2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467443367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1467443367
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1156539612
Short name T624
Test name
Test status
Simulation time 91224347553 ps
CPU time 188.51 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:04:22 PM PST 24
Peak memory 198292 kb
Host smart-34c7a8ee-9602-4819-9687-2cb76d4579b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156539612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1156539612
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3785441282
Short name T138
Test name
Test status
Simulation time 16206041 ps
CPU time 0.58 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:01:12 PM PST 24
Peak memory 194296 kb
Host smart-c71884a9-6aef-4bbf-85e2-16d90370c5a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785441282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3785441282
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2898723096
Short name T212
Test name
Test status
Simulation time 37201285 ps
CPU time 0.8 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 195368 kb
Host smart-456a24c6-2af1-46d9-9353-bec3f6f7931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898723096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2898723096
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2336897251
Short name T563
Test name
Test status
Simulation time 409169954 ps
CPU time 9.81 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 197304 kb
Host smart-3e09d8c7-bf74-441d-a3c0-e62652f3d9b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336897251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2336897251
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.407231274
Short name T673
Test name
Test status
Simulation time 413008691 ps
CPU time 0.71 seconds
Started Mar 05 01:01:18 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 195332 kb
Host smart-82713f13-9bb1-4ca8-8448-9df7865cd6c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407231274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.407231274
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1946312501
Short name T456
Test name
Test status
Simulation time 79380666 ps
CPU time 1.16 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 195936 kb
Host smart-948c8cdc-cd79-4c94-8ef2-6e208e1a2fc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946312501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1946312501
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3405282782
Short name T174
Test name
Test status
Simulation time 179633438 ps
CPU time 3.59 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:21 PM PST 24
Peak memory 198100 kb
Host smart-0c81b130-d9f7-4ee3-b167-291ea6a831d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405282782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3405282782
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2814866622
Short name T133
Test name
Test status
Simulation time 448090829 ps
CPU time 1.9 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 196612 kb
Host smart-d754e341-0669-4516-9c32-e7287ed02df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814866622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2814866622
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1903845860
Short name T403
Test name
Test status
Simulation time 98166696 ps
CPU time 1.04 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 196092 kb
Host smart-424ac0d5-92e3-452c-98ed-7bde2d234829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903845860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1903845860
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.266952022
Short name T391
Test name
Test status
Simulation time 121728870 ps
CPU time 0.63 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 194344 kb
Host smart-984194ff-b679-4d25-8a24-28919f0f86df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266952022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.266952022
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2725816480
Short name T422
Test name
Test status
Simulation time 119249020 ps
CPU time 2.84 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 198160 kb
Host smart-e2085d40-0f9b-4eb5-a0ba-f35aeb7d0f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725816480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2725816480
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.207100734
Short name T591
Test name
Test status
Simulation time 47182241 ps
CPU time 1.37 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:17 PM PST 24
Peak memory 197000 kb
Host smart-ce57e9b0-9f1f-446a-9ed1-934aca33c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207100734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.207100734
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1865192456
Short name T228
Test name
Test status
Simulation time 305292860 ps
CPU time 1.31 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 196852 kb
Host smart-699e38ea-66f2-4d49-8748-d1e0a23919c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865192456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1865192456
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2997238689
Short name T570
Test name
Test status
Simulation time 4698166195 ps
CPU time 117.4 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:03:10 PM PST 24
Peak memory 198312 kb
Host smart-a67bc2a3-4ab6-45b3-be0e-27ad868e54ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997238689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2997238689
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2503048901
Short name T312
Test name
Test status
Simulation time 13911068 ps
CPU time 0.56 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:13 PM PST 24
Peak memory 194076 kb
Host smart-afd14c46-f0fb-4d4d-8185-2849a2ab6e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503048901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2503048901
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3836548627
Short name T217
Test name
Test status
Simulation time 49357024 ps
CPU time 0.9 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:14 PM PST 24
Peak memory 197204 kb
Host smart-0c799a01-ffe6-413f-8638-a12772f85a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836548627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3836548627
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.12841430
Short name T39
Test name
Test status
Simulation time 1989281416 ps
CPU time 11.82 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 196432 kb
Host smart-e47e4639-d6e1-4a82-aa70-5de5b275feab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress
.12841430
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4000959512
Short name T534
Test name
Test status
Simulation time 117199912 ps
CPU time 0.88 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 195856 kb
Host smart-88e626e8-2758-4f17-a23e-d077ba150a3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000959512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4000959512
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2476314000
Short name T366
Test name
Test status
Simulation time 197442998 ps
CPU time 1.39 seconds
Started Mar 05 01:01:16 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 195876 kb
Host smart-67d6cf95-4236-42f8-b3cd-386d0230677a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476314000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2476314000
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.6533771
Short name T574
Test name
Test status
Simulation time 929188292 ps
CPU time 2.79 seconds
Started Mar 05 01:01:13 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 196368 kb
Host smart-3b051c2e-330c-4bdb-8820-8c4a87280591
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6533771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.gpio_intr_with_filter_rand_intr_event.6533771
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3992659311
Short name T167
Test name
Test status
Simulation time 566896170 ps
CPU time 2.79 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:20 PM PST 24
Peak memory 197028 kb
Host smart-39490231-8ac0-4e25-8aa6-1584f127558c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992659311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3992659311
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3961030870
Short name T327
Test name
Test status
Simulation time 14027076 ps
CPU time 0.7 seconds
Started Mar 05 01:01:18 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 194392 kb
Host smart-111ed467-3cf4-4616-b4d0-5d2c42c9b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961030870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3961030870
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2457437230
Short name T583
Test name
Test status
Simulation time 34844185 ps
CPU time 1.23 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 196984 kb
Host smart-20c32f9e-c5e2-48c3-92f0-93971690c0e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457437230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2457437230
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3598104459
Short name T490
Test name
Test status
Simulation time 1377672399 ps
CPU time 5.53 seconds
Started Mar 05 01:01:12 PM PST 24
Finished Mar 05 01:01:18 PM PST 24
Peak memory 198188 kb
Host smart-79afc93b-e362-4b23-af66-fe808543d3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598104459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3598104459
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2934667443
Short name T331
Test name
Test status
Simulation time 122454638 ps
CPU time 1.35 seconds
Started Mar 05 01:01:17 PM PST 24
Finished Mar 05 01:01:19 PM PST 24
Peak memory 197260 kb
Host smart-aae49761-8122-4bab-934a-4eac8f6b15b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934667443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2934667443
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3661040715
Short name T589
Test name
Test status
Simulation time 152198876 ps
CPU time 1.19 seconds
Started Mar 05 01:01:15 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 197124 kb
Host smart-dc6d961c-2fc4-40f8-b7a2-9137f4278d4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661040715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3661040715
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3896840459
Short name T3
Test name
Test status
Simulation time 2765749251 ps
CPU time 30.89 seconds
Started Mar 05 01:01:14 PM PST 24
Finished Mar 05 01:01:45 PM PST 24
Peak memory 198316 kb
Host smart-e41aa626-49ed-40f1-a94a-dfc2097b02ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896840459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3896840459
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1955115758
Short name T66
Test name
Test status
Simulation time 154523443192 ps
CPU time 1660.28 seconds
Started Mar 05 01:01:11 PM PST 24
Finished Mar 05 01:28:51 PM PST 24
Peak memory 198480 kb
Host smart-b8a4d2cd-86ab-4119-bdd2-16d8171d6621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1955115758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1955115758
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3352237733
Short name T552
Test name
Test status
Simulation time 37479280 ps
CPU time 0.56 seconds
Started Mar 05 01:01:22 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 194792 kb
Host smart-2df97382-d611-4f35-9592-4782ae1c1e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352237733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3352237733
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2127042503
Short name T143
Test name
Test status
Simulation time 17663428 ps
CPU time 0.7 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:22 PM PST 24
Peak memory 194708 kb
Host smart-03d638c3-aa7b-42c2-a32f-4a11de3d1737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127042503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2127042503
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1182792664
Short name T609
Test name
Test status
Simulation time 1922568970 ps
CPU time 11.76 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:33 PM PST 24
Peak memory 197048 kb
Host smart-459e9638-96df-4ff7-a1ad-cfac10fd2b45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182792664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1182792664
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1687000163
Short name T703
Test name
Test status
Simulation time 71727912 ps
CPU time 0.96 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 197992 kb
Host smart-500ba497-e787-4004-9dfc-decd0e4427da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687000163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1687000163
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1483200940
Short name T364
Test name
Test status
Simulation time 50302153 ps
CPU time 1.29 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 197304 kb
Host smart-77c40b30-f76e-4887-bd73-f70b6636427e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483200940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1483200940
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.20902329
Short name T627
Test name
Test status
Simulation time 90193734 ps
CPU time 3.64 seconds
Started Mar 05 01:01:25 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 198248 kb
Host smart-ee783e86-dd9b-4cc6-a03a-c446b43f8106
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.gpio_intr_with_filter_rand_intr_event.20902329
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.498681649
Short name T25
Test name
Test status
Simulation time 127413057 ps
CPU time 2.71 seconds
Started Mar 05 01:01:22 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 197348 kb
Host smart-7f4ddac9-b76e-4bcc-b281-e981bf030213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498681649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
498681649
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3523553271
Short name T660
Test name
Test status
Simulation time 113540527 ps
CPU time 1.08 seconds
Started Mar 05 01:01:33 PM PST 24
Finished Mar 05 01:01:34 PM PST 24
Peak memory 196136 kb
Host smart-426dab90-f6e9-4c54-b1d2-29a54aaa99b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523553271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3523553271
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1054474629
Short name T603
Test name
Test status
Simulation time 130924303 ps
CPU time 1.23 seconds
Started Mar 05 01:01:22 PM PST 24
Finished Mar 05 01:01:24 PM PST 24
Peak memory 195960 kb
Host smart-166901a0-a0b0-4bfb-834e-3dfa7a60d860
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054474629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1054474629
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.524023240
Short name T554
Test name
Test status
Simulation time 188599531 ps
CPU time 1.61 seconds
Started Mar 05 01:01:20 PM PST 24
Finished Mar 05 01:01:22 PM PST 24
Peak memory 198100 kb
Host smart-c24d0e37-0339-4a3e-8667-16b7564ca851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524023240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.524023240
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.77621616
Short name T415
Test name
Test status
Simulation time 75693460 ps
CPU time 0.73 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 195252 kb
Host smart-32c70f9c-6e52-4e80-a7db-4576b52fd135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77621616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.77621616
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1407077410
Short name T642
Test name
Test status
Simulation time 264847848 ps
CPU time 1.53 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 197856 kb
Host smart-d090bc55-9b11-4bbb-88b8-bf4502fac2a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407077410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1407077410
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2978118332
Short name T654
Test name
Test status
Simulation time 67662217823 ps
CPU time 178.66 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:04:23 PM PST 24
Peak memory 198128 kb
Host smart-5728778c-b0b6-49c9-b1ca-634a82f4b7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978118332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2978118332
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1113715960
Short name T620
Test name
Test status
Simulation time 31597598 ps
CPU time 0.55 seconds
Started Mar 05 01:01:25 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 194084 kb
Host smart-518d2c94-1ff1-45b1-aea9-074c97f9f79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113715960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1113715960
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3108491117
Short name T442
Test name
Test status
Simulation time 35593337 ps
CPU time 0.7 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 194860 kb
Host smart-3fedbe45-7cec-44e6-bf31-2815a12c2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108491117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3108491117
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3611206395
Short name T539
Test name
Test status
Simulation time 1605482544 ps
CPU time 20.64 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:42 PM PST 24
Peak memory 197020 kb
Host smart-6bc8b7d6-e51b-44da-b88f-25d76fd6994a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611206395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3611206395
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.324171755
Short name T337
Test name
Test status
Simulation time 29623433 ps
CPU time 0.62 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 194472 kb
Host smart-f4b28115-0764-4503-936d-d365da023e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324171755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.324171755
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3589224885
Short name T651
Test name
Test status
Simulation time 74041552 ps
CPU time 0.91 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 197536 kb
Host smart-3192077c-47d0-49f5-8f6f-9fc838012f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589224885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3589224885
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2653589374
Short name T162
Test name
Test status
Simulation time 54463654 ps
CPU time 2.09 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:01:29 PM PST 24
Peak memory 198148 kb
Host smart-35d32a7d-d3ff-450a-bed8-05d713aaecb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653589374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2653589374
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4231627203
Short name T53
Test name
Test status
Simulation time 331301491 ps
CPU time 2.63 seconds
Started Mar 05 01:01:23 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 195888 kb
Host smart-f07e739f-892a-47bb-975a-752fa83ff864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231627203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4231627203
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.327682616
Short name T214
Test name
Test status
Simulation time 59799613 ps
CPU time 1.11 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 195980 kb
Host smart-d05dc40c-d123-4589-91fa-1c5a3f885c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327682616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.327682616
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3944213456
Short name T356
Test name
Test status
Simulation time 70913890 ps
CPU time 1.32 seconds
Started Mar 05 01:01:23 PM PST 24
Finished Mar 05 01:01:24 PM PST 24
Peak memory 198240 kb
Host smart-17a21d15-ce47-475f-ae69-374a716a3d04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944213456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3944213456
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3308874382
Short name T8
Test name
Test status
Simulation time 466009735 ps
CPU time 3.48 seconds
Started Mar 05 01:01:22 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 198096 kb
Host smart-80492c42-6e17-4d5b-823b-921677231215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308874382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3308874382
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.215631226
Short name T353
Test name
Test status
Simulation time 106563996 ps
CPU time 1.34 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 196792 kb
Host smart-feeede3f-a83c-4ca0-83b5-9073c471161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215631226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.215631226
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4059792816
Short name T250
Test name
Test status
Simulation time 174465608 ps
CPU time 1.43 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 196784 kb
Host smart-03d4a662-1654-492c-ba16-1b96a8a2636a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059792816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4059792816
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1092057813
Short name T309
Test name
Test status
Simulation time 47225978959 ps
CPU time 161.14 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:04:02 PM PST 24
Peak memory 198312 kb
Host smart-060e09ae-91da-4354-9fe6-79b19a6e129f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092057813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1092057813
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4195987045
Short name T509
Test name
Test status
Simulation time 14951402 ps
CPU time 0.59 seconds
Started Mar 05 01:01:25 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 194208 kb
Host smart-1b18586e-f0c5-43d9-9e87-491577795028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195987045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4195987045
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.765826729
Short name T45
Test name
Test status
Simulation time 27430071 ps
CPU time 0.77 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 195168 kb
Host smart-aba72dd2-106d-438d-a429-c31603050309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765826729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.765826729
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.412597711
Short name T491
Test name
Test status
Simulation time 1251602827 ps
CPU time 11.17 seconds
Started Mar 05 01:01:25 PM PST 24
Finished Mar 05 01:01:36 PM PST 24
Peak memory 198144 kb
Host smart-52d35f86-c5cb-446d-aafb-089e9c77ab4e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412597711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.412597711
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.490809005
Short name T573
Test name
Test status
Simulation time 40723857 ps
CPU time 0.77 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 195448 kb
Host smart-1068aa86-fd87-4f8b-89af-880cf0cddcdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490809005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.490809005
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2721931198
Short name T572
Test name
Test status
Simulation time 172159908 ps
CPU time 1.29 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 196096 kb
Host smart-7f10bca2-d42c-448c-ba95-a4c043c0e99d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721931198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2721931198
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1690679608
Short name T519
Test name
Test status
Simulation time 49696934 ps
CPU time 2.07 seconds
Started Mar 05 01:01:23 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 198224 kb
Host smart-b48e36d8-2331-4321-b17e-56b2ac7c80bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690679608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1690679608
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.246793212
Short name T134
Test name
Test status
Simulation time 81592977 ps
CPU time 1.31 seconds
Started Mar 05 01:01:20 PM PST 24
Finished Mar 05 01:01:22 PM PST 24
Peak memory 196264 kb
Host smart-3f7b4236-50bf-41d5-a347-38f11932e75b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246793212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
246793212
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4278293065
Short name T482
Test name
Test status
Simulation time 54451058 ps
CPU time 1.2 seconds
Started Mar 05 01:01:22 PM PST 24
Finished Mar 05 01:01:23 PM PST 24
Peak memory 197080 kb
Host smart-4afd531f-5c2a-435c-8397-f8d464de7369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278293065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4278293065
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1103758349
Short name T665
Test name
Test status
Simulation time 52300207 ps
CPU time 0.71 seconds
Started Mar 05 01:01:21 PM PST 24
Finished Mar 05 01:01:22 PM PST 24
Peak memory 195516 kb
Host smart-96460919-8824-422a-888f-5f11af8e0998
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103758349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1103758349
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2135529518
Short name T260
Test name
Test status
Simulation time 174657196 ps
CPU time 3.29 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:29 PM PST 24
Peak memory 198072 kb
Host smart-ab341768-158d-4209-b307-e94fc4fa7646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135529518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2135529518
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1993981481
Short name T299
Test name
Test status
Simulation time 142142900 ps
CPU time 0.88 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 196372 kb
Host smart-92ade75b-9913-42f6-9ede-5162af016e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993981481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1993981481
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1829758020
Short name T230
Test name
Test status
Simulation time 74146749 ps
CPU time 1.22 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:25 PM PST 24
Peak memory 198084 kb
Host smart-2c493372-9f4f-438e-b329-053719485f02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829758020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1829758020
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3815500359
Short name T158
Test name
Test status
Simulation time 5601835469 ps
CPU time 83.68 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:02:48 PM PST 24
Peak memory 198320 kb
Host smart-85b7c7c7-903d-4a2f-8d42-11477475c276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815500359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3815500359
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.354849469
Short name T465
Test name
Test status
Simulation time 14004557 ps
CPU time 0.57 seconds
Started Mar 05 01:01:30 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 194912 kb
Host smart-71a2777c-10dd-4a58-8e5e-69107c6414a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354849469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.354849469
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.296123919
Short name T541
Test name
Test status
Simulation time 29146998 ps
CPU time 0.87 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 195960 kb
Host smart-dea8bb72-d263-4b3b-a613-731b4127978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296123919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.296123919
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1028537054
Short name T319
Test name
Test status
Simulation time 486527894 ps
CPU time 6.09 seconds
Started Mar 05 01:01:29 PM PST 24
Finished Mar 05 01:01:35 PM PST 24
Peak memory 195548 kb
Host smart-12ee2740-46b5-457b-8f85-f8ce26f14fe6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028537054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1028537054
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2901202768
Short name T360
Test name
Test status
Simulation time 51051463 ps
CPU time 0.83 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:27 PM PST 24
Peak memory 195912 kb
Host smart-1541f188-7876-4d62-82e5-65044c1e5c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901202768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2901202768
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.698253573
Short name T27
Test name
Test status
Simulation time 23649203 ps
CPU time 0.74 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 195080 kb
Host smart-03352e55-8f3e-4c53-a7a9-0972bd53527a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698253573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.698253573
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2797606687
Short name T132
Test name
Test status
Simulation time 313979350 ps
CPU time 2.39 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 198140 kb
Host smart-1589faac-fb35-4da6-bce3-6d14acb1f761
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797606687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2797606687
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3936402856
Short name T277
Test name
Test status
Simulation time 129842819 ps
CPU time 3.55 seconds
Started Mar 05 01:01:40 PM PST 24
Finished Mar 05 01:01:44 PM PST 24
Peak memory 197300 kb
Host smart-c3fb8912-df43-4121-86bb-297c37c21fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936402856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3936402856
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.305976835
Short name T445
Test name
Test status
Simulation time 105430931 ps
CPU time 1.12 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 196172 kb
Host smart-1c796e12-69c9-42de-aaf6-9e098c6d3d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305976835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.305976835
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2080839863
Short name T434
Test name
Test status
Simulation time 55905176 ps
CPU time 1.2 seconds
Started Mar 05 01:01:24 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 197088 kb
Host smart-cfa1e65d-f60e-4977-9be3-bf155b7672cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080839863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2080839863
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3140321236
Short name T436
Test name
Test status
Simulation time 354949454 ps
CPU time 4.07 seconds
Started Mar 05 01:01:40 PM PST 24
Finished Mar 05 01:01:44 PM PST 24
Peak memory 198112 kb
Host smart-56330bd1-4d10-4007-a752-e7b8e7178de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140321236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3140321236
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.577856592
Short name T22
Test name
Test status
Simulation time 49182737 ps
CPU time 1.31 seconds
Started Mar 05 01:01:26 PM PST 24
Finished Mar 05 01:01:28 PM PST 24
Peak memory 196940 kb
Host smart-417ac7d0-97d7-4f4f-81b5-8f96a0cafaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577856592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.577856592
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.245158272
Short name T440
Test name
Test status
Simulation time 37936411 ps
CPU time 1.12 seconds
Started Mar 05 01:01:25 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 195932 kb
Host smart-e8534204-f614-4072-ac4e-416ef1cde458
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245158272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.245158272
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.780424007
Short name T506
Test name
Test status
Simulation time 6730737793 ps
CPU time 173.45 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:04:22 PM PST 24
Peak memory 198324 kb
Host smart-94b182d8-6a58-474b-bca2-c49d6acfd056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780424007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.780424007
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2790258869
Short name T306
Test name
Test status
Simulation time 36587333 ps
CPU time 0.59 seconds
Started Mar 05 01:01:30 PM PST 24
Finished Mar 05 01:01:31 PM PST 24
Peak memory 194848 kb
Host smart-9bf6d16a-00e3-45d0-908f-4309c901f39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790258869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2790258869
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2191100440
Short name T535
Test name
Test status
Simulation time 39508086 ps
CPU time 0.95 seconds
Started Mar 05 01:01:29 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 196824 kb
Host smart-310fe3dd-dbb8-4c78-a051-caaa0ad02047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191100440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2191100440
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3176451283
Short name T129
Test name
Test status
Simulation time 696643018 ps
CPU time 20.02 seconds
Started Mar 05 01:01:29 PM PST 24
Finished Mar 05 01:01:49 PM PST 24
Peak memory 196736 kb
Host smart-57240a05-4706-423c-9979-3369d97f0483
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176451283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3176451283
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2341430642
Short name T375
Test name
Test status
Simulation time 373124254 ps
CPU time 1.12 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:01:29 PM PST 24
Peak memory 198176 kb
Host smart-60f75a95-1141-4515-8031-01fc231cdd18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341430642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2341430642
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3670378013
Short name T684
Test name
Test status
Simulation time 76176373 ps
CPU time 1.11 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:01:29 PM PST 24
Peak memory 196196 kb
Host smart-5bd45440-e709-457d-a149-ae666f424e0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670378013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3670378013
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.23637077
Short name T265
Test name
Test status
Simulation time 535579014 ps
CPU time 1.86 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 198016 kb
Host smart-c122eab4-88e6-406f-8b54-46c8a880128a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23637077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.gpio_intr_with_filter_rand_intr_event.23637077
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3038985932
Short name T512
Test name
Test status
Simulation time 415749697 ps
CPU time 2.52 seconds
Started Mar 05 01:01:29 PM PST 24
Finished Mar 05 01:01:32 PM PST 24
Peak memory 197168 kb
Host smart-d45368b9-c2f9-456d-a8b1-3e31d4b64eb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038985932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3038985932
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1756000025
Short name T702
Test name
Test status
Simulation time 47906394 ps
CPU time 1.07 seconds
Started Mar 05 01:01:31 PM PST 24
Finished Mar 05 01:01:32 PM PST 24
Peak memory 196080 kb
Host smart-929c36f0-e860-4a41-bc7b-8607f7578817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756000025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1756000025
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2190267740
Short name T657
Test name
Test status
Simulation time 20529735 ps
CPU time 0.88 seconds
Started Mar 05 01:01:29 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 196728 kb
Host smart-a5873525-4a0f-4ca3-b1a7-ca1b69faee48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190267740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2190267740
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.833275886
Short name T105
Test name
Test status
Simulation time 124892383 ps
CPU time 2.07 seconds
Started Mar 05 01:01:28 PM PST 24
Finished Mar 05 01:01:30 PM PST 24
Peak memory 198108 kb
Host smart-17f59b65-88a6-4007-86e5-03714c317b19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833275886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.833275886
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3878898395
Short name T120
Test name
Test status
Simulation time 58211890 ps
CPU time 0.99 seconds
Started Mar 05 01:01:31 PM PST 24
Finished Mar 05 01:01:32 PM PST 24
Peak memory 195872 kb
Host smart-0cb1f593-950f-41c3-a9cc-aa6b160adf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878898395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3878898395
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3594916841
Short name T495
Test name
Test status
Simulation time 220670065 ps
CPU time 1.08 seconds
Started Mar 05 01:01:30 PM PST 24
Finished Mar 05 01:01:31 PM PST 24
Peak memory 196268 kb
Host smart-73a15755-46cc-45ae-90dd-e0aef6642e64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594916841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3594916841
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1642237978
Short name T559
Test name
Test status
Simulation time 8793831782 ps
CPU time 114.02 seconds
Started Mar 05 01:01:27 PM PST 24
Finished Mar 05 01:03:21 PM PST 24
Peak memory 198300 kb
Host smart-66fe8e31-f0fc-43be-bab6-66645ce031c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642237978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1642237978
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.740127987
Short name T380
Test name
Test status
Simulation time 12647111 ps
CPU time 0.58 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:03 PM PST 24
Peak memory 194716 kb
Host smart-3739e92b-385d-4f93-aa62-d4b2d686e37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740127987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.740127987
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3067925927
Short name T638
Test name
Test status
Simulation time 38163920 ps
CPU time 0.87 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:05 PM PST 24
Peak memory 196512 kb
Host smart-8f96f6d3-30a0-4530-9970-b47b1493fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067925927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3067925927
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1826969705
Short name T70
Test name
Test status
Simulation time 957505094 ps
CPU time 8.38 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 196956 kb
Host smart-377ade3c-09cc-48a8-92a5-7eaaa37d691a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826969705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1826969705
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.463285061
Short name T579
Test name
Test status
Simulation time 412761655 ps
CPU time 0.83 seconds
Started Mar 05 12:59:08 PM PST 24
Finished Mar 05 12:59:09 PM PST 24
Peak memory 195828 kb
Host smart-bfe0aa2a-5ade-4568-b7b5-2a528eb17e6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463285061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.463285061
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1314151737
Short name T650
Test name
Test status
Simulation time 597808327 ps
CPU time 1.32 seconds
Started Mar 05 12:59:01 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 198280 kb
Host smart-025750dc-cef0-4957-8e47-5398a6277a7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314151737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1314151737
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1511354040
Short name T145
Test name
Test status
Simulation time 188518113 ps
CPU time 3.74 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:07 PM PST 24
Peak memory 198200 kb
Host smart-77258d5e-0f02-430a-81b8-6bf909c06a04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511354040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1511354040
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3077245612
Short name T634
Test name
Test status
Simulation time 115476008 ps
CPU time 3.27 seconds
Started Mar 05 12:58:58 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 197216 kb
Host smart-f055f571-85b3-44f8-83e0-6d875359fa57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077245612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3077245612
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2744879372
Short name T441
Test name
Test status
Simulation time 100990527 ps
CPU time 0.75 seconds
Started Mar 05 12:59:02 PM PST 24
Finished Mar 05 12:59:03 PM PST 24
Peak memory 195528 kb
Host smart-2e133af8-f5b5-43c5-bdf5-1fed583c7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744879372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2744879372
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2298923339
Short name T124
Test name
Test status
Simulation time 26689339 ps
CPU time 0.76 seconds
Started Mar 05 12:59:08 PM PST 24
Finished Mar 05 12:59:09 PM PST 24
Peak memory 195544 kb
Host smart-27f4e7ba-d037-4d60-9c9e-a2d418b22348
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298923339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2298923339
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2927624242
Short name T488
Test name
Test status
Simulation time 206304757 ps
CPU time 3.49 seconds
Started Mar 05 12:59:00 PM PST 24
Finished Mar 05 12:59:04 PM PST 24
Peak memory 198132 kb
Host smart-e259def6-4b06-4dc3-9406-7ce060c0d417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927624242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2927624242
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.372608284
Short name T527
Test name
Test status
Simulation time 41705081 ps
CPU time 1.19 seconds
Started Mar 05 12:59:04 PM PST 24
Finished Mar 05 12:59:05 PM PST 24
Peak memory 196896 kb
Host smart-28ef62d0-3bdb-4007-95eb-9a7aa55b8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372608284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.372608284
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1849571850
Short name T226
Test name
Test status
Simulation time 282827984 ps
CPU time 1.22 seconds
Started Mar 05 12:59:03 PM PST 24
Finished Mar 05 12:59:05 PM PST 24
Peak memory 196880 kb
Host smart-4f589f29-7a94-4586-aae9-4d9ec843fb5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849571850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1849571850
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.758097381
Short name T683
Test name
Test status
Simulation time 56987190728 ps
CPU time 129.03 seconds
Started Mar 05 12:59:07 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 198356 kb
Host smart-d3042f38-fadd-4a7c-9a81-c8a56a402824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758097381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.758097381
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2591549194
Short name T562
Test name
Test status
Simulation time 13633358 ps
CPU time 0.56 seconds
Started Mar 05 12:59:08 PM PST 24
Finished Mar 05 12:59:09 PM PST 24
Peak memory 194088 kb
Host smart-f5c21164-44c7-4aa8-8313-89768889fda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591549194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2591549194
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.628204141
Short name T478
Test name
Test status
Simulation time 148995335 ps
CPU time 0.89 seconds
Started Mar 05 12:59:11 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 196436 kb
Host smart-8d19123c-c4e3-403b-a9bd-470fa66661a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628204141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.628204141
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.750013482
Short name T496
Test name
Test status
Simulation time 499926094 ps
CPU time 26.17 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:37 PM PST 24
Peak memory 195644 kb
Host smart-b0d1c39c-7015-4849-9df9-67af57d49f93
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750013482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.750013482
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1714562089
Short name T407
Test name
Test status
Simulation time 59799841 ps
CPU time 0.99 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:11 PM PST 24
Peak memory 197948 kb
Host smart-0a6bfd8b-f224-4638-8d92-4226f74b1144
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714562089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1714562089
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2145328780
Short name T209
Test name
Test status
Simulation time 239136064 ps
CPU time 1.15 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 196248 kb
Host smart-ed3568d3-2f57-4cc7-80a2-51246230fb83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145328780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2145328780
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1034309551
Short name T686
Test name
Test status
Simulation time 268287389 ps
CPU time 2.74 seconds
Started Mar 05 12:59:11 PM PST 24
Finished Mar 05 12:59:14 PM PST 24
Peak memory 198148 kb
Host smart-e82d71e1-42c4-4764-921e-2a57110b6f19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034309551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1034309551
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3409688400
Short name T215
Test name
Test status
Simulation time 922485231 ps
CPU time 3.34 seconds
Started Mar 05 12:59:12 PM PST 24
Finished Mar 05 12:59:15 PM PST 24
Peak memory 197244 kb
Host smart-6377dd67-ebb6-47ac-b4a5-8afa9f569a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409688400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3409688400
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.892884197
Short name T387
Test name
Test status
Simulation time 231103481 ps
CPU time 1.31 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 198196 kb
Host smart-6e08b040-9a52-4987-b895-842b0684016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892884197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.892884197
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.652214426
Short name T385
Test name
Test status
Simulation time 33634889 ps
CPU time 1.15 seconds
Started Mar 05 12:59:09 PM PST 24
Finished Mar 05 12:59:10 PM PST 24
Peak memory 197024 kb
Host smart-54075393-7232-4135-a7e7-696be836c6d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652214426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.652214426
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2652473759
Short name T621
Test name
Test status
Simulation time 70276416 ps
CPU time 3.29 seconds
Started Mar 05 12:59:13 PM PST 24
Finished Mar 05 12:59:16 PM PST 24
Peak memory 197988 kb
Host smart-5376cb91-323f-4f3b-8361-8ca6d6a15c54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652473759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2652473759
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1445473024
Short name T302
Test name
Test status
Simulation time 158105966 ps
CPU time 0.97 seconds
Started Mar 05 12:59:12 PM PST 24
Finished Mar 05 12:59:13 PM PST 24
Peak memory 195632 kb
Host smart-a2b43023-7778-4142-ba70-c52b61cc60b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445473024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1445473024
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1128763847
Short name T540
Test name
Test status
Simulation time 125686025 ps
CPU time 1.23 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:11 PM PST 24
Peak memory 196668 kb
Host smart-ee18c772-3d70-402d-a017-055c4d163636
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128763847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1128763847
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2165558736
Short name T229
Test name
Test status
Simulation time 15232641256 ps
CPU time 228.59 seconds
Started Mar 05 12:59:13 PM PST 24
Finished Mar 05 01:03:02 PM PST 24
Peak memory 198192 kb
Host smart-8a0f48fa-1638-47c6-a638-c5eebf2a639e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165558736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2165558736
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3109831243
Short name T206
Test name
Test status
Simulation time 20568240 ps
CPU time 0.61 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 194308 kb
Host smart-b347db37-f1cf-4512-aa1c-c2c05054b5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109831243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3109831243
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2238509066
Short name T141
Test name
Test status
Simulation time 88033526 ps
CPU time 0.82 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:11 PM PST 24
Peak memory 195464 kb
Host smart-1540d857-096d-4c2e-bb86-ff49c264d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238509066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2238509066
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2768584459
Short name T587
Test name
Test status
Simulation time 606387578 ps
CPU time 8.03 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:18 PM PST 24
Peak memory 195688 kb
Host smart-8e5a284a-c57b-4cd9-98d2-72715a374e40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768584459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2768584459
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1806844867
Short name T320
Test name
Test status
Simulation time 72625716 ps
CPU time 0.94 seconds
Started Mar 05 12:59:09 PM PST 24
Finished Mar 05 12:59:10 PM PST 24
Peak memory 197396 kb
Host smart-5aef9c82-fd7b-49a9-9dc3-560bb9fa3397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806844867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1806844867
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1103255184
Short name T566
Test name
Test status
Simulation time 34235082 ps
CPU time 0.7 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 12:59:11 PM PST 24
Peak memory 194484 kb
Host smart-ece1e1eb-8b24-4794-9726-1961df41ca84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103255184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1103255184
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3028535118
Short name T264
Test name
Test status
Simulation time 55184990 ps
CPU time 2.2 seconds
Started Mar 05 12:59:09 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 198040 kb
Host smart-c43aaa21-1eb4-4b51-a837-2b31025a0211
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028535118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3028535118
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3079384848
Short name T128
Test name
Test status
Simulation time 208400447 ps
CPU time 2.11 seconds
Started Mar 05 12:59:12 PM PST 24
Finished Mar 05 12:59:14 PM PST 24
Peak memory 196820 kb
Host smart-25030d7a-27dc-4b3f-ae42-3cabdfa3252f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079384848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3079384848
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2619365502
Short name T251
Test name
Test status
Simulation time 69961612 ps
CPU time 0.73 seconds
Started Mar 05 12:59:12 PM PST 24
Finished Mar 05 12:59:13 PM PST 24
Peak memory 195516 kb
Host smart-78c54ce4-3f23-48ca-9b13-e292997e5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619365502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2619365502
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3311652691
Short name T198
Test name
Test status
Simulation time 29294115 ps
CPU time 0.78 seconds
Started Mar 05 12:59:14 PM PST 24
Finished Mar 05 12:59:15 PM PST 24
Peak memory 195488 kb
Host smart-e3ec9cc6-66fa-49d5-aaa5-c96b2c03aba9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311652691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3311652691
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3046413490
Short name T507
Test name
Test status
Simulation time 107412108 ps
CPU time 4.82 seconds
Started Mar 05 12:59:14 PM PST 24
Finished Mar 05 12:59:19 PM PST 24
Peak memory 198152 kb
Host smart-bd11bbff-e9e1-436f-a30a-2b5a67623cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046413490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3046413490
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1433220606
Short name T461
Test name
Test status
Simulation time 58311477 ps
CPU time 0.92 seconds
Started Mar 05 12:59:14 PM PST 24
Finished Mar 05 12:59:15 PM PST 24
Peak memory 195588 kb
Host smart-94a7dcd0-fc2d-40b0-a58c-175f47581a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433220606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1433220606
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.724898579
Short name T171
Test name
Test status
Simulation time 35938498 ps
CPU time 1.08 seconds
Started Mar 05 12:59:11 PM PST 24
Finished Mar 05 12:59:12 PM PST 24
Peak memory 195836 kb
Host smart-10ef552f-2b90-48b4-87e8-f7f048c938ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724898579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.724898579
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.112557580
Short name T256
Test name
Test status
Simulation time 19393008609 ps
CPU time 116.65 seconds
Started Mar 05 12:59:10 PM PST 24
Finished Mar 05 01:01:07 PM PST 24
Peak memory 198276 kb
Host smart-bcceb530-f303-43f9-a2fe-44fb93508b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112557580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.112557580
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2665705650
Short name T263
Test name
Test status
Simulation time 35785726 ps
CPU time 0.57 seconds
Started Mar 05 12:59:18 PM PST 24
Finished Mar 05 12:59:19 PM PST 24
Peak memory 194988 kb
Host smart-1a1dd50a-1785-4d20-8921-069ebcac088a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665705650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2665705650
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2275983100
Short name T580
Test name
Test status
Simulation time 14674912 ps
CPU time 0.61 seconds
Started Mar 05 12:59:22 PM PST 24
Finished Mar 05 12:59:23 PM PST 24
Peak memory 194864 kb
Host smart-949d53ec-613d-4b99-9fc0-34ab0e16b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275983100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2275983100
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3378025841
Short name T127
Test name
Test status
Simulation time 10636999878 ps
CPU time 26.35 seconds
Started Mar 05 12:59:24 PM PST 24
Finished Mar 05 12:59:51 PM PST 24
Peak memory 196824 kb
Host smart-73f0bc73-63d9-4ae7-8109-c9d1a856fdbc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378025841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3378025841
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.388127316
Short name T16
Test name
Test status
Simulation time 26859145 ps
CPU time 0.67 seconds
Started Mar 05 12:59:21 PM PST 24
Finished Mar 05 12:59:22 PM PST 24
Peak memory 194656 kb
Host smart-621c5797-184d-4d7d-a889-1e1176184e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388127316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.388127316
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2702469003
Short name T136
Test name
Test status
Simulation time 136730843 ps
CPU time 1.14 seconds
Started Mar 05 12:59:21 PM PST 24
Finished Mar 05 12:59:22 PM PST 24
Peak memory 196336 kb
Host smart-f6f66fe0-78ac-442e-bf3d-ffe5e4c28404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702469003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2702469003
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1653079228
Short name T321
Test name
Test status
Simulation time 74317209 ps
CPU time 2.91 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:23 PM PST 24
Peak memory 198260 kb
Host smart-a3cdeeac-79a9-44d8-8835-b6430732b6a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653079228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1653079228
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.770946728
Short name T698
Test name
Test status
Simulation time 39192147 ps
CPU time 1.35 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:22 PM PST 24
Peak memory 196168 kb
Host smart-8531ba0a-1eab-496e-ab4c-80fead699e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770946728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.770946728
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1472689980
Short name T373
Test name
Test status
Simulation time 66859026 ps
CPU time 0.86 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:22 PM PST 24
Peak memory 196700 kb
Host smart-37571f41-62db-4d14-9475-07e8758d6ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472689980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1472689980
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3661876172
Short name T191
Test name
Test status
Simulation time 23676855 ps
CPU time 0.87 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 196496 kb
Host smart-81fcfed5-b2f9-4dcb-a038-88e3e66c44f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661876172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3661876172
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1410932311
Short name T10
Test name
Test status
Simulation time 882487740 ps
CPU time 2.98 seconds
Started Mar 05 12:59:19 PM PST 24
Finished Mar 05 12:59:23 PM PST 24
Peak memory 198072 kb
Host smart-85bf8165-03a3-4ea3-803c-71c554f76fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410932311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1410932311
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2767607825
Short name T682
Test name
Test status
Simulation time 39977229 ps
CPU time 0.95 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 196416 kb
Host smart-c0e23263-6c92-4cd9-a9a9-36b222b1e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767607825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2767607825
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2396783306
Short name T305
Test name
Test status
Simulation time 77658777 ps
CPU time 1.33 seconds
Started Mar 05 12:59:21 PM PST 24
Finished Mar 05 12:59:23 PM PST 24
Peak memory 195644 kb
Host smart-5fb9756e-9621-4383-bc7c-3ee2e9d6f04e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396783306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2396783306
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3783728577
Short name T4
Test name
Test status
Simulation time 72240273831 ps
CPU time 198.83 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 01:02:40 PM PST 24
Peak memory 198272 kb
Host smart-2ccf83a7-5c03-41a7-b12a-07996a4b7c18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783728577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3783728577
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.780037656
Short name T68
Test name
Test status
Simulation time 18301879166 ps
CPU time 258.55 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 01:03:39 PM PST 24
Peak memory 198500 kb
Host smart-6605f9f1-3dd7-43ed-9644-88a58f2f0b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=780037656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.780037656
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1241593218
Short name T149
Test name
Test status
Simulation time 24180564 ps
CPU time 0.55 seconds
Started Mar 05 12:59:32 PM PST 24
Finished Mar 05 12:59:33 PM PST 24
Peak memory 193504 kb
Host smart-1d298971-e115-4806-8f20-d281265285c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241593218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1241593218
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.161070736
Short name T324
Test name
Test status
Simulation time 25045509 ps
CPU time 0.67 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 194792 kb
Host smart-82c3f026-9767-40dd-a32c-8a6788b10bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161070736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.161070736
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3206803119
Short name T341
Test name
Test status
Simulation time 311380142 ps
CPU time 16.32 seconds
Started Mar 05 12:59:33 PM PST 24
Finished Mar 05 12:59:49 PM PST 24
Peak memory 195656 kb
Host smart-7f011f69-c601-4230-a002-037d5eaf3195
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206803119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3206803119
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.439120756
Short name T126
Test name
Test status
Simulation time 312628675 ps
CPU time 1.41 seconds
Started Mar 05 12:59:19 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 197188 kb
Host smart-a2fdaa09-5913-4f9f-aa8e-ed9d8968113c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439120756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.439120756
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2778719035
Short name T243
Test name
Test status
Simulation time 377749166 ps
CPU time 2.22 seconds
Started Mar 05 12:59:23 PM PST 24
Finished Mar 05 12:59:26 PM PST 24
Peak memory 196836 kb
Host smart-2549c8db-8ef1-42a6-aa36-b5dcba41143b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778719035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2778719035
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1000964929
Short name T393
Test name
Test status
Simulation time 33062823 ps
CPU time 1.07 seconds
Started Mar 05 12:59:20 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 197216 kb
Host smart-c3ee1f32-fdde-47f1-97b1-d37eacdff323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000964929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1000964929
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3095435808
Short name T637
Test name
Test status
Simulation time 68807677 ps
CPU time 0.65 seconds
Started Mar 05 12:59:18 PM PST 24
Finished Mar 05 12:59:19 PM PST 24
Peak memory 194384 kb
Host smart-07989527-ce10-4245-86b9-bf09d106ebd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095435808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3095435808
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1220566284
Short name T116
Test name
Test status
Simulation time 1234578448 ps
CPU time 5.47 seconds
Started Mar 05 12:59:30 PM PST 24
Finished Mar 05 12:59:36 PM PST 24
Peak memory 197980 kb
Host smart-19b59cc5-40dc-4e2a-a40b-5abba627298e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220566284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1220566284
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.865136016
Short name T406
Test name
Test status
Simulation time 385909331 ps
CPU time 1.29 seconds
Started Mar 05 12:59:19 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 196964 kb
Host smart-0ac3e9f1-d102-487f-8075-2b38b05e4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865136016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.865136016
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2013617857
Short name T693
Test name
Test status
Simulation time 245937956 ps
CPU time 1.22 seconds
Started Mar 05 12:59:22 PM PST 24
Finished Mar 05 12:59:24 PM PST 24
Peak memory 196840 kb
Host smart-2edbafaa-5a77-4857-86ba-7c0a9af042b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013617857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2013617857
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3320445353
Short name T282
Test name
Test status
Simulation time 27193907657 ps
CPU time 177.48 seconds
Started Mar 05 12:59:30 PM PST 24
Finished Mar 05 01:02:28 PM PST 24
Peak memory 198216 kb
Host smart-0de790fe-9521-458c-8c40-b40df7f9d861
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320445353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3320445353
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2686858055
Short name T898
Test name
Test status
Simulation time 31671168 ps
CPU time 0.99 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 196588 kb
Host smart-590fdf2d-94e0-46a4-b955-7f834a984338
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2686858055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2686858055
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495317508
Short name T920
Test name
Test status
Simulation time 49762187 ps
CPU time 1.34 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 196744 kb
Host smart-d2ec5406-f1eb-41ea-88ab-3f13e80c05a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495317508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1495317508
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.498477970
Short name T902
Test name
Test status
Simulation time 791224289 ps
CPU time 1.46 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 196532 kb
Host smart-ecca297e-f7a5-41ad-935c-7ced8639da8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=498477970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.498477970
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3578031583
Short name T921
Test name
Test status
Simulation time 139933976 ps
CPU time 1.02 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 195872 kb
Host smart-7bef2957-3fd2-42cc-ae3e-8687e0390c62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578031583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3578031583
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.480959284
Short name T856
Test name
Test status
Simulation time 60941705 ps
CPU time 1.32 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 196380 kb
Host smart-b5c019fe-2e69-4a85-a81a-71c938e2b88f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=480959284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.480959284
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3717293824
Short name T851
Test name
Test status
Simulation time 28960336 ps
CPU time 0.68 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:22 PM PST 24
Peak memory 194280 kb
Host smart-aa181a7a-8ad4-4f69-a041-40d09f0f0746
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717293824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3717293824
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2697607005
Short name T838
Test name
Test status
Simulation time 116864796 ps
CPU time 1.14 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196628 kb
Host smart-0939aac7-6086-4568-ab9c-54f4ba2f72fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2697607005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2697607005
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233424177
Short name T854
Test name
Test status
Simulation time 130666966 ps
CPU time 1.12 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:26 PM PST 24
Peak memory 195852 kb
Host smart-d6e5f2a5-20f7-4884-af22-375a8233f37c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233424177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2233424177
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3324450297
Short name T930
Test name
Test status
Simulation time 83632911 ps
CPU time 1.36 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 196740 kb
Host smart-259a16bd-1e41-4e5e-8462-78cb694157ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3324450297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3324450297
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1228010107
Short name T893
Test name
Test status
Simulation time 140894080 ps
CPU time 1.32 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 196936 kb
Host smart-bb7edf14-7350-435f-8c5e-974a8fa00f1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228010107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1228010107
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1349977134
Short name T926
Test name
Test status
Simulation time 43539827 ps
CPU time 0.93 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 195728 kb
Host smart-68faeaec-5e92-450c-877e-a65527da374c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1349977134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1349977134
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324064113
Short name T857
Test name
Test status
Simulation time 200962880 ps
CPU time 1.04 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196456 kb
Host smart-053144c6-3cdf-4753-9a37-c1edaaf22924
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324064113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3324064113
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1315583143
Short name T845
Test name
Test status
Simulation time 21366410 ps
CPU time 0.77 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 195372 kb
Host smart-084e3487-1fa2-4ace-a1a1-bcd625ee15fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1315583143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1315583143
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71020716
Short name T916
Test name
Test status
Simulation time 71669227 ps
CPU time 1.25 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 197976 kb
Host smart-591125d9-0e37-44b4-a9cb-02d3e6de5ecd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71020716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.71020716
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1562726037
Short name T858
Test name
Test status
Simulation time 358749815 ps
CPU time 1.41 seconds
Started Mar 05 12:39:30 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 196652 kb
Host smart-d42c1c93-b4c5-4d27-902f-197f7a3cb056
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1562726037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1562726037
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3022758074
Short name T880
Test name
Test status
Simulation time 65846769 ps
CPU time 0.85 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 196136 kb
Host smart-1b63affc-8dc0-449c-bd03-6ccbc24b1d07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022758074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3022758074
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3994747789
Short name T924
Test name
Test status
Simulation time 113951499 ps
CPU time 1.04 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 196464 kb
Host smart-3b05e5c3-c094-4796-9bf9-412aa8e270fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3994747789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3994747789
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945807624
Short name T872
Test name
Test status
Simulation time 63641294 ps
CPU time 1.12 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 196712 kb
Host smart-6381ead8-e57a-470f-b5b3-eb8f4e3b4093
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945807624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1945807624
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3788942381
Short name T928
Test name
Test status
Simulation time 102931094 ps
CPU time 1.41 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 196724 kb
Host smart-4334cfe0-b815-4ea7-bb9c-bf44c8c4b840
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3788942381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3788942381
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3628811779
Short name T839
Test name
Test status
Simulation time 153167958 ps
CPU time 1.15 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 197960 kb
Host smart-94acddd0-2655-42ba-8cfb-8fabdcaf2bca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628811779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3628811779
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3852585757
Short name T903
Test name
Test status
Simulation time 151919144 ps
CPU time 1 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 197920 kb
Host smart-d48fa0f6-cef9-4667-8601-3ccaa65f53e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3852585757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3852585757
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272851840
Short name T932
Test name
Test status
Simulation time 336050965 ps
CPU time 1.3 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 195612 kb
Host smart-636d8e72-cad9-4b1e-8e4d-bafef2f50601
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272851840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1272851840
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3368000253
Short name T910
Test name
Test status
Simulation time 221842004 ps
CPU time 1.33 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 196784 kb
Host smart-5f50b5e9-41d6-4bb6-b17f-3b4d565a8b88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3368000253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3368000253
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4099206124
Short name T884
Test name
Test status
Simulation time 120896978 ps
CPU time 1.04 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 196480 kb
Host smart-3483351d-1869-4dbe-a503-180ddb6b1a99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099206124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4099206124
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1868462310
Short name T853
Test name
Test status
Simulation time 59674227 ps
CPU time 0.88 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 196508 kb
Host smart-37d240bf-9b73-44c4-bdd0-ed4532e280d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1868462310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1868462310
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3590151222
Short name T842
Test name
Test status
Simulation time 28671820 ps
CPU time 0.75 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 195928 kb
Host smart-cfa3b4da-c95e-49cb-95c3-e10cda41c32f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590151222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3590151222
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3125086102
Short name T866
Test name
Test status
Simulation time 241846530 ps
CPU time 1.35 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 197836 kb
Host smart-a9c0ffcf-78bd-4fb5-9600-badafea19602
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3125086102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3125086102
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113988475
Short name T919
Test name
Test status
Simulation time 53682309 ps
CPU time 0.76 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 195340 kb
Host smart-26b9c1dc-a324-42c0-b0de-679addeb6485
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113988475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.113988475
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2859302289
Short name T844
Test name
Test status
Simulation time 31977361 ps
CPU time 0.7 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 194392 kb
Host smart-bb686d89-6d55-472b-93fa-88a0cf762ee6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2859302289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2859302289
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.739960046
Short name T873
Test name
Test status
Simulation time 261337976 ps
CPU time 1.15 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:26 PM PST 24
Peak memory 196536 kb
Host smart-3219993f-d8ad-4e15-a6ad-482acfa63709
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739960046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.739960046
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.289016599
Short name T875
Test name
Test status
Simulation time 46615706 ps
CPU time 1.07 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 196600 kb
Host smart-095f8070-4664-437f-a454-ba19fb0ff166
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289016599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.289016599
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3280095886
Short name T904
Test name
Test status
Simulation time 44043504 ps
CPU time 1.16 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 195608 kb
Host smart-a2c2908b-5059-4b82-9bc6-56197e4c9ca7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280095886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3280095886
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1608453528
Short name T874
Test name
Test status
Simulation time 61416389 ps
CPU time 1.05 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 196868 kb
Host smart-67d75c3b-7c0a-4737-ba72-1cb3c73cdf4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1608453528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1608453528
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2609783219
Short name T882
Test name
Test status
Simulation time 77866843 ps
CPU time 1.1 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 195812 kb
Host smart-53a1ca39-995f-4ff2-b2f0-648e92da7e93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609783219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2609783219
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4283779440
Short name T852
Test name
Test status
Simulation time 264009416 ps
CPU time 1.26 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 196684 kb
Host smart-b95e14b4-745e-4e9a-944f-5b0c042a168c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4283779440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4283779440
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057199996
Short name T907
Test name
Test status
Simulation time 172235459 ps
CPU time 1.45 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196540 kb
Host smart-49a81944-9f44-43c0-a17b-77dde542b960
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057199996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1057199996
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3192802822
Short name T888
Test name
Test status
Simulation time 72362504 ps
CPU time 0.93 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 197724 kb
Host smart-8848c5cf-ac98-47d5-af37-e2358456ef58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3192802822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3192802822
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2835779736
Short name T912
Test name
Test status
Simulation time 54453028 ps
CPU time 1.42 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 198088 kb
Host smart-088c2294-4769-4ee6-8119-9ec3ccf578dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835779736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2835779736
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2366274621
Short name T840
Test name
Test status
Simulation time 122424941 ps
CPU time 0.95 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 196568 kb
Host smart-976a8629-8dfe-4091-a4dc-3e798170725f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2366274621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2366274621
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2486595026
Short name T860
Test name
Test status
Simulation time 52517746 ps
CPU time 1.3 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 196840 kb
Host smart-181b8047-b7e6-4a5f-ad97-d3c258b6ddfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486595026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2486595026
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2336780390
Short name T868
Test name
Test status
Simulation time 281779284 ps
CPU time 1.19 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:03 PM PST 24
Peak memory 196616 kb
Host smart-907fd796-7549-41e8-9f99-2065f270a8a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2336780390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2336780390
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.224819047
Short name T897
Test name
Test status
Simulation time 120549005 ps
CPU time 1 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 198072 kb
Host smart-8e899b38-dee8-4d16-80da-234ca8e51a50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224819047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.224819047
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3131667745
Short name T881
Test name
Test status
Simulation time 167721156 ps
CPU time 1.15 seconds
Started Mar 05 12:39:03 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 195564 kb
Host smart-bf8b2729-862a-456f-8610-c9967085937c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3131667745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3131667745
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.315131672
Short name T871
Test name
Test status
Simulation time 25671779 ps
CPU time 0.83 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 195516 kb
Host smart-dc5efa6b-95d7-41ab-a28d-bee9dfcbc1ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315131672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.315131672
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3527350905
Short name T886
Test name
Test status
Simulation time 64979891 ps
CPU time 1.18 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 196464 kb
Host smart-964433d3-5479-4bdc-9597-e0ee08ed2142
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3527350905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3527350905
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2851758178
Short name T890
Test name
Test status
Simulation time 249330750 ps
CPU time 1.06 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 197960 kb
Host smart-9accffaf-9aa9-4ea2-b773-e94da6795e4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851758178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2851758178
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2356400585
Short name T900
Test name
Test status
Simulation time 303629683 ps
CPU time 1.33 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 196492 kb
Host smart-b6e87599-6863-4c6a-8505-a4aa40483963
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2356400585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2356400585
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3160637379
Short name T901
Test name
Test status
Simulation time 206478774 ps
CPU time 1.08 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 195660 kb
Host smart-56200af2-8cf1-4f5d-99f5-ef7ee312f8fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160637379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3160637379
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3239095577
Short name T885
Test name
Test status
Simulation time 85224541 ps
CPU time 1.42 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 196480 kb
Host smart-2fc9be28-e123-4b9a-b094-ff29e73ce648
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3239095577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3239095577
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540825278
Short name T909
Test name
Test status
Simulation time 55275428 ps
CPU time 1.07 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 196764 kb
Host smart-ef92a6a1-fe77-447b-a08b-fdbcd2d48b32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540825278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.540825278
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1172486642
Short name T861
Test name
Test status
Simulation time 232527593 ps
CPU time 1.08 seconds
Started Mar 05 12:39:08 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 195724 kb
Host smart-0d84a4c0-11ff-4016-88a8-dbfda50c1faf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1172486642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1172486642
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3486772775
Short name T933
Test name
Test status
Simulation time 409115993 ps
CPU time 1.3 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 196752 kb
Host smart-df07f5b9-797f-466c-87b0-300c74ed3b78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486772775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3486772775
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4158410007
Short name T914
Test name
Test status
Simulation time 262007305 ps
CPU time 1.24 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196516 kb
Host smart-eac82abf-3bb2-4d07-92a7-afc622f59ef1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4158410007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4158410007
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4057127693
Short name T929
Test name
Test status
Simulation time 153038340 ps
CPU time 1.16 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:22 PM PST 24
Peak memory 195840 kb
Host smart-cebf7c31-f343-43c0-ba7e-9c573a7010c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057127693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4057127693
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1816968712
Short name T896
Test name
Test status
Simulation time 189784233 ps
CPU time 1.13 seconds
Started Mar 05 12:39:21 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 197488 kb
Host smart-160c210d-d8d1-40eb-8ffd-f5f2ef826c75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1816968712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1816968712
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.514144886
Short name T836
Test name
Test status
Simulation time 114185279 ps
CPU time 0.97 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 196484 kb
Host smart-b0722740-7714-4f5d-a867-459d0de9d5e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514144886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.514144886
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2116002696
Short name T927
Test name
Test status
Simulation time 56747207 ps
CPU time 1.22 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 197500 kb
Host smart-1dad0417-b807-4946-a8c2-e05c2d74c05b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2116002696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2116002696
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2944875003
Short name T895
Test name
Test status
Simulation time 224320092 ps
CPU time 1.22 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 196828 kb
Host smart-ea05f29f-836b-4c61-b1d6-6cf1723f06a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944875003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2944875003
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2328045992
Short name T849
Test name
Test status
Simulation time 326606204 ps
CPU time 1.42 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 197576 kb
Host smart-9b59aed1-12f1-4509-a565-d4c428377b65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2328045992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2328045992
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1653213773
Short name T892
Test name
Test status
Simulation time 126833018 ps
CPU time 0.86 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:26 PM PST 24
Peak memory 195928 kb
Host smart-0f01c682-1513-44e1-802f-ebc51d482ca6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653213773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1653213773
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.965968642
Short name T891
Test name
Test status
Simulation time 40731138 ps
CPU time 1.19 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 196404 kb
Host smart-2895334d-1476-4a71-8c7d-379873c9cf54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=965968642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.965968642
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453201455
Short name T877
Test name
Test status
Simulation time 141094640 ps
CPU time 1.1 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 197628 kb
Host smart-87a89672-bef5-4559-874f-578acc97efea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453201455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3453201455
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2547732713
Short name T850
Test name
Test status
Simulation time 102485836 ps
CPU time 1.39 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 198048 kb
Host smart-e7e713ee-e929-4b58-9f9b-4093ce8277bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2547732713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2547732713
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2149577221
Short name T864
Test name
Test status
Simulation time 80662812 ps
CPU time 0.9 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 195884 kb
Host smart-e8e1c56c-5487-4f11-ba4a-90dd5389f4c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149577221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2149577221
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1916696017
Short name T911
Test name
Test status
Simulation time 306030716 ps
CPU time 1.43 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 198128 kb
Host smart-0f808b71-f3fe-4de7-af4d-1bc6e7c8fdd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1916696017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1916696017
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.440974877
Short name T869
Test name
Test status
Simulation time 222981705 ps
CPU time 1.34 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 198104 kb
Host smart-340f38b9-4ff6-43d5-8075-587a07a17891
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440974877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.440974877
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1042516900
Short name T931
Test name
Test status
Simulation time 65713509 ps
CPU time 1.31 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 197968 kb
Host smart-644f072c-de3b-44f0-91c5-adba45ad2c31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1042516900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1042516900
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.469871386
Short name T913
Test name
Test status
Simulation time 49279782 ps
CPU time 1.14 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 196256 kb
Host smart-1584109f-89ba-47b5-9d3a-4aa9cf5a76b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469871386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.469871386
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3553034001
Short name T837
Test name
Test status
Simulation time 96656310 ps
CPU time 0.78 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 195300 kb
Host smart-d3589636-4c4e-4f4e-ac0e-4ff090d14552
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3553034001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3553034001
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2020141379
Short name T917
Test name
Test status
Simulation time 37772432 ps
CPU time 1.01 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 196432 kb
Host smart-6043a90f-5ea5-474a-9cd4-4c80af42b3f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020141379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2020141379
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1642215434
Short name T867
Test name
Test status
Simulation time 103247433 ps
CPU time 1.5 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 196648 kb
Host smart-aa34fdab-81a0-4bdb-8daa-e253fa96b47c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1642215434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1642215434
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2980072196
Short name T915
Test name
Test status
Simulation time 79743609 ps
CPU time 0.87 seconds
Started Mar 05 12:39:32 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 196916 kb
Host smart-bb74a45b-307a-4bbf-b884-5e52d443c64d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980072196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2980072196
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3628067528
Short name T876
Test name
Test status
Simulation time 57624508 ps
CPU time 1.27 seconds
Started Mar 05 12:39:46 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 196696 kb
Host smart-e7b19ed1-829d-48ac-952d-42882e4afc90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3628067528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3628067528
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3688953094
Short name T835
Test name
Test status
Simulation time 261430606 ps
CPU time 1.2 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 196548 kb
Host smart-c8c1c86e-528b-438f-a965-5e5889633619
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688953094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3688953094
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4124344330
Short name T934
Test name
Test status
Simulation time 206180874 ps
CPU time 1.02 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 195796 kb
Host smart-84c6e5a7-cae1-4082-9f4c-21d2bea81142
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4124344330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4124344330
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501941540
Short name T899
Test name
Test status
Simulation time 145102792 ps
CPU time 0.98 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 196512 kb
Host smart-45a8d2bc-4d59-4faf-9e98-f64be88e6375
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501941540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3501941540
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1342918093
Short name T847
Test name
Test status
Simulation time 135735287 ps
CPU time 0.87 seconds
Started Mar 05 12:39:26 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 196440 kb
Host smart-bff1d9f2-9e90-4eae-8b93-1575a25391cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1342918093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1342918093
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.877741539
Short name T855
Test name
Test status
Simulation time 216001370 ps
CPU time 1.04 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 195872 kb
Host smart-d4b032e3-455e-4e93-925f-fcbd13ce6699
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877741539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.877741539
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2566623101
Short name T887
Test name
Test status
Simulation time 61488205 ps
CPU time 1.14 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 195820 kb
Host smart-4fa37e91-899c-41f7-8b77-c548a270b034
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2566623101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2566623101
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1462332329
Short name T922
Test name
Test status
Simulation time 43283659 ps
CPU time 0.87 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 195404 kb
Host smart-267a291e-f9b1-4540-b7e0-dd816622ba4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462332329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1462332329
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2960626181
Short name T843
Test name
Test status
Simulation time 35204229 ps
CPU time 1.12 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196540 kb
Host smart-71a90b27-2ce9-433e-8fe6-4eb4fb3f4a45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2960626181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2960626181
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1543910381
Short name T905
Test name
Test status
Simulation time 42833886 ps
CPU time 1.06 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 196572 kb
Host smart-d9aff2c2-8d98-4135-b21e-aec7ff53ece8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543910381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1543910381
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2609429038
Short name T918
Test name
Test status
Simulation time 148038603 ps
CPU time 0.87 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 196036 kb
Host smart-aa7df82a-9539-4817-86a7-93e564b8a6db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2609429038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2609429038
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.680597640
Short name T848
Test name
Test status
Simulation time 123128569 ps
CPU time 1.02 seconds
Started Mar 05 12:39:19 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 196328 kb
Host smart-66965aa1-1675-4e63-9efc-c86c6d10e4ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680597640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.680597640
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2174202540
Short name T879
Test name
Test status
Simulation time 263342031 ps
CPU time 1.11 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 196032 kb
Host smart-80cdfb7a-68b7-48ea-a20a-7f08c921d0e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2174202540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2174202540
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456231509
Short name T870
Test name
Test status
Simulation time 64837923 ps
CPU time 1.22 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 195860 kb
Host smart-10edb43d-beb4-4d40-bd80-1bdf2e5958a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456231509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3456231509
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.613466270
Short name T862
Test name
Test status
Simulation time 248390768 ps
CPU time 0.86 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 195464 kb
Host smart-83b2df99-2b9a-4bb8-8f6f-4a4232c91ce6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=613466270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.613466270
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833506418
Short name T906
Test name
Test status
Simulation time 132703759 ps
CPU time 0.92 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 196472 kb
Host smart-8a4e87fa-f8c5-45c4-b29e-efb82c96da39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833506418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2833506418
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2857982821
Short name T883
Test name
Test status
Simulation time 72957013 ps
CPU time 0.67 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 194920 kb
Host smart-99e03ba0-2b13-4d8f-aa08-fe22d203b1f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2857982821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2857982821
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1930459620
Short name T925
Test name
Test status
Simulation time 546523315 ps
CPU time 0.97 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 195724 kb
Host smart-9dcf502f-7ac3-4ead-937a-69a5157cde9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930459620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1930459620
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3179179204
Short name T846
Test name
Test status
Simulation time 39468412 ps
CPU time 0.89 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 197856 kb
Host smart-b426ceca-1ecc-434c-a07f-a5f1a2444af6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3179179204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3179179204
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169437821
Short name T894
Test name
Test status
Simulation time 435395696 ps
CPU time 0.89 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 196384 kb
Host smart-1b4fbafc-b9e0-46b4-aead-d75db3714952
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169437821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3169437821
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2259791896
Short name T865
Test name
Test status
Simulation time 43060611 ps
CPU time 1.15 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 195604 kb
Host smart-9ef0e2dd-8772-43b0-bb70-f42caa21f92a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2259791896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2259791896
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.314900854
Short name T859
Test name
Test status
Simulation time 261682270 ps
CPU time 1.29 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196920 kb
Host smart-99d6736d-7289-4276-9a44-9ea219fd3421
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314900854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.314900854
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4044386579
Short name T863
Test name
Test status
Simulation time 73930704 ps
CPU time 0.69 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 194952 kb
Host smart-f05060a9-3924-4aa3-a35d-a88721bb6a7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4044386579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4044386579
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585354270
Short name T841
Test name
Test status
Simulation time 50352654 ps
CPU time 1.31 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 196540 kb
Host smart-36304ebd-0b9f-451d-8bf4-9df74b6d4c34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585354270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1585354270
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1861627245
Short name T878
Test name
Test status
Simulation time 259783955 ps
CPU time 1.31 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 196992 kb
Host smart-828cd036-a9ef-4380-8e50-60a5f84b3410
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1861627245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1861627245
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4141012562
Short name T889
Test name
Test status
Simulation time 54677428 ps
CPU time 1.47 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196664 kb
Host smart-055d5b16-9a95-4a5b-beb8-b12b6a16e387
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141012562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4141012562
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3374753699
Short name T908
Test name
Test status
Simulation time 128741103 ps
CPU time 1.21 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 197932 kb
Host smart-2e2cfa39-53d8-48b5-a7ab-7aa31b85a057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3374753699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3374753699
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4180361378
Short name T923
Test name
Test status
Simulation time 49062057 ps
CPU time 0.95 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 196456 kb
Host smart-21bbfe53-47e8-4f37-8efa-13243a5cb4f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180361378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4180361378
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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