Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4635066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20749794

1

T21

722

T22

283

T23

311

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10137436	1			T21	846		T22	56		T23	506
values[0x0]	7491749	1			T21	148		T22	125		T23	34
values[0x1]	7755675	1			T21	150		T22	128		T23	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3559650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21825210

1

T21

805

T22

287

T23

357

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87972	1			T21	8		T22	2		T26	5
valid_sources[0x01]	92156	1			T21	7		T22	5		T24	8
valid_sources[0x02]	91074	1			T21	2		T22	1		T27	1
valid_sources[0x03]	95746	1			T21	1		T22	1		T24	3
valid_sources[0x04]	93493	1			T21	2		T27	1		T29	24
valid_sources[0x05]	151907	1			T21	6		T27	1		T29	25
valid_sources[0x06]	99601	1			T21	6		T22	4		T27	2
valid_sources[0x07]	228947	1			T21	3		T22	2		T29	26
valid_sources[0x08]	94002	1			T21	3		T22	5		T26	4
valid_sources[0x09]	91156	1			T21	6		T27	1		T29	21
valid_sources[0x0a]	96696	1			T21	6		T27	1		T28	8
valid_sources[0x0b]	97039	1			T21	3		T28	2		T29	22
valid_sources[0x0c]	98878	1			T21	5		T29	25		T30	1
valid_sources[0x0d]	84196	1			T21	7		T27	3		T29	37
valid_sources[0x0e]	87198	1			T21	2		T22	5		T24	1
valid_sources[0x0f]	90629	1			T21	2		T22	4		T27	1
valid_sources[0x10]	85054	1			T21	3		T24	2		T27	1
valid_sources[0x11]	90074	1			T21	5		T27	1		T29	42
valid_sources[0x12]	90442	1			T21	3		T28	3		T29	24
valid_sources[0x13]	95123	1			T21	2		T22	2		T27	1
valid_sources[0x14]	91326	1			T21	2		T27	3		T28	1
valid_sources[0x15]	90958	1			T21	2		T22	2		T27	2
valid_sources[0x16]	93947	1			T21	10		T28	1		T29	23
valid_sources[0x17]	199724	1			T21	15		T27	1		T29	18
valid_sources[0x18]	99177	1			T21	4		T27	1		T29	20
valid_sources[0x19]	92378	1			T21	4		T22	2		T26	1
valid_sources[0x1a]	96140	1			T21	2		T26	1		T27	1
valid_sources[0x1b]	95479	1			T21	7		T27	2		T28	4
valid_sources[0x1c]	91063	1			T21	7		T26	4		T27	2
valid_sources[0x1d]	89662	1			T21	6		T24	7		T27	1
valid_sources[0x1e]	94457	1			T21	4		T27	1		T28	2
valid_sources[0x1f]	203863	1			T21	2		T27	2		T28	1
valid_sources[0x20]	86539	1			T21	4		T27	1		T29	15
valid_sources[0x21]	92068	1			T21	4		T29	19		T30	1
valid_sources[0x22]	98828	1			T21	4		T22	1		T24	5
valid_sources[0x23]	102905	1			T21	4		T22	2		T26	1
valid_sources[0x24]	93508	1			T21	1		T26	4		T27	2
valid_sources[0x25]	90350	1			T21	1		T29	11		T30	1
valid_sources[0x26]	91086	1			T21	7		T26	3		T27	3
valid_sources[0x27]	91072	1			T21	5		T27	3		T29	27
valid_sources[0x28]	99065	1			T21	8		T26	1		T27	1
valid_sources[0x29]	84490	1			T21	3		T22	5		T27	2
valid_sources[0x2a]	89279	1			T21	1		T22	3		T27	2
valid_sources[0x2b]	100278	1			T21	2		T22	6		T27	1
valid_sources[0x2c]	231274	1			T21	9		T22	2		T27	3
valid_sources[0x2d]	100014	1			T21	2		T22	2		T27	1
valid_sources[0x2e]	88460	1			T22	8		T26	2		T29	25
valid_sources[0x2f]	94673	1			T21	2		T22	3		T29	11
valid_sources[0x30]	127079	1			T21	6		T22	5		T27	2
valid_sources[0x31]	94964	1			T21	5		T22	1		T28	5
valid_sources[0x32]	86086	1			T21	11		T22	15		T28	1
valid_sources[0x33]	95026	1			T21	6		T27	3		T29	24
valid_sources[0x34]	101658	1			T21	4		T27	3		T28	7
valid_sources[0x35]	99016	1			T21	1		T26	2		T27	1
valid_sources[0x36]	89021	1			T21	5		T27	2		T29	17
valid_sources[0x37]	88662	1			T21	2		T24	21		T27	1
valid_sources[0x38]	89732	1			T21	3		T24	2		T27	1
valid_sources[0x39]	215164	1			T21	10		T22	1		T24	2
valid_sources[0x3a]	98969	1			T21	1		T27	1		T28	1
valid_sources[0x3b]	95288	1			T21	6		T29	15		T121	2
valid_sources[0x3c]	98895	1			T21	2		T28	2		T29	18
valid_sources[0x3d]	88238	1			T21	5		T22	2		T26	1
valid_sources[0x3e]	97173	1			T21	3		T22	2		T29	25
valid_sources[0x3f]	88555	1			T21	7		T22	6		T27	2
valid_sources[0x40]	90377	1			T21	1		T24	1		T26	1
valid_sources[0x41]	92167	1			T21	3		T22	4		T29	14
valid_sources[0x42]	94268	1			T21	2		T22	5		T24	5
valid_sources[0x43]	89828	1			T21	3		T29	21		T121	1
valid_sources[0x44]	89025	1			T21	2		T22	2		T27	2
valid_sources[0x45]	94820	1			T21	5		T28	4		T29	18
valid_sources[0x46]	91835	1			T21	4		T22	4		T27	3
valid_sources[0x47]	93710	1			T21	4		T22	3		T27	1
valid_sources[0x48]	96478	1			T21	4		T27	2		T29	22
valid_sources[0x49]	87616	1			T21	4		T22	6		T27	1
valid_sources[0x4a]	94253	1			T21	5		T27	1		T28	1
valid_sources[0x4b]	99059	1			T21	3		T22	1		T27	1
valid_sources[0x4c]	105000	1			T21	4		T24	3		T29	27
valid_sources[0x4d]	92537	1			T21	7		T24	10		T26	2
valid_sources[0x4e]	89522	1			T21	4		T22	4		T24	1
valid_sources[0x4f]	93353	1			T21	7		T24	10		T28	1
valid_sources[0x50]	90470	1			T21	4		T27	1		T29	23
valid_sources[0x51]	101007	1			T21	6		T28	2		T29	26
valid_sources[0x52]	101585	1			T21	6		T27	1		T29	29
valid_sources[0x53]	102392	1			T21	2		T27	1		T28	2
valid_sources[0x54]	90166	1			T21	3		T22	1		T24	4
valid_sources[0x55]	94223	1			T21	2		T22	2		T27	2
valid_sources[0x56]	99639	1			T21	7		T27	1		T29	21
valid_sources[0x57]	97965	1			T21	5		T22	4		T24	3
valid_sources[0x58]	93841	1			T21	7		T22	2		T24	26
valid_sources[0x59]	90902	1			T21	4		T24	1		T27	1
valid_sources[0x5a]	94200	1			T21	7		T22	3		T27	1
valid_sources[0x5b]	103073	1			T21	3		T27	2		T28	2
valid_sources[0x5c]	92466	1			T21	2		T22	3		T24	2
valid_sources[0x5d]	98237	1			T21	1		T26	3		T27	1
valid_sources[0x5e]	93606	1			T21	5		T22	1		T27	3
valid_sources[0x5f]	95102	1			T21	5		T22	2		T27	1
valid_sources[0x60]	90394	1			T21	3		T29	20		T121	2
valid_sources[0x61]	101318	1			T21	6		T22	5		T29	19
valid_sources[0x62]	94358	1			T21	4		T27	1		T29	19
valid_sources[0x63]	98184	1			T21	4		T22	1		T29	22
valid_sources[0x64]	100579	1			T21	7		T22	1		T27	2
valid_sources[0x65]	103949	1			T21	3		T27	3		T28	4
valid_sources[0x66]	87413	1			T21	2		T29	16		T30	5
valid_sources[0x67]	93202	1			T21	4		T27	2		T28	1
valid_sources[0x68]	97473	1			T21	3		T22	3		T28	1
valid_sources[0x69]	97931	1			T21	8		T27	2		T29	21
valid_sources[0x6a]	95147	1			T21	5		T27	1		T29	19
valid_sources[0x6b]	99282	1			T21	9		T27	2		T29	18
valid_sources[0x6c]	91192	1			T21	4		T29	22		T30	1
valid_sources[0x6d]	88580	1			T21	5		T29	21		T30	1
valid_sources[0x6e]	99233	1			T21	9		T24	5		T27	1
valid_sources[0x6f]	96915	1			T21	1		T27	2		T29	15
valid_sources[0x70]	96091	1			T21	6		T27	1		T28	4
valid_sources[0x71]	102616	1			T21	6		T29	16		T30	1
valid_sources[0x72]	96079	1			T21	2		T22	4		T27	1
valid_sources[0x73]	207207	1			T21	3		T24	21		T27	1
valid_sources[0x74]	96500	1			T21	4		T26	4		T27	1
valid_sources[0x75]	87922	1			T21	9		T24	5		T26	1
valid_sources[0x76]	88865	1			T21	4		T27	1		T29	43
valid_sources[0x77]	91078	1			T21	4		T22	4		T27	2
valid_sources[0x78]	96547	1			T21	3		T29	34		T30	1
valid_sources[0x79]	94895	1			T21	5		T22	3		T24	3
valid_sources[0x7a]	99654	1			T21	4		T29	11		T30	1
valid_sources[0x7b]	94299	1			T21	5		T22	4		T27	2
valid_sources[0x7c]	98632	1			T21	3		T29	20		T31	2722
valid_sources[0x7d]	91460	1			T21	3		T22	3		T24	3
valid_sources[0x7e]	93359	1			T21	7		T22	1		T24	7
valid_sources[0x7f]	91321	1			T21	4		T22	1		T28	2
valid_sources[0x80]	93633	1			T21	4		T29	25		T31	2622

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5821322

1

T21

424

T22

30

T23

233

values[0x0]

all_enables

biggest_size

7465173

1

T21

148

T22

125

T23

34

values[0x1]

all_enables

biggest_size

7463299

1

T21

150

T22

128

T23

44