Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	196694764	0	0	0
ctrl_en_input_filter_rd_A	196694764	44622	0	0
intr_ctrl_en_falling_rd_A	196694764	45104	0	0
intr_ctrl_en_lvlhigh_rd_A	196694764	44443	0	0
intr_ctrl_en_lvllow_rd_A	196694764	44973	0	0
intr_ctrl_en_rising_rd_A	196694764	44741	0	0
intr_enable_rd_A	196694764	44083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	44622	0	0
T1	47990	338	0	0
T2	0	324	0	0
T3	0	363	0	0
T4	0	5646	0	0
T5	0	1001	0	0
T6	0	157	0	0
T7	0	5742	0	0
T8	0	7581	0	0
T9	0	554	0	0
T10	0	263	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	45104	0	0
T1	47990	348	0	0
T2	0	241	0	0
T3	0	328	0	0
T4	0	5429	0	0
T5	0	1026	0	0
T6	0	142	0	0
T7	0	5603	0	0
T8	0	7720	0	0
T9	0	631	0	0
T10	0	95	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	44443	0	0
T1	47990	349	0	0
T2	0	339	0	0
T3	0	384	0	0
T4	0	5524	0	0
T5	0	1032	0	0
T6	0	87	0	0
T7	0	5647	0	0
T8	0	7539	0	0
T9	0	594	0	0
T10	0	228	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	44973	0	0
T1	47990	365	0	0
T2	0	370	0	0
T3	0	333	0	0
T4	0	5081	0	0
T5	0	888	0	0
T6	0	146	0	0
T7	0	5826	0	0
T8	0	7625	0	0
T9	0	692	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0
T20	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	44741	0	0
T1	47990	368	0	0
T2	0	380	0	0
T3	0	319	0	0
T4	0	5349	0	0
T5	0	1062	0	0
T6	0	147	0	0
T7	0	5685	0	0
T8	0	7319	0	0
T9	0	642	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0
T20	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196694764	44083	0	0
T1	47990	374	0	0
T2	0	276	0	0
T3	0	391	0	0
T4	0	5181	0	0
T5	0	1187	0	0
T6	0	91	0	0
T7	0	5738	0	0
T8	0	7513	0	0
T9	0	546	0	0
T10	0	183	0	0
T11	1942	0	0	0
T12	1593	0	0	0
T13	3617	0	0	0
T14	3816	0	0	0
T15	2964	0	0	0
T16	23358	0	0	0
T17	1343	0	0	0
T18	1368	0	0	0
T19	815	0	0	0