Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4219039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19462271

1

T22

780

T1

3003

T11

392

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9315697	1			T22	936		T1	2172		T11	79
values[0x0]	7047301	1			T22	142		T1	942		T11	174
values[0x1]	7318312	1			T22	169		T1	915		T11	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3225164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20456146

1

T22

865

T1

3231

T11

396

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91570	1			T22	1		T1	13		T12	1568
valid_sources[0x01]	93930	1			T1	11		T12	1543		T15	7
valid_sources[0x02]	83618	1			T1	22		T11	7		T12	1571
valid_sources[0x03]	92171	1			T1	16		T11	5		T12	1569
valid_sources[0x04]	88094	1			T1	13		T12	1581		T14	2
valid_sources[0x05]	91438	1			T22	7		T1	17		T12	1513
valid_sources[0x06]	89294	1			T22	6		T1	20		T12	1558
valid_sources[0x07]	83840	1			T22	2		T1	21		T11	7
valid_sources[0x08]	89755	1			T22	9		T1	10		T12	1519
valid_sources[0x09]	85343	1			T22	3		T1	20		T12	1562
valid_sources[0x0a]	87955	1			T22	2		T1	14		T11	28
valid_sources[0x0b]	89542	1			T1	18		T12	1550		T14	3
valid_sources[0x0c]	94205	1			T22	1		T1	20		T12	1567
valid_sources[0x0d]	90296	1			T22	6		T1	14		T12	1581
valid_sources[0x0e]	85919	1			T22	5		T1	6		T11	5
valid_sources[0x0f]	88279	1			T1	16		T12	1549		T14	5
valid_sources[0x10]	88813	1			T22	1		T1	18		T12	1581
valid_sources[0x11]	84862	1			T22	17		T1	8		T11	2
valid_sources[0x12]	93035	1			T22	3		T1	21		T11	8
valid_sources[0x13]	82514	1			T22	8		T1	9		T12	1562
valid_sources[0x14]	87397	1			T22	3		T1	18		T12	1558
valid_sources[0x15]	88810	1			T22	1		T1	12		T11	8
valid_sources[0x16]	90865	1			T22	15		T1	19		T11	4
valid_sources[0x17]	86534	1			T22	14		T1	10		T12	1469
valid_sources[0x18]	92403	1			T22	2		T1	13		T12	1472
valid_sources[0x19]	88622	1			T22	5		T1	19		T12	1659
valid_sources[0x1a]	83847	1			T22	9		T1	14		T11	1
valid_sources[0x1b]	94873	1			T22	2		T1	18		T12	1512
valid_sources[0x1c]	82356	1			T1	19		T12	1455		T14	6
valid_sources[0x1d]	88987	1			T22	8		T1	19		T12	1473
valid_sources[0x1e]	88812	1			T1	11		T12	1572		T14	8
valid_sources[0x1f]	93110	1			T22	6		T1	18		T12	1488
valid_sources[0x20]	94737	1			T22	1		T1	20		T12	1573
valid_sources[0x21]	89619	1			T22	6		T1	20		T11	5
valid_sources[0x22]	90645	1			T22	10		T1	15		T12	1577
valid_sources[0x23]	85887	1			T1	22		T11	3		T12	1523
valid_sources[0x24]	91382	1			T22	12		T1	12		T12	1470
valid_sources[0x25]	83689	1			T22	8		T1	16		T12	1557
valid_sources[0x26]	85614	1			T22	3		T1	17		T12	1573
valid_sources[0x27]	88410	1			T22	3		T1	18		T11	3
valid_sources[0x28]	91022	1			T22	5		T1	16		T12	1520
valid_sources[0x29]	85358	1			T22	14		T1	21		T12	1495
valid_sources[0x2a]	90123	1			T22	2		T1	21		T11	1
valid_sources[0x2b]	88452	1			T22	3		T1	10		T11	1
valid_sources[0x2c]	88246	1			T22	10		T1	14		T11	1
valid_sources[0x2d]	89803	1			T22	10		T1	16		T12	1580
valid_sources[0x2e]	87551	1			T22	9		T1	15		T11	1
valid_sources[0x2f]	85105	1			T22	1		T1	15		T12	1525
valid_sources[0x30]	99128	1			T22	4		T1	24		T12	1581
valid_sources[0x31]	85409	1			T22	14		T1	7		T11	1
valid_sources[0x32]	89121	1			T22	3		T1	14		T12	1539
valid_sources[0x33]	90464	1			T22	1		T1	23		T12	1590
valid_sources[0x34]	105287	1			T22	13		T1	21		T12	1566
valid_sources[0x35]	89330	1			T22	7		T1	10		T12	1523
valid_sources[0x36]	90606	1			T22	10		T1	18		T12	1566
valid_sources[0x37]	87613	1			T22	5		T1	16		T12	1536
valid_sources[0x38]	85544	1			T22	3		T1	16		T12	1543
valid_sources[0x39]	94584	1			T22	4		T1	19		T12	1629
valid_sources[0x3a]	95901	1			T22	2		T1	12		T12	1527
valid_sources[0x3b]	94157	1			T22	4		T1	14		T11	8
valid_sources[0x3c]	84314	1			T22	3		T1	25		T11	10
valid_sources[0x3d]	93383	1			T22	8		T1	13		T12	1488
valid_sources[0x3e]	85099	1			T22	2		T1	12		T12	1513
valid_sources[0x3f]	88198	1			T22	4		T1	16		T11	3
valid_sources[0x40]	88338	1			T22	5		T1	17		T11	9
valid_sources[0x41]	89090	1			T1	8		T12	1557		T14	3
valid_sources[0x42]	92118	1			T1	12		T12	1567		T14	5
valid_sources[0x43]	88350	1			T22	2		T1	16		T12	1522
valid_sources[0x44]	89517	1			T22	15		T1	20		T12	1552
valid_sources[0x45]	82865	1			T22	4		T1	13		T12	1517
valid_sources[0x46]	86513	1			T22	4		T1	21		T12	1653
valid_sources[0x47]	88471	1			T22	7		T1	17		T12	1523
valid_sources[0x48]	213088	1			T1	14		T12	1496		T14	2
valid_sources[0x49]	90907	1			T1	12		T12	1577		T14	4
valid_sources[0x4a]	157768	1			T22	1		T1	13		T11	3
valid_sources[0x4b]	86769	1			T22	5		T1	13		T11	2
valid_sources[0x4c]	89316	1			T22	3		T1	20		T12	1488
valid_sources[0x4d]	85497	1			T22	13		T1	18		T12	1572
valid_sources[0x4e]	89999	1			T22	2		T1	11		T11	5
valid_sources[0x4f]	84819	1			T22	1		T1	13		T12	1609
valid_sources[0x50]	90839	1			T22	2		T1	18		T11	2
valid_sources[0x51]	172617	1			T22	7		T1	13		T12	1593
valid_sources[0x52]	176494	1			T22	7		T1	14		T12	1513
valid_sources[0x53]	89825	1			T22	1		T1	21		T12	1475
valid_sources[0x54]	85094	1			T22	4		T1	15		T12	1539
valid_sources[0x55]	88503	1			T1	13		T12	1610		T14	4
valid_sources[0x56]	86617	1			T22	5		T1	22		T12	1521
valid_sources[0x57]	92014	1			T22	5		T1	11		T12	1551
valid_sources[0x58]	86260	1			T1	18		T12	1536		T14	3
valid_sources[0x59]	88078	1			T22	9		T1	15		T12	1550
valid_sources[0x5a]	98167	1			T22	3		T1	15		T12	1485
valid_sources[0x5b]	88756	1			T22	3		T1	9		T12	1503
valid_sources[0x5c]	84888	1			T22	3		T1	18		T12	1471
valid_sources[0x5d]	94401	1			T22	3		T1	15		T12	1543
valid_sources[0x5e]	88197	1			T22	4		T1	19		T11	10
valid_sources[0x5f]	99799	1			T22	2		T1	12		T12	1567
valid_sources[0x60]	91684	1			T22	2		T1	14		T11	1
valid_sources[0x61]	90523	1			T1	11		T12	1437		T13	1
valid_sources[0x62]	93524	1			T22	1		T1	15		T12	1480
valid_sources[0x63]	89377	1			T22	7		T1	19		T11	3
valid_sources[0x64]	86755	1			T22	2		T1	15		T12	1552
valid_sources[0x65]	85740	1			T1	17		T12	1553		T14	6
valid_sources[0x66]	85403	1			T22	5		T1	14		T12	1587
valid_sources[0x67]	86481	1			T1	16		T12	1460		T13	1
valid_sources[0x68]	92773	1			T22	1		T1	16		T11	10
valid_sources[0x69]	89996	1			T22	2		T1	11		T12	1510
valid_sources[0x6a]	90547	1			T22	7		T1	16		T12	1519
valid_sources[0x6b]	86366	1			T22	2		T1	18		T12	1570
valid_sources[0x6c]	89647	1			T22	3		T1	12		T12	1507
valid_sources[0x6d]	89770	1			T22	12		T1	10		T11	3
valid_sources[0x6e]	87396	1			T22	19		T1	12		T12	1570
valid_sources[0x6f]	93105	1			T1	15		T11	22		T12	1512
valid_sources[0x70]	84942	1			T22	6		T1	18		T11	10
valid_sources[0x71]	94301	1			T22	4		T1	14		T11	14
valid_sources[0x72]	88801	1			T22	3		T1	24		T12	1528
valid_sources[0x73]	94636	1			T22	1		T1	14		T12	1563
valid_sources[0x74]	92577	1			T1	25		T12	1567		T14	5
valid_sources[0x75]	91190	1			T22	4		T1	11		T12	1553
valid_sources[0x76]	89422	1			T22	14		T1	13		T11	7
valid_sources[0x77]	90314	1			T22	7		T1	17		T12	1520
valid_sources[0x78]	92444	1			T22	4		T1	15		T11	4
valid_sources[0x79]	86215	1			T1	20		T12	1526		T14	4
valid_sources[0x7a]	88568	1			T22	5		T1	17		T12	1601
valid_sources[0x7b]	95975	1			T22	5		T1	17		T12	1561
valid_sources[0x7c]	87525	1			T22	2		T1	15		T11	2
valid_sources[0x7d]	93355	1			T22	1		T1	14		T12	1558
valid_sources[0x7e]	88537	1			T1	12		T11	7		T12	1595
valid_sources[0x7f]	91516	1			T22	16		T1	13		T12	1500
valid_sources[0x80]	90771	1			T22	2		T1	20		T12	1531

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5419777

1

T22

469

T1

1146

T11

41

values[0x0]

all_enables

biggest_size

7020404

1

T22

142

T1

942

T11

174

values[0x1]

all_enables

biggest_size

7022090

1

T22

169

T1

915

T11

177