Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	193556233	0	0	0
ctrl_en_input_filter_rd_A	193556233	66582	0	0
intr_ctrl_en_falling_rd_A	193556233	66153	0	0
intr_ctrl_en_lvlhigh_rd_A	193556233	66624	0	0
intr_ctrl_en_lvllow_rd_A	193556233	66530	0	0
intr_ctrl_en_rising_rd_A	193556233	66035	0	0
intr_enable_rd_A	193556233	66699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66582	0	0
T1	37971	188	0	0
T2	0	3	0	0
T3	0	763	0	0
T4	0	10	0	0
T5	0	3276	0	0
T6	0	2561	0	0
T7	0	7083	0	0
T8	0	3372	0	0
T9	0	2060	0	0
T10	0	111	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66153	0	0
T1	37971	175	0	0
T3	0	753	0	0
T4	0	4	0	0
T5	0	3515	0	0
T6	0	2342	0	0
T7	0	6867	0	0
T8	0	3351	0	0
T9	0	2166	0	0
T10	0	123	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0
T20	0	7	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66624	0	0
T1	37971	252	0	0
T3	0	733	0	0
T5	0	3489	0	0
T6	0	2206	0	0
T7	0	7132	0	0
T8	0	3840	0	0
T9	0	2258	0	0
T10	0	146	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0
T20	0	6	0	0
T21	0	1155	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66530	0	0
T1	37971	147	0	0
T2	0	8	0	0
T3	0	683	0	0
T4	0	2	0	0
T5	0	3423	0	0
T6	0	2435	0	0
T7	0	6564	0	0
T8	0	3222	0	0
T9	0	2124	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0
T20	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66035	0	0
T1	37971	183	0	0
T2	0	12	0	0
T3	0	575	0	0
T4	0	7	0	0
T5	0	3677	0	0
T6	0	2285	0	0
T7	0	6663	0	0
T8	0	3429	0	0
T9	0	2278	0	0
T10	0	127	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193556233	66699	0	0
T1	37971	268	0	0
T2	0	7	0	0
T3	0	650	0	0
T5	0	3368	0	0
T6	0	2362	0	0
T7	0	7200	0	0
T8	0	3571	0	0
T9	0	2158	0	0
T10	0	122	0	0
T11	3304	0	0	0
T12	228031	0	0	0
T13	942	0	0	0
T14	9475	0	0	0
T15	5663	0	0	0
T16	4471	0	0	0
T17	9551	0	0	0
T18	18255	0	0	0
T19	1923	0	0	0
T21	0	1071	0	0