Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3754726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16266144

1

T22

1433

T23

65

T24

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8113357	1			T22	1692		T23	51		T24	17
values[0x0]	5861299	1			T22	291		T23	22		T24	84
values[0x1]	6046214	1			T22	283		T23	19		T24	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2898682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17122188

1

T22

1598

T23

69

T24

166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75615	1			T22	12		T23	2		T25	882
valid_sources[0x01]	70853	1			T22	13		T27	1		T28	3692
valid_sources[0x02]	69415	1			T22	3		T27	3		T28	3769
valid_sources[0x03]	71076	1			T22	9		T27	1		T28	3994
valid_sources[0x04]	68569	1			T22	14		T27	1		T28	3685
valid_sources[0x05]	69306	1			T22	8		T27	3		T28	3365
valid_sources[0x06]	73019	1			T22	10		T27	2		T28	3524
valid_sources[0x07]	70486	1			T22	7		T23	1		T24	2
valid_sources[0x08]	75749	1			T22	11		T23	1		T28	3805
valid_sources[0x09]	78982	1			T22	6		T28	4086		T1	19
valid_sources[0x0a]	80018	1			T22	12		T27	1		T28	3664
valid_sources[0x0b]	75295	1			T22	10		T23	2		T28	2993
valid_sources[0x0c]	74728	1			T22	14		T27	1		T28	3548
valid_sources[0x0d]	73495	1			T22	10		T23	1		T27	1
valid_sources[0x0e]	79194	1			T22	2		T27	2		T28	3949
valid_sources[0x0f]	77661	1			T22	5		T28	3748		T31	12
valid_sources[0x10]	73963	1			T22	7		T23	2		T24	3
valid_sources[0x11]	78106	1			T22	7		T27	1		T28	3762
valid_sources[0x12]	63932	1			T22	12		T23	2		T24	3
valid_sources[0x13]	80742	1			T22	13		T23	1		T24	2
valid_sources[0x14]	79608	1			T22	11		T28	3005		T29	3
valid_sources[0x15]	68994	1			T22	9		T28	3573		T29	1
valid_sources[0x16]	84145	1			T22	6		T27	1		T28	4201
valid_sources[0x17]	76041	1			T22	11		T23	1		T27	1
valid_sources[0x18]	80533	1			T22	9		T24	4		T28	3677
valid_sources[0x19]	70278	1			T22	5		T27	1		T28	4065
valid_sources[0x1a]	147715	1			T22	7		T23	1		T24	7
valid_sources[0x1b]	70271	1			T22	11		T27	1		T28	4022
valid_sources[0x1c]	72709	1			T22	10		T23	1		T27	2
valid_sources[0x1d]	71458	1			T22	7		T27	1		T28	3822
valid_sources[0x1e]	76954	1			T22	7		T24	3		T27	1
valid_sources[0x1f]	79932	1			T22	10		T27	1		T28	3823
valid_sources[0x20]	118024	1			T22	8		T27	3		T28	3472
valid_sources[0x21]	82262	1			T22	3		T23	1		T24	1
valid_sources[0x22]	72090	1			T22	12		T27	1		T28	3799
valid_sources[0x23]	169323	1			T22	12		T27	2		T28	3212
valid_sources[0x24]	76480	1			T22	11		T27	2		T28	3618
valid_sources[0x25]	73374	1			T22	7		T23	1		T27	2
valid_sources[0x26]	78495	1			T22	9		T23	1		T27	1
valid_sources[0x27]	73164	1			T22	5		T28	4225		T1	20
valid_sources[0x28]	72325	1			T22	7		T27	2		T28	3688
valid_sources[0x29]	79842	1			T22	7		T23	1		T27	2
valid_sources[0x2a]	71053	1			T22	14		T23	1		T28	4465
valid_sources[0x2b]	159390	1			T22	21		T28	3524		T29	5
valid_sources[0x2c]	76683	1			T22	17		T27	2		T28	3433
valid_sources[0x2d]	77823	1			T22	11		T27	1		T28	3535
valid_sources[0x2e]	68639	1			T22	4		T23	1		T27	1
valid_sources[0x2f]	68228	1			T22	8		T24	4		T28	3353
valid_sources[0x30]	75982	1			T22	9		T27	1		T28	3936
valid_sources[0x31]	73879	1			T22	5		T24	1		T27	1
valid_sources[0x32]	73560	1			T22	14		T27	2		T28	3986
valid_sources[0x33]	68800	1			T22	6		T24	6		T27	1
valid_sources[0x34]	75596	1			T22	12		T23	2		T28	3634
valid_sources[0x35]	69065	1			T22	5		T28	3926		T1	10
valid_sources[0x36]	71325	1			T22	6		T28	3146		T1	27
valid_sources[0x37]	82714	1			T22	14		T27	2		T28	3663
valid_sources[0x38]	70237	1			T22	11		T23	1		T27	1
valid_sources[0x39]	71829	1			T22	5		T27	4		T28	3374
valid_sources[0x3a]	74032	1			T22	7		T27	2		T28	3213
valid_sources[0x3b]	75699	1			T22	12		T24	9		T27	4
valid_sources[0x3c]	69353	1			T22	3		T24	1		T27	2
valid_sources[0x3d]	67849	1			T22	9		T23	1		T28	3437
valid_sources[0x3e]	77752	1			T22	15		T24	1		T27	2
valid_sources[0x3f]	71145	1			T22	7		T27	1		T28	3922
valid_sources[0x40]	81893	1			T22	12		T23	1		T27	1
valid_sources[0x41]	146987	1			T22	18		T23	1		T28	4390
valid_sources[0x42]	83538	1			T22	9		T27	2		T28	3797
valid_sources[0x43]	77688	1			T22	13		T27	1		T28	4983
valid_sources[0x44]	75215	1			T23	1		T27	1		T28	3974
valid_sources[0x45]	75094	1			T22	4		T27	1		T28	3908
valid_sources[0x46]	66200	1			T22	17		T27	1		T28	3681
valid_sources[0x47]	77807	1			T22	14		T24	10		T28	3701
valid_sources[0x48]	81357	1			T22	9		T23	1		T27	1
valid_sources[0x49]	83311	1			T22	7		T27	2		T28	3002
valid_sources[0x4a]	79542	1			T22	10		T24	1		T28	3753
valid_sources[0x4b]	71749	1			T22	9		T27	1		T28	3776
valid_sources[0x4c]	67742	1			T22	7		T27	3		T28	3938
valid_sources[0x4d]	75833	1			T22	7		T24	1		T27	1
valid_sources[0x4e]	82106	1			T22	10		T23	1		T27	2
valid_sources[0x4f]	149326	1			T22	10		T24	3		T27	3
valid_sources[0x50]	76883	1			T22	8		T28	4298		T29	2
valid_sources[0x51]	73085	1			T22	7		T27	1		T28	4083
valid_sources[0x52]	207632	1			T22	14		T23	2		T28	3956
valid_sources[0x53]	76333	1			T22	11		T27	2		T28	3476
valid_sources[0x54]	75442	1			T22	10		T27	2		T28	4354
valid_sources[0x55]	78298	1			T22	12		T27	4		T28	3887
valid_sources[0x56]	75400	1			T22	6		T24	1		T27	4
valid_sources[0x57]	83628	1			T22	10		T27	1		T28	3964
valid_sources[0x58]	80456	1			T22	6		T27	2		T28	3265
valid_sources[0x59]	72992	1			T22	7		T27	1		T28	3265
valid_sources[0x5a]	74349	1			T22	10		T23	1		T27	1
valid_sources[0x5b]	82113	1			T22	13		T23	2		T27	1
valid_sources[0x5c]	77483	1			T22	7		T24	2		T27	1
valid_sources[0x5d]	73984	1			T22	8		T24	2		T27	1
valid_sources[0x5e]	155153	1			T22	9		T23	1		T24	3
valid_sources[0x5f]	70373	1			T22	10		T27	2		T28	4150
valid_sources[0x60]	73369	1			T22	15		T23	1		T27	2
valid_sources[0x61]	74200	1			T22	10		T27	2		T28	4155
valid_sources[0x62]	74078	1			T22	6		T23	2		T27	1
valid_sources[0x63]	69764	1			T22	8		T28	3761		T29	2
valid_sources[0x64]	79613	1			T22	20		T27	1		T28	3404
valid_sources[0x65]	75198	1			T22	8		T24	6		T27	1
valid_sources[0x66]	83828	1			T22	2		T28	3685		T1	17
valid_sources[0x67]	72598	1			T22	4		T27	2		T28	3733
valid_sources[0x68]	69103	1			T22	8		T27	2		T28	3708
valid_sources[0x69]	75238	1			T22	9		T27	1		T28	3799
valid_sources[0x6a]	71779	1			T22	5		T24	2		T27	1
valid_sources[0x6b]	75919	1			T22	1		T24	1		T27	1
valid_sources[0x6c]	72424	1			T22	9		T27	3		T28	4107
valid_sources[0x6d]	82367	1			T22	9		T26	2		T27	2
valid_sources[0x6e]	74847	1			T22	6		T27	1		T28	3926
valid_sources[0x6f]	75484	1			T22	12		T27	1		T28	3457
valid_sources[0x70]	73500	1			T22	15		T28	3381		T1	22
valid_sources[0x71]	72169	1			T22	9		T23	2		T27	1
valid_sources[0x72]	74187	1			T22	14		T27	1		T28	3301
valid_sources[0x73]	76108	1			T22	9		T27	3		T28	4057
valid_sources[0x74]	66099	1			T22	9		T28	3535		T1	8
valid_sources[0x75]	78614	1			T22	8		T28	3394		T29	3
valid_sources[0x76]	76045	1			T22	7		T23	1		T28	4264
valid_sources[0x77]	77088	1			T22	10		T27	3		T28	3613
valid_sources[0x78]	80218	1			T22	8		T28	3247		T1	25
valid_sources[0x79]	74746	1			T22	8		T27	4		T28	3423
valid_sources[0x7a]	71398	1			T22	8		T23	1		T27	3
valid_sources[0x7b]	63237	1			T22	8		T23	2		T27	1
valid_sources[0x7c]	80882	1			T22	4		T24	1		T27	1
valid_sources[0x7d]	76961	1			T22	9		T28	3284		T1	14
valid_sources[0x7e]	74643	1			T22	14		T26	7		T27	2
valid_sources[0x7f]	76157	1			T22	8		T27	3		T28	3194
valid_sources[0x80]	85522	1			T22	11		T28	4346		T29	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4583311

1

T22

859

T23

24

T24

11

values[0x0]

all_enables

biggest_size

5842477

1

T22

291

T23

22

T24

84

values[0x1]

all_enables

biggest_size

5840356

1

T22

283

T23

19

T24

69