Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149098137	0	0	0
ctrl_en_input_filter_rd_A	149098137	37537	0	0
intr_ctrl_en_falling_rd_A	149098137	37084	0	0
intr_ctrl_en_lvlhigh_rd_A	149098137	37099	0	0
intr_ctrl_en_lvllow_rd_A	149098137	37730	0	0
intr_ctrl_en_rising_rd_A	149098137	37244	0	0
intr_enable_rd_A	149098137	38136	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	37537	0	0
T1	45819	362	0	0
T2	38037	269	0	0
T3	0	1	0	0
T4	0	6054	0	0
T5	0	252	0	0
T6	0	110	0	0
T7	0	1	0	0
T8	0	6636	0	0
T9	0	2121	0	0
T10	0	62	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	37084	0	0
T1	45819	345	0	0
T2	38037	260	0	0
T4	0	5540	0	0
T5	0	190	0	0
T6	0	71	0	0
T8	0	6440	0	0
T9	0	2049	0	0
T10	0	56	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0
T19	0	3	0	0
T20	0	4254	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	37099	0	0
T1	45819	327	0	0
T2	38037	248	0	0
T4	0	5500	0	0
T5	0	317	0	0
T6	0	69	0	0
T7	0	10	0	0
T8	0	6558	0	0
T9	0	2206	0	0
T10	0	32	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0
T21	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	37730	0	0
T1	45819	247	0	0
T2	38037	258	0	0
T4	0	5563	0	0
T5	0	219	0	0
T6	0	85	0	0
T7	0	5	0	0
T8	0	6750	0	0
T9	0	2168	0	0
T10	0	61	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0
T21	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	37244	0	0
T1	45819	311	0	0
T2	38037	247	0	0
T4	0	5642	0	0
T5	0	238	0	0
T6	0	81	0	0
T7	0	5	0	0
T8	0	6608	0	0
T9	0	2292	0	0
T10	0	65	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0
T21	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149098137	38136	0	0
T1	45819	410	0	0
T2	38037	253	0	0
T4	0	5767	0	0
T5	0	163	0	0
T6	0	77	0	0
T7	0	11	0	0
T8	0	6186	0	0
T9	0	2346	0	0
T10	0	57	0	0
T11	5307	0	0	0
T12	4561	0	0	0
T13	85038	0	0	0
T14	2471	0	0	0
T15	6847	0	0	0
T16	6597	0	0	0
T17	4395	0	0	0
T18	5757	0	0	0
T21	0	1	0	0