Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3261997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14064681

1

T32

191

T1

141

T11

441

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7053980	1			T32	75		T1	16		T11	83
values[0x0]	5057447	1			T32	79		T1	65		T11	193
values[0x1]	5215251	1			T32	77		T1	68		T11	207

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2520258	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14806420

1

T32

203

T1

144

T11

450

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64737	1			T1	3		T12	1		T14	1
valid_sources[0x01]	63533	1			T32	3		T11	6		T12	1
valid_sources[0x02]	69028	1			T1	1		T12	2		T16	219
valid_sources[0x03]	62456	1			T12	3		T14	1		T16	209
valid_sources[0x04]	66823	1			T11	1		T12	2		T14	1
valid_sources[0x05]	254923	1			T32	1		T12	1		T13	1
valid_sources[0x06]	65896	1			T12	1		T14	1		T16	264
valid_sources[0x07]	66673	1			T12	7		T13	4		T14	2
valid_sources[0x08]	68899	1			T32	3		T1	1		T12	1
valid_sources[0x09]	66851	1			T12	1		T13	2		T14	2
valid_sources[0x0a]	58923	1			T12	1		T13	2		T14	2
valid_sources[0x0b]	64625	1			T1	1		T12	1		T14	1
valid_sources[0x0c]	60755	1			T12	2		T14	2		T16	212
valid_sources[0x0d]	74661	1			T32	1		T12	1		T14	1
valid_sources[0x0e]	61923	1			T1	1		T12	5		T13	2
valid_sources[0x0f]	69667	1			T32	2		T1	1		T11	1
valid_sources[0x10]	60582	1			T1	1		T12	2		T14	2
valid_sources[0x11]	115531	1			T32	1		T12	4		T14	2
valid_sources[0x12]	61891	1			T1	1		T13	1		T14	2
valid_sources[0x13]	65210	1			T1	2		T12	1		T16	215
valid_sources[0x14]	60729	1			T12	4		T14	1		T16	214
valid_sources[0x15]	70753	1			T32	4		T1	1		T12	4
valid_sources[0x16]	69167	1			T1	3		T11	12		T12	2
valid_sources[0x17]	70082	1			T32	5		T1	1		T11	5
valid_sources[0x18]	62929	1			T11	5		T12	4		T13	2
valid_sources[0x19]	62703	1			T32	4		T11	8		T12	1
valid_sources[0x1a]	62284	1			T32	1		T12	2		T14	1
valid_sources[0x1b]	64589	1			T12	4		T14	2		T16	182
valid_sources[0x1c]	67176	1			T1	1		T12	2		T16	251
valid_sources[0x1d]	67021	1			T14	3		T16	218		T112	3
valid_sources[0x1e]	66383	1			T16	274		T112	2		T114	1
valid_sources[0x1f]	60265	1			T32	5		T12	2		T16	237
valid_sources[0x20]	58793	1			T1	1		T12	2		T14	1
valid_sources[0x21]	64061	1			T1	1		T12	2		T14	1
valid_sources[0x22]	66887	1			T32	3		T11	1		T12	2
valid_sources[0x23]	65900	1			T11	2		T12	2		T14	1
valid_sources[0x24]	61456	1			T32	2		T1	1		T12	2
valid_sources[0x25]	62999	1			T1	1		T12	2		T13	5
valid_sources[0x26]	59583	1			T12	2		T16	233		T115	1
valid_sources[0x27]	61587	1			T12	2		T14	2		T16	213
valid_sources[0x28]	72609	1			T32	2		T12	3		T16	215
valid_sources[0x29]	60795	1			T32	1		T12	2		T13	1
valid_sources[0x2a]	70722	1			T32	3		T12	3		T16	227
valid_sources[0x2b]	64150	1			T11	5		T12	4		T14	1
valid_sources[0x2c]	63877	1			T32	1		T16	245		T112	4
valid_sources[0x2d]	65312	1			T11	1		T12	3		T14	3
valid_sources[0x2e]	57115	1			T32	5		T12	2		T14	1
valid_sources[0x2f]	65196	1			T1	2		T11	4		T14	1
valid_sources[0x30]	68851	1			T32	1		T1	1		T12	1
valid_sources[0x31]	61329	1			T12	2		T16	198		T112	4
valid_sources[0x32]	67033	1			T32	10		T1	1		T11	3
valid_sources[0x33]	57895	1			T32	1		T11	7		T16	219
valid_sources[0x34]	65304	1			T32	4		T1	1		T11	1
valid_sources[0x35]	66127	1			T11	6		T12	3		T13	3
valid_sources[0x36]	62596	1			T1	3		T12	2		T13	2
valid_sources[0x37]	61632	1			T11	19		T12	2		T16	240
valid_sources[0x38]	67844	1			T11	3		T14	2		T16	253
valid_sources[0x39]	64836	1			T32	1		T12	2		T16	253
valid_sources[0x3a]	59676	1			T1	1		T11	2		T12	1
valid_sources[0x3b]	59597	1			T1	1		T12	1		T13	2
valid_sources[0x3c]	59290	1			T1	1		T11	1		T13	2
valid_sources[0x3d]	75997	1			T1	1		T11	1		T12	2
valid_sources[0x3e]	57048	1			T12	2		T13	2		T16	203
valid_sources[0x3f]	62023	1			T1	1		T12	3		T16	263
valid_sources[0x40]	70409	1			T12	4		T14	1		T16	222
valid_sources[0x41]	69251	1			T1	2		T11	2		T12	4
valid_sources[0x42]	83456	1			T32	1		T12	4		T16	219
valid_sources[0x43]	58117	1			T11	2		T12	3		T16	272
valid_sources[0x44]	64708	1			T32	1		T12	6		T16	209
valid_sources[0x45]	62717	1			T32	2		T1	2		T12	1
valid_sources[0x46]	60312	1			T32	2		T11	1		T14	1
valid_sources[0x47]	65440	1			T32	1		T12	3		T13	1
valid_sources[0x48]	68383	1			T32	2		T11	5		T12	4
valid_sources[0x49]	104597	1			T12	2		T16	237		T114	1
valid_sources[0x4a]	60737	1			T11	5		T12	3		T16	199
valid_sources[0x4b]	180092	1			T32	4		T11	3		T12	3
valid_sources[0x4c]	70062	1			T32	1		T1	2		T14	1
valid_sources[0x4d]	62867	1			T32	2		T1	1		T11	1
valid_sources[0x4e]	60838	1			T11	2		T12	5		T16	247
valid_sources[0x4f]	59542	1			T11	6		T12	1		T16	220
valid_sources[0x50]	70346	1			T32	1		T1	1		T12	3
valid_sources[0x51]	62645	1			T32	1		T1	1		T12	3
valid_sources[0x52]	60443	1			T11	2		T14	1		T16	225
valid_sources[0x53]	60985	1			T1	3		T12	5		T13	2
valid_sources[0x54]	59246	1			T32	2		T1	1		T11	1
valid_sources[0x55]	69361	1			T1	1		T12	1		T16	231
valid_sources[0x56]	63170	1			T1	1		T12	3		T13	3
valid_sources[0x57]	62897	1			T32	1		T12	1		T13	1
valid_sources[0x58]	68043	1			T32	1		T12	2		T13	1
valid_sources[0x59]	61199	1			T32	1		T1	1		T11	5
valid_sources[0x5a]	63145	1			T11	3		T12	3		T13	4
valid_sources[0x5b]	65073	1			T32	6		T11	1		T12	3
valid_sources[0x5c]	71653	1			T32	1		T11	6		T12	1
valid_sources[0x5d]	66059	1			T12	3		T14	2		T16	256
valid_sources[0x5e]	58899	1			T32	1		T12	2		T16	212
valid_sources[0x5f]	71310	1			T32	4		T12	1		T13	1
valid_sources[0x60]	61916	1			T1	4		T12	2		T14	1
valid_sources[0x61]	87310	1			T12	1		T16	229		T112	5
valid_sources[0x62]	61320	1			T11	6		T12	2		T14	1
valid_sources[0x63]	68381	1			T12	1		T14	1		T16	245
valid_sources[0x64]	68296	1			T12	4		T13	2		T14	2
valid_sources[0x65]	62490	1			T1	1		T12	1		T16	207
valid_sources[0x66]	62649	1			T12	1		T13	1		T14	1
valid_sources[0x67]	63772	1			T32	1		T11	5		T12	4
valid_sources[0x68]	57023	1			T12	1		T16	230		T112	5
valid_sources[0x69]	72340	1			T11	1		T12	3		T14	1
valid_sources[0x6a]	60392	1			T32	2		T11	4		T12	2
valid_sources[0x6b]	59807	1			T1	1		T11	1		T12	3
valid_sources[0x6c]	62758	1			T32	2		T11	2		T12	4
valid_sources[0x6d]	62310	1			T32	1		T11	9		T12	2
valid_sources[0x6e]	58418	1			T32	1		T11	8		T12	3
valid_sources[0x6f]	66088	1			T32	3		T12	3		T16	209
valid_sources[0x70]	64014	1			T32	5		T1	1		T12	2
valid_sources[0x71]	64063	1			T32	7		T12	2		T16	204
valid_sources[0x72]	62297	1			T32	3		T1	1		T11	17
valid_sources[0x73]	64620	1			T32	4		T1	1		T12	1
valid_sources[0x74]	63510	1			T12	1		T13	1		T14	1
valid_sources[0x75]	60008	1			T1	1		T11	1		T12	2
valid_sources[0x76]	63152	1			T12	1		T13	3		T14	1
valid_sources[0x77]	68604	1			T32	5		T1	3		T11	2
valid_sources[0x78]	61576	1			T12	1		T13	1		T16	235
valid_sources[0x79]	64069	1			T11	1		T12	6		T16	197
valid_sources[0x7a]	58743	1			T1	2		T12	2		T16	244
valid_sources[0x7b]	74027	1			T12	4		T16	218		T112	7
valid_sources[0x7c]	61009	1			T12	4		T16	259		T112	2
valid_sources[0x7d]	61795	1			T32	3		T12	5		T14	1
valid_sources[0x7e]	68355	1			T32	2		T1	1		T12	1
valid_sources[0x7f]	64493	1			T11	1		T14	2		T16	219
valid_sources[0x80]	63178	1			T11	2		T12	4		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3982858

1

T32

35

T1

8

T11

41

values[0x0]

all_enables

biggest_size

5041415

1

T32

79

T1

65

T11

193

values[0x1]

all_enables

biggest_size

5040408

1

T32

77

T1

68

T11

207