Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132109957	0	0	0
ctrl_en_input_filter_rd_A	132109957	73969	0	0
intr_ctrl_en_falling_rd_A	132109957	76334	0	0
intr_ctrl_en_lvlhigh_rd_A	132109957	74165	0	0
intr_ctrl_en_lvllow_rd_A	132109957	74675	0	0
intr_ctrl_en_rising_rd_A	132109957	74689	0	0
intr_enable_rd_A	132109957	75172	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	73969	0	0
T1	5497	4	0	0
T2	0	96	0	0
T3	0	1396	0	0
T4	0	186	0	0
T5	0	7255	0	0
T6	0	203	0	0
T7	0	470	0	0
T8	0	1133	0	0
T9	0	1458	0	0
T10	0	3399	0	0
T11	8321	0	0	0
T12	4944	0	0	0
T13	2660	0	0	0
T14	5414	0	0	0
T15	937	0	0	0
T16	289963	0	0	0
T17	4466	0	0	0
T18	1816	0	0	0
T19	1589	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	76334	0	0
T2	19333	103	0	0
T3	0	1336	0	0
T4	0	185	0	0
T5	0	7226	0	0
T6	0	163	0	0
T7	0	506	0	0
T8	0	1040	0	0
T9	0	1519	0	0
T10	0	3240	0	0
T20	0	334	0	0
T21	1336	0	0	0
T22	11414	0	0	0
T23	12568	0	0	0
T24	1221	0	0	0
T25	9778	0	0	0
T26	3036	0	0	0
T27	4753	0	0	0
T28	1996	0	0	0
T29	5138	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	74165	0	0
T2	19333	115	0	0
T3	0	1269	0	0
T4	0	203	0	0
T5	0	7285	0	0
T6	0	207	0	0
T7	0	468	0	0
T8	0	1035	0	0
T9	0	1331	0	0
T10	0	3377	0	0
T21	1336	0	0	0
T22	11414	0	0	0
T23	12568	0	0	0
T24	1221	0	0	0
T25	9778	0	0	0
T26	3036	0	0	0
T27	4753	0	0	0
T28	1996	0	0	0
T29	5138	0	0	0
T30	0	4	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	74675	0	0
T2	19333	68	0	0
T3	0	1349	0	0
T4	0	204	0	0
T5	0	6911	0	0
T6	0	177	0	0
T7	0	399	0	0
T8	0	1135	0	0
T9	0	1299	0	0
T10	0	3314	0	0
T21	1336	0	0	0
T22	11414	0	0	0
T23	12568	0	0	0
T24	1221	0	0	0
T25	9778	0	0	0
T26	3036	0	0	0
T27	4753	0	0	0
T28	1996	0	0	0
T29	5138	0	0	0
T31	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	74689	0	0
T2	19333	120	0	0
T3	0	1258	0	0
T4	0	196	0	0
T5	0	7824	0	0
T6	0	203	0	0
T7	0	451	0	0
T8	0	1204	0	0
T9	0	1370	0	0
T21	1336	0	0	0
T22	11414	0	0	0
T23	12568	0	0	0
T24	1221	0	0	0
T25	9778	0	0	0
T26	3036	0	0	0
T27	4753	0	0	0
T28	1996	0	0	0
T29	5138	0	0	0
T30	0	3	0	0
T31	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132109957	75172	0	0
T2	19333	188	0	0
T3	0	1501	0	0
T4	0	198	0	0
T5	0	7395	0	0
T6	0	243	0	0
T7	0	392	0	0
T8	0	1218	0	0
T9	0	1309	0	0
T10	0	3201	0	0
T21	1336	0	0	0
T22	11414	0	0	0
T23	12568	0	0	0
T24	1221	0	0	0
T25	9778	0	0	0
T26	3036	0	0	0
T27	4753	0	0	0
T28	1996	0	0	0
T29	5138	0	0	0
T31	0	8	0	0