Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	143804132	0	0	0
ctrl_en_input_filter_rd_A	143804132	79458	0	0
intr_ctrl_en_falling_rd_A	143804132	82395	0	0
intr_ctrl_en_lvlhigh_rd_A	143804132	79451	0	0
intr_ctrl_en_lvllow_rd_A	143804132	81315	0	0
intr_ctrl_en_rising_rd_A	143804132	79145	0	0
intr_enable_rd_A	143804132	80547	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	79458	0	0
T1	123329	4412	0	0
T2	52749	334	0	0
T3	0	1557	0	0
T4	0	141	0	0
T5	0	153	0	0
T6	0	215	0	0
T7	0	6284	0	0
T8	0	10	0	0
T9	0	264	0	0
T10	0	7	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	82395	0	0
T1	123329	4262	0	0
T2	52749	419	0	0
T3	0	1686	0	0
T4	0	151	0	0
T5	0	178	0	0
T6	0	145	0	0
T7	0	5732	0	0
T9	0	307	0	0
T10	0	7	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0
T19	0	3869	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	79451	0	0
T1	123329	4295	0	0
T2	52749	420	0	0
T3	0	1524	0	0
T4	0	154	0	0
T5	0	192	0	0
T6	0	132	0	0
T7	0	5824	0	0
T9	0	373	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0
T19	0	3546	0	0
T20	0	4069	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	81315	0	0
T1	123329	4172	0	0
T2	52749	407	0	0
T3	0	1649	0	0
T4	0	187	0	0
T5	0	143	0	0
T6	0	190	0	0
T7	0	6027	0	0
T9	0	312	0	0
T10	0	5	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0
T19	0	3745	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	79145	0	0
T1	123329	4502	0	0
T2	52749	417	0	0
T3	0	1468	0	0
T4	0	190	0	0
T5	0	140	0	0
T6	0	185	0	0
T7	0	6042	0	0
T9	0	309	0	0
T10	0	4	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0
T19	0	3621	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143804132	80547	0	0
T1	123329	4317	0	0
T2	52749	432	0	0
T3	0	1518	0	0
T4	0	193	0	0
T5	0	129	0	0
T6	0	145	0	0
T7	0	6324	0	0
T9	0	317	0	0
T10	0	3	0	0
T11	50269	0	0	0
T12	9142	0	0	0
T13	3383	0	0	0
T14	3081	0	0	0
T15	130778	0	0	0
T16	999	0	0	0
T17	3997	0	0	0
T18	2317	0	0	0
T19	0	3749	0	0