Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2872705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12582117

1

T25

2006

T26

105

T27

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6231980	1			T25	3158		T26	110		T27	19
values[0x0]	4538080	1			T25	211		T26	27		T27	64
values[0x1]	4684762	1			T25	223		T26	27		T27	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2215591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13239231

1

T25

2337

T26

120

T27

129

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138902	1			T25	5		T26	1		T12	3
valid_sources[0x01]	59339	1			T12	3		T13	1		T14	2
valid_sources[0x02]	51761	1			T25	30		T12	2		T14	1
valid_sources[0x03]	56499	1			T25	1		T12	3		T14	1
valid_sources[0x04]	116016	1			T12	6		T14	1		T16	555
valid_sources[0x05]	140355	1			T25	29		T12	2		T16	669
valid_sources[0x06]	56079	1			T25	2		T26	3		T12	1
valid_sources[0x07]	56998	1			T25	17		T12	1		T15	2
valid_sources[0x08]	56705	1			T25	13		T12	1		T13	2
valid_sources[0x09]	54791	1			T26	1		T13	1		T14	4
valid_sources[0x0a]	56176	1			T25	45		T26	1		T12	2
valid_sources[0x0b]	55554	1			T26	1		T12	3		T16	493
valid_sources[0x0c]	57747	1			T25	2		T26	1		T12	1
valid_sources[0x0d]	57888	1			T25	53		T26	1		T12	1
valid_sources[0x0e]	62223	1			T25	11		T12	2		T16	581
valid_sources[0x0f]	65279	1			T25	31		T14	2		T16	598
valid_sources[0x10]	54060	1			T25	69		T26	1		T12	1
valid_sources[0x11]	54094	1			T12	2		T14	1		T15	4
valid_sources[0x12]	59976	1			T25	18		T12	1		T13	2
valid_sources[0x13]	57934	1			T25	1		T12	2		T15	9
valid_sources[0x14]	52481	1			T25	7		T12	2		T14	1
valid_sources[0x15]	57233	1			T25	7		T26	1		T12	2
valid_sources[0x16]	59937	1			T25	16		T12	2		T14	1
valid_sources[0x17]	57111	1			T25	11		T15	1		T16	486
valid_sources[0x18]	54204	1			T25	10		T26	2		T12	2
valid_sources[0x19]	64211	1			T25	25		T26	2		T12	2
valid_sources[0x1a]	52107	1			T25	43		T12	2		T16	509
valid_sources[0x1b]	58981	1			T25	21		T26	1		T12	5
valid_sources[0x1c]	63066	1			T25	16		T26	2		T12	4
valid_sources[0x1d]	53491	1			T25	13		T26	1		T12	2
valid_sources[0x1e]	55264	1			T25	12		T26	1		T13	6
valid_sources[0x1f]	57658	1			T25	2		T12	3		T14	1
valid_sources[0x20]	58662	1			T26	1		T12	3		T14	3
valid_sources[0x21]	57763	1			T25	41		T26	1		T12	2
valid_sources[0x22]	54603	1			T25	14		T26	1		T13	1
valid_sources[0x23]	54918	1			T25	4		T12	2		T13	1
valid_sources[0x24]	55905	1			T26	1		T12	3		T16	433
valid_sources[0x25]	53652	1			T12	1		T15	1		T16	490
valid_sources[0x26]	53240	1			T25	9		T12	2		T16	609
valid_sources[0x27]	53702	1			T25	25		T26	1		T12	4
valid_sources[0x28]	55619	1			T12	2		T16	501		T17	2
valid_sources[0x29]	56631	1			T25	17		T12	3		T13	1
valid_sources[0x2a]	54107	1			T25	14		T12	2		T16	602
valid_sources[0x2b]	57329	1			T12	4		T16	401		T19	2
valid_sources[0x2c]	56467	1			T25	4		T12	1		T13	3
valid_sources[0x2d]	56761	1			T26	1		T13	2		T14	1
valid_sources[0x2e]	52734	1			T25	26		T12	2		T13	4
valid_sources[0x2f]	56926	1			T25	20		T12	3		T15	14
valid_sources[0x30]	87408	1			T26	2		T14	1		T16	581
valid_sources[0x31]	58485	1			T25	46		T26	1		T12	3
valid_sources[0x32]	54214	1			T25	33		T12	2		T14	1
valid_sources[0x33]	59921	1			T12	4		T14	1		T15	1
valid_sources[0x34]	58957	1			T25	18		T26	1		T12	1
valid_sources[0x35]	55298	1			T25	7		T26	1		T12	4
valid_sources[0x36]	59010	1			T16	586		T17	1		T18	4
valid_sources[0x37]	57860	1			T12	3		T14	1		T16	556
valid_sources[0x38]	53217	1			T25	2		T12	1		T16	528
valid_sources[0x39]	53069	1			T25	12		T12	2		T13	2
valid_sources[0x3a]	59534	1			T13	2		T14	1		T16	547
valid_sources[0x3b]	62335	1			T26	1		T12	2		T14	1
valid_sources[0x3c]	58715	1			T25	13		T26	1		T14	5
valid_sources[0x3d]	56933	1			T25	25		T12	1		T16	480
valid_sources[0x3e]	56149	1			T25	26		T26	1		T12	2
valid_sources[0x3f]	52433	1			T26	1		T12	5		T16	485
valid_sources[0x40]	59895	1			T26	1		T14	2		T16	578
valid_sources[0x41]	57592	1			T25	20		T16	642		T19	2
valid_sources[0x42]	137522	1			T25	2		T12	4		T13	2
valid_sources[0x43]	57148	1			T25	8		T12	4		T16	586
valid_sources[0x44]	52808	1			T25	1		T26	1		T12	5
valid_sources[0x45]	59216	1			T25	16		T26	1		T12	4
valid_sources[0x46]	53651	1			T12	1		T13	2		T14	1
valid_sources[0x47]	54797	1			T25	9		T12	3		T14	4
valid_sources[0x48]	57851	1			T25	2		T26	2		T12	2
valid_sources[0x49]	56356	1			T26	1		T12	3		T13	1
valid_sources[0x4a]	165114	1			T25	1		T12	2		T14	2
valid_sources[0x4b]	56408	1			T25	46		T12	1		T16	588
valid_sources[0x4c]	53652	1			T25	14		T12	2		T13	1
valid_sources[0x4d]	51756	1			T25	20		T13	2		T14	1
valid_sources[0x4e]	56901	1			T25	14		T12	2		T16	619
valid_sources[0x4f]	61805	1			T25	13		T26	1		T12	1
valid_sources[0x50]	59517	1			T25	20		T12	3		T16	494
valid_sources[0x51]	52755	1			T25	4		T26	2		T12	1
valid_sources[0x52]	55416	1			T25	33		T12	3		T16	567
valid_sources[0x53]	57335	1			T25	11		T26	1		T12	2
valid_sources[0x54]	56419	1			T25	8		T13	1		T14	1
valid_sources[0x55]	55350	1			T25	7		T26	2		T13	1
valid_sources[0x56]	55166	1			T25	14		T12	2		T13	2
valid_sources[0x57]	57234	1			T25	18		T14	1		T15	2
valid_sources[0x58]	57569	1			T25	4		T12	3		T16	604
valid_sources[0x59]	57101	1			T25	10		T26	1		T12	1
valid_sources[0x5a]	52602	1			T25	1		T12	2		T13	1
valid_sources[0x5b]	205363	1			T25	2		T26	4		T12	1
valid_sources[0x5c]	55780	1			T25	39		T26	1		T13	7
valid_sources[0x5d]	58648	1			T25	3		T12	2		T16	488
valid_sources[0x5e]	52904	1			T25	27		T12	5		T16	428
valid_sources[0x5f]	57272	1			T25	10		T12	3		T13	3
valid_sources[0x60]	57313	1			T25	29		T26	1		T12	4
valid_sources[0x61]	57957	1			T25	32		T26	2		T12	4
valid_sources[0x62]	55108	1			T25	13		T12	2		T14	2
valid_sources[0x63]	64935	1			T25	4		T26	1		T13	1
valid_sources[0x64]	60833	1			T25	15		T26	1		T12	2
valid_sources[0x65]	54610	1			T25	23		T12	2		T13	4
valid_sources[0x66]	58859	1			T25	15		T26	3		T12	1
valid_sources[0x67]	56021	1			T25	9		T26	1		T12	1
valid_sources[0x68]	54449	1			T25	11		T12	3		T13	2
valid_sources[0x69]	55500	1			T25	24		T12	2		T13	2
valid_sources[0x6a]	66041	1			T25	64		T13	2		T16	489
valid_sources[0x6b]	52095	1			T25	39		T12	1		T13	2
valid_sources[0x6c]	52613	1			T25	2		T26	1		T12	1
valid_sources[0x6d]	55350	1			T25	12		T12	2		T14	1
valid_sources[0x6e]	54106	1			T26	2		T12	1		T14	1
valid_sources[0x6f]	58102	1			T25	20		T12	2		T13	1
valid_sources[0x70]	53337	1			T25	6		T26	1		T16	428
valid_sources[0x71]	64070	1			T25	21		T14	1		T16	562
valid_sources[0x72]	55444	1			T25	3		T12	5		T13	1
valid_sources[0x73]	57117	1			T25	3		T12	3		T13	3
valid_sources[0x74]	56523	1			T25	1		T12	3		T15	5
valid_sources[0x75]	63652	1			T25	48		T14	3		T16	496
valid_sources[0x76]	54182	1			T25	9		T26	2		T16	707
valid_sources[0x77]	58604	1			T25	3		T16	547		T19	2
valid_sources[0x78]	52498	1			T25	22		T12	1		T13	1
valid_sources[0x79]	57044	1			T25	9		T12	1		T13	1
valid_sources[0x7a]	54301	1			T25	8		T12	1		T13	1
valid_sources[0x7b]	57055	1			T25	5		T12	3		T13	2
valid_sources[0x7c]	55912	1			T25	2		T11	4059		T14	1
valid_sources[0x7d]	56564	1			T25	26		T26	1		T12	2
valid_sources[0x7e]	53819	1			T25	22		T26	1		T12	1
valid_sources[0x7f]	55015	1			T25	20		T26	2		T12	1
valid_sources[0x80]	58249	1			T25	20		T26	1		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3538868

1

T25

1572

T26

51

T27

12

values[0x0]

all_enables

biggest_size

4522809

1

T25

211

T26

27

T27

64

values[0x1]

all_enables

biggest_size

4520440

1

T25

223

T26

27

T27

52