Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	130300681	0	0	0
ctrl_en_input_filter_rd_A	130300681	55634	0	0
intr_ctrl_en_falling_rd_A	130300681	55956	0	0
intr_ctrl_en_lvlhigh_rd_A	130300681	55600	0	0
intr_ctrl_en_lvllow_rd_A	130300681	57150	0	0
intr_ctrl_en_rising_rd_A	130300681	55563	0	0
intr_enable_rd_A	130300681	56124	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	55634	0	0
T1	51201	361	0	0
T2	0	182	0	0
T3	0	81	0	0
T4	0	117	0	0
T5	0	5394	0	0
T6	0	2304	0	0
T7	0	221	0	0
T8	0	1028	0	0
T9	0	7	0	0
T10	0	4562	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	55956	0	0
T1	51201	345	0	0
T2	0	136	0	0
T3	0	39	0	0
T4	0	174	0	0
T5	0	5327	0	0
T6	0	2297	0	0
T7	0	174	0	0
T8	0	1164	0	0
T9	0	4	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0
T20	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	55600	0	0
T1	51201	344	0	0
T2	0	183	0	0
T3	0	41	0	0
T4	0	101	0	0
T5	0	5565	0	0
T6	0	2383	0	0
T7	0	134	0	0
T8	0	999	0	0
T9	0	8	0	0
T10	0	4628	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	57150	0	0
T1	51201	330	0	0
T2	0	150	0	0
T3	0	33	0	0
T4	0	147	0	0
T5	0	5360	0	0
T6	0	2565	0	0
T7	0	133	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0
T20	0	6	0	0
T21	0	18	0	0
T22	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	55563	0	0
T1	51201	294	0	0
T2	0	165	0	0
T3	0	55	0	0
T4	0	204	0	0
T5	0	5326	0	0
T6	0	2578	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0
T20	0	2	0	0
T21	0	6	0	0
T22	0	15	0	0
T23	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130300681	56124	0	0
T1	51201	386	0	0
T2	0	188	0	0
T3	0	31	0	0
T4	0	156	0	0
T5	0	5150	0	0
T6	0	2153	0	0
T7	0	127	0	0
T11	39404	0	0	0
T12	7208	0	0	0
T13	4407	0	0	0
T14	3923	0	0	0
T15	3621	0	0	0
T16	120813	0	0	0
T17	8319	0	0	0
T18	6160	0	0	0
T19	8236	0	0	0
T20	0	8	0	0
T21	0	17	0	0
T24	0	2	0	0