Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2498230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11140117

1

T26

691

T27

290

T28

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5454000	1			T26	864		T27	61		T28	1
values[0x0]	4022279	1			T26	150		T27	106		T28	9
values[0x1]	4162068	1			T26	120		T27	148		T28	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1920676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11717671

1

T26

768

T27

291

T28

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50818	1			T26	4		T31	11		T32	581
valid_sources[0x01]	56913	1			T26	5		T31	20		T32	547
valid_sources[0x02]	46675	1			T27	1		T31	15		T32	539
valid_sources[0x03]	51422	1			T31	21		T32	555		T33	8
valid_sources[0x04]	45592	1			T27	2		T31	20		T32	572
valid_sources[0x05]	41742	1			T27	2		T31	24		T32	554
valid_sources[0x06]	54947	1			T26	2		T31	14		T32	523
valid_sources[0x07]	46403	1			T26	2		T31	15		T32	613
valid_sources[0x08]	48073	1			T26	7		T31	22		T32	588
valid_sources[0x09]	46133	1			T26	5		T31	13		T32	596
valid_sources[0x0a]	48511	1			T26	1		T27	1		T31	20
valid_sources[0x0b]	47005	1			T26	2		T31	18		T32	576
valid_sources[0x0c]	56679	1			T26	14		T31	14		T32	546
valid_sources[0x0d]	50988	1			T26	4		T27	2		T31	15
valid_sources[0x0e]	55660	1			T27	5		T31	13		T32	561
valid_sources[0x0f]	55486	1			T26	4		T27	4		T31	20
valid_sources[0x10]	46675	1			T26	1		T27	7		T31	19
valid_sources[0x11]	50554	1			T26	4		T27	7		T31	10
valid_sources[0x12]	54381	1			T27	2		T31	20		T32	586
valid_sources[0x13]	45828	1			T26	8		T27	3		T31	11
valid_sources[0x14]	46244	1			T26	2		T31	17		T32	571
valid_sources[0x15]	49183	1			T27	4		T31	16		T32	575
valid_sources[0x16]	45156	1			T26	3		T27	1		T31	21
valid_sources[0x17]	46757	1			T31	20		T32	532		T33	3
valid_sources[0x18]	54720	1			T27	2		T31	11		T32	549
valid_sources[0x19]	47660	1			T26	6		T31	18		T32	543
valid_sources[0x1a]	48680	1			T31	16		T32	576		T33	6
valid_sources[0x1b]	46594	1			T26	6		T27	3		T31	8
valid_sources[0x1c]	47630	1			T26	5		T27	1		T31	21
valid_sources[0x1d]	53947	1			T26	5		T27	1		T31	22
valid_sources[0x1e]	50827	1			T27	1		T31	16		T32	583
valid_sources[0x1f]	46777	1			T27	8		T29	3		T31	14
valid_sources[0x20]	42090	1			T27	2		T31	23		T32	529
valid_sources[0x21]	54489	1			T26	2		T27	1		T31	13
valid_sources[0x22]	114785	1			T26	5		T31	19		T32	589
valid_sources[0x23]	54375	1			T26	1		T31	15		T32	511
valid_sources[0x24]	46561	1			T26	11		T27	4		T31	20
valid_sources[0x25]	66898	1			T27	3		T31	12		T32	577
valid_sources[0x26]	58449	1			T26	4		T31	11		T32	581
valid_sources[0x27]	46002	1			T26	8		T27	1		T31	27
valid_sources[0x28]	42729	1			T31	15		T32	573		T33	14
valid_sources[0x29]	51195	1			T27	1		T31	23		T32	551
valid_sources[0x2a]	50287	1			T27	3		T31	13		T32	547
valid_sources[0x2b]	54299	1			T31	11		T32	600		T33	17
valid_sources[0x2c]	123316	1			T26	3		T31	16		T32	569
valid_sources[0x2d]	60749	1			T27	3		T31	11		T32	565
valid_sources[0x2e]	40000	1			T26	12		T31	14		T32	607
valid_sources[0x2f]	45424	1			T26	14		T27	3		T31	22
valid_sources[0x30]	42909	1			T26	10		T31	22		T32	539
valid_sources[0x31]	49989	1			T26	6		T29	3		T31	16
valid_sources[0x32]	51074	1			T26	11		T31	15		T32	531
valid_sources[0x33]	40027	1			T26	9		T27	1		T31	24
valid_sources[0x34]	56304	1			T26	3		T27	3		T31	18
valid_sources[0x35]	46296	1			T26	6		T31	22		T32	580
valid_sources[0x36]	43521	1			T27	4		T31	19		T32	563
valid_sources[0x37]	50774	1			T26	15		T27	1		T31	15
valid_sources[0x38]	152938	1			T27	2		T31	20		T32	579
valid_sources[0x39]	44512	1			T27	1		T31	24		T32	521
valid_sources[0x3a]	48960	1			T27	1		T31	20		T32	539
valid_sources[0x3b]	40662	1			T27	2		T31	15		T32	590
valid_sources[0x3c]	45825	1			T27	2		T31	19		T32	580
valid_sources[0x3d]	50051	1			T26	1		T27	2		T31	19
valid_sources[0x3e]	44955	1			T26	4		T31	11		T32	611
valid_sources[0x3f]	48693	1			T26	4		T27	1		T31	21
valid_sources[0x40]	57662	1			T26	12		T31	17		T32	578
valid_sources[0x41]	43373	1			T26	3		T31	14		T32	565
valid_sources[0x42]	47008	1			T26	3		T27	4		T31	18
valid_sources[0x43]	46404	1			T26	25		T31	14		T32	536
valid_sources[0x44]	44549	1			T26	12		T31	14		T32	566
valid_sources[0x45]	45395	1			T26	6		T27	1		T31	18
valid_sources[0x46]	45778	1			T26	5		T31	15		T32	595
valid_sources[0x47]	50588	1			T27	1		T31	17		T32	562
valid_sources[0x48]	52794	1			T26	10		T27	3		T31	22
valid_sources[0x49]	51283	1			T26	11		T27	2		T31	9
valid_sources[0x4a]	48983	1			T27	1		T31	11		T32	566
valid_sources[0x4b]	49787	1			T26	3		T27	1		T31	17
valid_sources[0x4c]	42351	1			T26	2		T31	22		T32	583
valid_sources[0x4d]	44753	1			T31	18		T32	554		T33	8
valid_sources[0x4e]	41462	1			T26	4		T27	3		T31	15
valid_sources[0x4f]	45693	1			T26	5		T27	1		T31	19
valid_sources[0x50]	46014	1			T26	9		T27	1		T31	19
valid_sources[0x51]	43185	1			T27	2		T31	13		T32	495
valid_sources[0x52]	50254	1			T26	1		T27	1		T31	18
valid_sources[0x53]	49737	1			T27	4		T31	15		T32	573
valid_sources[0x54]	91386	1			T26	4		T31	18		T32	578
valid_sources[0x55]	58090	1			T27	1		T31	15		T32	604
valid_sources[0x56]	58879	1			T27	3		T31	28		T32	575
valid_sources[0x57]	43206	1			T31	16		T32	566		T33	15
valid_sources[0x58]	107503	1			T26	3		T27	3		T31	9
valid_sources[0x59]	40856	1			T26	5		T31	12		T32	540
valid_sources[0x5a]	41655	1			T26	6		T31	17		T32	598
valid_sources[0x5b]	42867	1			T27	1		T31	12		T32	546
valid_sources[0x5c]	43396	1			T26	10		T27	1		T31	10
valid_sources[0x5d]	48400	1			T26	4		T31	21		T32	567
valid_sources[0x5e]	167651	1			T27	1		T31	15		T32	585
valid_sources[0x5f]	51992	1			T26	3		T31	18		T32	536
valid_sources[0x60]	49551	1			T26	9		T31	12		T32	535
valid_sources[0x61]	41263	1			T26	8		T27	4		T31	16
valid_sources[0x62]	37803	1			T26	16		T31	19		T32	551
valid_sources[0x63]	46523	1			T26	6		T31	15		T32	533
valid_sources[0x64]	47537	1			T27	2		T31	22		T32	555
valid_sources[0x65]	45430	1			T31	20		T32	586		T33	8
valid_sources[0x66]	46174	1			T26	1		T31	18		T32	529
valid_sources[0x67]	54348	1			T26	2		T27	1		T31	22
valid_sources[0x68]	44974	1			T26	8		T27	7		T31	23
valid_sources[0x69]	148818	1			T26	9		T31	14		T32	560
valid_sources[0x6a]	41938	1			T26	2		T27	2		T31	10
valid_sources[0x6b]	53117	1			T31	13		T32	574		T33	8
valid_sources[0x6c]	45680	1			T26	4		T27	1		T31	21
valid_sources[0x6d]	47508	1			T26	8		T27	3		T31	23
valid_sources[0x6e]	47732	1			T31	18		T32	573		T33	6
valid_sources[0x6f]	57792	1			T26	1		T27	1		T31	12
valid_sources[0x70]	45811	1			T31	11		T32	558		T33	13
valid_sources[0x71]	49415	1			T26	4		T27	2		T31	14
valid_sources[0x72]	95738	1			T31	23		T32	568		T33	4
valid_sources[0x73]	45473	1			T31	14		T32	541		T33	15
valid_sources[0x74]	40664	1			T27	1		T31	20		T32	532
valid_sources[0x75]	39272	1			T26	9		T27	7		T31	17
valid_sources[0x76]	69420	1			T26	2		T27	7		T30	504
valid_sources[0x77]	52735	1			T26	10		T31	16		T32	575
valid_sources[0x78]	48040	1			T27	1		T31	19		T32	571
valid_sources[0x79]	53457	1			T26	12		T27	2		T31	19
valid_sources[0x7a]	61943	1			T26	6		T27	2		T31	19
valid_sources[0x7b]	45548	1			T26	2		T27	4		T31	15
valid_sources[0x7c]	48491	1			T26	1		T27	3		T31	10
valid_sources[0x7d]	47171	1			T26	4		T27	3		T31	26
valid_sources[0x7e]	53350	1			T26	12		T27	1		T31	16
valid_sources[0x7f]	50108	1			T26	2		T27	1		T31	16
valid_sources[0x80]	52688	1			T26	1		T27	2		T31	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3124508

1

T26

421

T27

36

T28

1

values[0x0]

all_enables

biggest_size

4007979

1

T26

150

T27

106

T28

1

values[0x1]

all_enables

biggest_size

4007630

1

T26

120

T27

148

T28

2