Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123391485	0	0	0
ctrl_en_input_filter_rd_A	123391485	47913	0	0
intr_ctrl_en_falling_rd_A	123391485	49253	0	0
intr_ctrl_en_lvlhigh_rd_A	123391485	47059	0	0
intr_ctrl_en_lvllow_rd_A	123391485	47699	0	0
intr_ctrl_en_rising_rd_A	123391485	48087	0	0
intr_enable_rd_A	123391485	47747	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	47913	0	0
T1	104227	1792	0	0
T2	0	14039	0	0
T3	0	119	0	0
T4	0	6	0	0
T5	0	3	0	0
T6	0	2890	0	0
T7	0	6671	0	0
T8	0	72	0	0
T9	0	191	0	0
T10	0	279	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	49253	0	0
T1	104227	1760	0	0
T2	0	15358	0	0
T3	0	184	0	0
T6	0	2801	0	0
T7	0	6680	0	0
T8	0	127	0	0
T9	0	110	0	0
T10	0	288	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0
T20	0	2	0	0
T21	0	47	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	47059	0	0
T1	104227	1894	0	0
T2	0	14268	0	0
T3	0	203	0	0
T5	0	1	0	0
T6	0	2954	0	0
T7	0	6256	0	0
T8	0	113	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0
T20	0	5	0	0
T22	0	5	0	0
T23	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	47699	0	0
T1	104227	1718	0	0
T2	0	14631	0	0
T3	0	158	0	0
T4	0	16	0	0
T6	0	2734	0	0
T7	0	6281	0	0
T8	0	142	0	0
T9	0	103	0	0
T10	0	335	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0
T23	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	48087	0	0
T1	104227	1868	0	0
T2	0	14267	0	0
T3	0	172	0	0
T6	0	3022	0	0
T7	0	6717	0	0
T8	0	125	0	0
T9	0	92	0	0
T10	0	271	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0
T21	0	64	0	0
T24	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123391485	47747	0	0
T1	104227	1715	0	0
T2	0	14258	0	0
T3	0	195	0	0
T6	0	2839	0	0
T7	0	6516	0	0
T8	0	96	0	0
T9	0	175	0	0
T10	0	298	0	0
T11	13717	0	0	0
T12	3349	0	0	0
T13	3505	0	0	0
T14	2203	0	0	0
T15	2660	0	0	0
T16	3177	0	0	0
T17	532647	0	0	0
T18	2124	0	0	0
T19	8741	0	0	0
T21	0	40	0	0
T25	0	731	0	0