Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	190669126	0	0	0
ctrl_en_input_filter_rd_A	190669126	68530	0	0
intr_ctrl_en_falling_rd_A	190669126	70902	0	0
intr_ctrl_en_lvlhigh_rd_A	190669126	67030	0	0
intr_ctrl_en_lvllow_rd_A	190669126	71587	0	0
intr_ctrl_en_rising_rd_A	190669126	67987	0	0
intr_enable_rd_A	190669126	68743	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	68530	0	0
T1	486478	1350	0	0
T2	671057	26066	0	0
T3	0	560	0	0
T4	0	157	0	0
T5	0	8033	0	0
T6	0	250	0	0
T7	0	37	0	0
T8	0	371	0	0
T9	0	908	0	0
T10	0	133	0	0
T11	8011	0	0	0
T12	1108	0	0	0
T13	6000	0	0	0
T14	2971	0	0	0
T15	4641	0	0	0
T16	3478	0	0	0
T17	4295	0	0	0
T18	2492	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	70902	0	0
T1	486478	1481	0	0
T2	671057	29407	0	0
T3	0	596	0	0
T4	0	125	0	0
T5	0	8262	0	0
T6	0	210	0	0
T7	0	51	0	0
T8	0	270	0	0
T9	0	895	0	0
T11	8011	0	0	0
T12	1108	0	0	0
T13	6000	0	0	0
T14	2971	0	0	0
T15	4641	0	0	0
T16	3478	0	0	0
T17	4295	0	0	0
T18	2492	0	0	0
T19	0	6	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	67030	0	0
T1	0	1443	0	0
T2	0	26022	0	0
T3	0	538	0	0
T4	0	141	0	0
T5	0	7961	0	0
T6	0	180	0	0
T7	0	66	0	0
T8	0	274	0	0
T20	5824	8	0	0
T21	0	5	0	0
T22	2212	0	0	0
T23	345548	0	0	0
T24	6047	0	0	0
T25	4032	0	0	0
T26	3049	0	0	0
T27	2997	0	0	0
T28	7801	0	0	0
T29	8171	0	0	0
T30	107625	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	71587	0	0
T1	0	1325	0	0
T2	0	29283	0	0
T3	0	564	0	0
T4	0	132	0	0
T5	0	8182	0	0
T6	0	247	0	0
T7	0	46	0	0
T8	0	281	0	0
T9	0	1041	0	0
T20	5824	9	0	0
T22	2212	0	0	0
T23	345548	0	0	0
T24	6047	0	0	0
T25	4032	0	0	0
T26	3049	0	0	0
T27	2997	0	0	0
T28	7801	0	0	0
T29	8171	0	0	0
T30	107625	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	67987	0	0
T1	0	1325	0	0
T2	0	26395	0	0
T3	0	681	0	0
T4	0	116	0	0
T5	0	8117	0	0
T6	0	224	0	0
T7	0	29	0	0
T8	0	294	0	0
T9	0	865	0	0
T20	5824	5	0	0
T22	2212	0	0	0
T23	345548	0	0	0
T24	6047	0	0	0
T25	4032	0	0	0
T26	3049	0	0	0
T27	2997	0	0	0
T28	7801	0	0	0
T29	8171	0	0	0
T30	107625	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190669126	68743	0	0
T1	486478	1347	0	0
T2	671057	26353	0	0
T3	0	605	0	0
T4	0	123	0	0
T5	0	8458	0	0
T6	0	258	0	0
T7	0	73	0	0
T8	0	262	0	0
T9	0	959	0	0
T11	8011	0	0	0
T12	1108	0	0	0
T13	6000	0	0	0
T14	2971	0	0	0
T15	4641	0	0	0
T16	3478	0	0	0
T17	4295	0	0	0
T18	2492	0	0	0
T21	0	2	0	0