Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3653700 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 15996025 1 T22 3 T23 299 T24 100911



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7916428 1 T22 1 T23 62 T24 57015
values[0x0] 5771535 1 T22 8 T23 134 T24 36200
values[0x1] 5961762 1 T22 10 T23 131 T24 36197



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2817328 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 16832397 1 T22 5 T23 304 T24 106496



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 76566 1 T23 2 T24 475 T25 3
valid_sources[0x01] 75822 1 T22 2 T24 496 T29 5195
valid_sources[0x02] 74688 1 T24 538 T25 1 T29 5292
valid_sources[0x03] 68651 1 T23 1 T24 494 T29 5317
valid_sources[0x04] 73802 1 T23 1 T24 508 T25 1
valid_sources[0x05] 72686 1 T24 557 T29 5066 T30 8
valid_sources[0x06] 71042 1 T23 1 T24 580 T29 5224
valid_sources[0x07] 59481 1 T23 2 T24 421 T28 1
valid_sources[0x08] 70056 1 T23 3 T24 520 T29 5052
valid_sources[0x09] 65771 1 T23 2 T24 508 T29 5054
valid_sources[0x0a] 62631 1 T24 514 T29 4982 T11 11
valid_sources[0x0b] 85971 1 T23 3 T24 542 T29 5089
valid_sources[0x0c] 79377 1 T23 3 T24 473 T29 5233
valid_sources[0x0d] 68997 1 T23 1 T24 468 T29 5100
valid_sources[0x0e] 62567 1 T23 2 T24 489 T29 5420
valid_sources[0x0f] 74506 1 T23 4 T24 478 T29 5039
valid_sources[0x10] 80757 1 T23 5 T24 471 T29 5117
valid_sources[0x11] 64577 1 T23 3 T24 489 T29 5191
valid_sources[0x12] 68415 1 T23 4 T24 506 T29 5066
valid_sources[0x13] 61413 1 T24 456 T29 5065 T11 16
valid_sources[0x14] 65145 1 T24 468 T29 5310 T11 12
valid_sources[0x15] 67673 1 T24 455 T29 5193 T11 16
valid_sources[0x16] 236685 1 T23 4 T24 497 T29 5212
valid_sources[0x17] 75208 1 T24 439 T25 1 T28 1
valid_sources[0x18] 69923 1 T23 2 T24 493 T29 5196
valid_sources[0x19] 82121 1 T23 2 T24 539 T29 5431
valid_sources[0x1a] 68616 1 T24 461 T25 1 T29 5334
valid_sources[0x1b] 77531 1 T24 450 T29 5375 T30 10
valid_sources[0x1c] 67828 1 T24 463 T29 5108 T11 5
valid_sources[0x1d] 65480 1 T23 2 T24 545 T29 5240
valid_sources[0x1e] 77918 1 T22 3 T23 2 T24 451
valid_sources[0x1f] 76325 1 T23 3 T24 484 T25 1
valid_sources[0x20] 70576 1 T23 2 T24 477 T29 5277
valid_sources[0x21] 77449 1 T23 2 T24 475 T29 5207
valid_sources[0x22] 74711 1 T24 509 T25 5 T29 5223
valid_sources[0x23] 72187 1 T23 2 T24 537 T25 1
valid_sources[0x24] 76763 1 T23 3 T24 502 T29 5310
valid_sources[0x25] 69558 1 T23 1 T24 482 T25 1
valid_sources[0x26] 66568 1 T23 3 T24 478 T25 2
valid_sources[0x27] 67561 1 T23 4 T24 564 T29 5135
valid_sources[0x28] 69055 1 T23 2 T24 485 T29 5324
valid_sources[0x29] 73504 1 T23 2 T24 524 T29 5359
valid_sources[0x2a] 71315 1 T24 528 T29 5291 T11 9
valid_sources[0x2b] 75780 1 T23 2 T24 536 T29 5210
valid_sources[0x2c] 79457 1 T23 2 T24 493 T29 5455
valid_sources[0x2d] 68884 1 T24 509 T29 5167 T11 15
valid_sources[0x2e] 63868 1 T24 501 T29 5347 T11 12
valid_sources[0x2f] 69542 1 T23 2 T24 468 T25 4
valid_sources[0x30] 77506 1 T24 437 T29 5030 T30 11
valid_sources[0x31] 74763 1 T23 2 T24 492 T28 1
valid_sources[0x32] 76891 1 T23 2 T24 468 T29 5133
valid_sources[0x33] 78051 1 T24 466 T29 5285 T11 6
valid_sources[0x34] 75045 1 T23 1 T24 509 T29 5128
valid_sources[0x35] 69897 1 T24 522 T29 5068 T30 7
valid_sources[0x36] 75723 1 T24 467 T29 5203 T11 13
valid_sources[0x37] 61490 1 T23 1 T24 490 T29 5128
valid_sources[0x38] 97807 1 T23 4 T24 533 T25 2
valid_sources[0x39] 62718 1 T23 2 T24 606 T29 5209
valid_sources[0x3a] 70003 1 T23 1 T24 513 T29 5284
valid_sources[0x3b] 76391 1 T23 4 T24 475 T29 5400
valid_sources[0x3c] 68480 1 T24 462 T29 5311 T11 22
valid_sources[0x3d] 68248 1 T24 566 T29 5303 T11 11
valid_sources[0x3e] 71815 1 T24 475 T29 5205 T11 12
valid_sources[0x3f] 74571 1 T23 2 T24 542 T29 5135
valid_sources[0x40] 73674 1 T23 2 T24 506 T29 5344
valid_sources[0x41] 72336 1 T22 5 T23 1 T24 539
valid_sources[0x42] 68203 1 T23 4 T24 460 T25 2
valid_sources[0x43] 77226 1 T23 2 T24 489 T29 5113
valid_sources[0x44] 64061 1 T23 1 T24 494 T29 5205
valid_sources[0x45] 64482 1 T23 2 T24 478 T29 5146
valid_sources[0x46] 165852 1 T23 2 T24 483 T25 1
valid_sources[0x47] 64907 1 T23 3 T24 496 T29 5216
valid_sources[0x48] 75551 1 T23 3 T24 503 T25 1
valid_sources[0x49] 67523 1 T22 1 T24 529 T29 5271
valid_sources[0x4a] 72045 1 T23 1 T24 538 T29 5260
valid_sources[0x4b] 80013 1 T22 1 T23 1 T24 523
valid_sources[0x4c] 70158 1 T23 1 T24 551 T29 5074
valid_sources[0x4d] 73388 1 T23 3 T24 441 T29 5164
valid_sources[0x4e] 61210 1 T24 615 T29 5237 T11 14
valid_sources[0x4f] 64202 1 T23 2 T24 520 T29 5177
valid_sources[0x50] 77294 1 T23 1 T24 474 T29 5147
valid_sources[0x51] 101285 1 T23 2 T24 514 T29 5361
valid_sources[0x52] 75608 1 T23 3 T24 427 T27 42
valid_sources[0x53] 66147 1 T24 530 T29 5047 T11 15
valid_sources[0x54] 75161 1 T23 1 T24 561 T29 5209
valid_sources[0x55] 73316 1 T23 1 T24 499 T29 4945
valid_sources[0x56] 67907 1 T23 4 T24 512 T29 5473
valid_sources[0x57] 77376 1 T23 4 T24 442 T29 5170
valid_sources[0x58] 84704 1 T23 1 T24 511 T29 5188
valid_sources[0x59] 66374 1 T24 569 T25 1 T29 5239
valid_sources[0x5a] 73444 1 T23 1 T24 483 T29 5128
valid_sources[0x5b] 70219 1 T24 488 T29 5030 T11 13
valid_sources[0x5c] 64916 1 T24 452 T29 5132 T11 13
valid_sources[0x5d] 72980 1 T23 5 T24 483 T29 5179
valid_sources[0x5e] 77658 1 T23 2 T24 531 T29 5173
valid_sources[0x5f] 68469 1 T23 3 T24 534 T29 5196
valid_sources[0x60] 79870 1 T23 2 T24 540 T29 5370
valid_sources[0x61] 67251 1 T23 1 T24 484 T29 5085
valid_sources[0x62] 69751 1 T23 2 T24 514 T25 1
valid_sources[0x63] 72347 1 T23 1 T24 511 T29 5255
valid_sources[0x64] 67374 1 T23 1 T24 511 T25 1
valid_sources[0x65] 67192 1 T24 500 T29 5310 T11 9
valid_sources[0x66] 74278 1 T23 1 T24 482 T29 5385
valid_sources[0x67] 74041 1 T24 552 T25 2 T29 5344
valid_sources[0x68] 66954 1 T23 1 T24 547 T25 3
valid_sources[0x69] 73680 1 T23 3 T24 556 T29 5118
valid_sources[0x6a] 73360 1 T24 564 T29 5170 T11 22
valid_sources[0x6b] 72444 1 T23 3 T24 581 T29 5355
valid_sources[0x6c] 70933 1 T24 511 T26 440 T29 5325
valid_sources[0x6d] 79510 1 T23 1 T24 546 T29 5125
valid_sources[0x6e] 73125 1 T24 538 T29 5286 T11 8
valid_sources[0x6f] 68226 1 T24 554 T29 5260 T11 15
valid_sources[0x70] 65888 1 T24 492 T25 1 T29 5122
valid_sources[0x71] 77762 1 T23 3 T24 477 T29 5113
valid_sources[0x72] 68446 1 T23 2 T24 493 T29 5159
valid_sources[0x73] 211923 1 T23 2 T24 529 T29 5192
valid_sources[0x74] 65054 1 T23 1 T24 518 T25 1
valid_sources[0x75] 64676 1 T23 1 T24 516 T29 5303
valid_sources[0x76] 74169 1 T23 1 T24 464 T29 5101
valid_sources[0x77] 74293 1 T24 514 T29 5149 T11 7
valid_sources[0x78] 80814 1 T23 1 T24 529 T29 5095
valid_sources[0x79] 68311 1 T23 2 T24 565 T29 5180
valid_sources[0x7a] 75567 1 T23 1 T24 510 T29 4953
valid_sources[0x7b] 68516 1 T23 2 T24 495 T25 6
valid_sources[0x7c] 61896 1 T23 2 T24 528 T29 5262
valid_sources[0x7d] 64851 1 T23 1 T24 495 T29 5405
valid_sources[0x7e] 187605 1 T23 1 T24 531 T25 1
valid_sources[0x7f] 69929 1 T23 1 T24 526 T29 5419
valid_sources[0x80] 225312 1 T23 1 T24 430 T25 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 4491099 1 T22 1 T23 34 T24 28514
values[0x0] all_enables biggest_size 5752457 1 T22 2 T23 134 T24 36200
values[0x1] all_enables biggest_size 5752469 1 T23 131 T24 36197 T25 21

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%