Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153304133	0	0	0
ctrl_en_input_filter_rd_A	153304133	40196	0	0
intr_ctrl_en_falling_rd_A	153304133	39135	0	0
intr_ctrl_en_lvlhigh_rd_A	153304133	39191	0	0
intr_ctrl_en_lvllow_rd_A	153304133	38666	0	0
intr_ctrl_en_rising_rd_A	153304133	38723	0	0
intr_enable_rd_A	153304133	38725	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	40196	0	0
T1	35438	208	0	0
T2	0	192	0	0
T3	0	202	0	0
T4	0	943	0	0
T5	0	2892	0	0
T6	0	1910	0	0
T7	0	139	0	0
T8	0	234	0	0
T9	0	136	0	0
T10	0	5137	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	39135	0	0
T1	35438	166	0	0
T2	0	148	0	0
T3	0	111	0	0
T4	0	1003	0	0
T5	0	2694	0	0
T6	0	1830	0	0
T7	0	127	0	0
T8	0	140	0	0
T9	0	184	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0
T20	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	39191	0	0
T1	35438	118	0	0
T2	0	139	0	0
T3	0	180	0	0
T4	0	1043	0	0
T5	0	2765	0	0
T6	0	1775	0	0
T7	0	138	0	0
T8	0	185	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0
T20	0	3	0	0
T21	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	38666	0	0
T1	35438	131	0	0
T2	0	136	0	0
T3	0	159	0	0
T4	0	814	0	0
T5	0	2969	0	0
T6	0	1785	0	0
T7	0	104	0	0
T8	0	209	0	0
T9	0	150	0	0
T10	0	5065	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	38723	0	0
T1	35438	151	0	0
T2	0	132	0	0
T3	0	156	0	0
T4	0	877	0	0
T5	0	2730	0	0
T6	0	1836	0	0
T7	0	127	0	0
T8	0	186	0	0
T9	0	199	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0
T21	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153304133	38725	0	0
T1	35438	169	0	0
T2	0	182	0	0
T3	0	134	0	0
T4	0	800	0	0
T5	0	2789	0	0
T6	0	1671	0	0
T7	0	142	0	0
T8	0	160	0	0
T9	0	163	0	0
T10	0	4774	0	0
T11	8096	0	0	0
T12	5869	0	0	0
T13	46929	0	0	0
T14	2145	0	0	0
T15	6038	0	0	0
T16	3566	0	0	0
T17	63682	0	0	0
T18	780269	0	0	0
T19	1395	0	0	0