Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2801876	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12379777

1

T31

2017

T32

2515

T33

101984

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6097364	1			T31	3120		T32	3882		T33	60432
values[0x0]	4468900	1			T31	242		T32	300		T33	36044
values[0x1]	4615389	1			T31	220		T32	292		T33	35739

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2158680	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13022973

1

T31

2343

T32

2909

T33

108020

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51240	1			T31	18		T32	14		T33	579
valid_sources[0x01]	54427	1			T31	17		T32	9		T33	613
valid_sources[0x02]	55637	1			T31	6		T32	35		T33	525
valid_sources[0x03]	60783	1			T31	16		T32	17		T33	453
valid_sources[0x04]	53959	1			T31	13		T32	6		T33	420
valid_sources[0x05]	58715	1			T31	11		T32	6		T33	397
valid_sources[0x06]	57026	1			T31	18		T33	339		T14	5
valid_sources[0x07]	53111	1			T31	12		T32	1		T33	643
valid_sources[0x08]	57487	1			T31	6		T32	21		T33	584
valid_sources[0x09]	55568	1			T31	11		T33	586		T14	6
valid_sources[0x0a]	60988	1			T31	17		T33	663		T14	6
valid_sources[0x0b]	56830	1			T31	16		T33	468		T14	2
valid_sources[0x0c]	55977	1			T31	16		T32	6		T33	802
valid_sources[0x0d]	57972	1			T31	14		T32	14		T33	449
valid_sources[0x0e]	59981	1			T31	15		T32	16		T33	434
valid_sources[0x0f]	63390	1			T31	13		T33	394		T14	6
valid_sources[0x10]	52092	1			T31	17		T32	7		T33	393
valid_sources[0x11]	56865	1			T31	10		T32	7		T33	371
valid_sources[0x12]	141897	1			T31	8		T32	12		T33	655
valid_sources[0x13]	56706	1			T31	12		T33	573		T14	12
valid_sources[0x14]	52786	1			T31	10		T32	2		T33	526
valid_sources[0x15]	52811	1			T31	7		T32	9		T33	549
valid_sources[0x16]	51263	1			T31	11		T32	9		T33	462
valid_sources[0x17]	57570	1			T31	11		T32	67		T33	413
valid_sources[0x18]	51474	1			T31	15		T32	30		T33	655
valid_sources[0x19]	53431	1			T31	14		T32	32		T33	442
valid_sources[0x1a]	126485	1			T31	11		T32	16		T33	549
valid_sources[0x1b]	55087	1			T31	14		T32	5		T33	637
valid_sources[0x1c]	54453	1			T31	16		T32	29		T33	532
valid_sources[0x1d]	49659	1			T31	13		T32	41		T33	545
valid_sources[0x1e]	63906	1			T31	8		T32	1		T33	383
valid_sources[0x1f]	66535	1			T31	13		T32	10		T33	598
valid_sources[0x20]	55068	1			T31	13		T32	9		T33	455
valid_sources[0x21]	56288	1			T31	10		T32	24		T33	611
valid_sources[0x22]	89991	1			T31	14		T32	4		T33	355
valid_sources[0x23]	49959	1			T31	11		T32	5		T33	647
valid_sources[0x24]	50784	1			T31	10		T32	9		T33	448
valid_sources[0x25]	50699	1			T31	7		T32	48		T33	492
valid_sources[0x26]	58600	1			T31	11		T32	3		T33	394
valid_sources[0x27]	53983	1			T31	18		T32	6		T33	409
valid_sources[0x28]	54974	1			T31	13		T32	13		T33	568
valid_sources[0x29]	50189	1			T31	11		T32	30		T33	526
valid_sources[0x2a]	56348	1			T31	8		T32	2		T33	524
valid_sources[0x2b]	49883	1			T31	18		T32	54		T33	580
valid_sources[0x2c]	56906	1			T31	14		T32	10		T33	513
valid_sources[0x2d]	54605	1			T31	10		T33	331		T34	2
valid_sources[0x2e]	56029	1			T31	10		T32	51		T33	702
valid_sources[0x2f]	55941	1			T31	25		T32	55		T33	588
valid_sources[0x30]	55325	1			T31	13		T32	34		T33	637
valid_sources[0x31]	52526	1			T31	11		T32	2		T33	581
valid_sources[0x32]	55420	1			T31	10		T33	663		T34	3
valid_sources[0x33]	61566	1			T31	17		T32	28		T33	280
valid_sources[0x34]	51254	1			T31	11		T32	11		T33	509
valid_sources[0x35]	52536	1			T31	15		T32	17		T33	509
valid_sources[0x36]	51670	1			T31	14		T32	18		T33	633
valid_sources[0x37]	53477	1			T31	14		T32	11		T33	304
valid_sources[0x38]	52195	1			T31	13		T32	30		T33	620
valid_sources[0x39]	65537	1			T31	10		T32	17		T33	435
valid_sources[0x3a]	57800	1			T31	10		T32	20		T33	323
valid_sources[0x3b]	52543	1			T31	27		T32	29		T33	629
valid_sources[0x3c]	49754	1			T31	11		T32	11		T33	488
valid_sources[0x3d]	54113	1			T31	12		T32	3		T33	424
valid_sources[0x3e]	55054	1			T31	13		T32	40		T33	461
valid_sources[0x3f]	57899	1			T31	18		T32	6		T33	378
valid_sources[0x40]	62267	1			T31	8		T32	13		T33	532
valid_sources[0x41]	57554	1			T31	14		T33	568		T14	12
valid_sources[0x42]	54820	1			T31	14		T32	6		T33	507
valid_sources[0x43]	60552	1			T31	21		T32	29		T33	590
valid_sources[0x44]	57093	1			T31	13		T32	1		T33	618
valid_sources[0x45]	53198	1			T31	20		T32	14		T33	521
valid_sources[0x46]	64557	1			T31	11		T32	3		T33	304
valid_sources[0x47]	56245	1			T31	10		T32	23		T33	605
valid_sources[0x48]	60147	1			T31	13		T32	48		T33	386
valid_sources[0x49]	57018	1			T31	25		T32	2		T33	740
valid_sources[0x4a]	56942	1			T31	10		T32	2		T33	369
valid_sources[0x4b]	52152	1			T31	15		T32	27		T33	502
valid_sources[0x4c]	58982	1			T31	8		T32	24		T33	589
valid_sources[0x4d]	58826	1			T31	13		T32	45		T33	463
valid_sources[0x4e]	56959	1			T31	9		T32	31		T33	398
valid_sources[0x4f]	53550	1			T31	18		T32	5		T33	602
valid_sources[0x50]	56117	1			T31	13		T32	8		T33	714
valid_sources[0x51]	49914	1			T31	22		T32	32		T33	489
valid_sources[0x52]	51382	1			T31	7		T33	668		T34	2
valid_sources[0x53]	54916	1			T31	15		T32	35		T33	375
valid_sources[0x54]	64536	1			T31	23		T32	26		T33	626
valid_sources[0x55]	51352	1			T31	15		T33	373		T34	3
valid_sources[0x56]	55700	1			T31	7		T32	27		T33	468
valid_sources[0x57]	70986	1			T31	14		T32	15		T33	526
valid_sources[0x58]	50615	1			T31	16		T32	79		T33	511
valid_sources[0x59]	54637	1			T31	10		T32	69		T33	383
valid_sources[0x5a]	56690	1			T31	8		T32	31		T33	482
valid_sources[0x5b]	47237	1			T31	9		T32	6		T33	413
valid_sources[0x5c]	51793	1			T31	14		T32	24		T33	535
valid_sources[0x5d]	60931	1			T31	17		T32	1		T33	432
valid_sources[0x5e]	65637	1			T31	19		T32	4		T33	441
valid_sources[0x5f]	57415	1			T31	17		T32	10		T33	565
valid_sources[0x60]	54948	1			T31	6		T32	7		T33	459
valid_sources[0x61]	59793	1			T31	18		T33	611		T34	2
valid_sources[0x62]	54117	1			T31	9		T32	33		T33	431
valid_sources[0x63]	65421	1			T31	19		T32	1		T33	520
valid_sources[0x64]	52120	1			T31	11		T32	22		T33	611
valid_sources[0x65]	56872	1			T31	11		T32	23		T33	555
valid_sources[0x66]	55965	1			T31	26		T32	13		T33	437
valid_sources[0x67]	63561	1			T31	18		T33	498		T14	14
valid_sources[0x68]	58010	1			T31	7		T32	22		T33	525
valid_sources[0x69]	53636	1			T31	14		T33	625		T34	4
valid_sources[0x6a]	53776	1			T31	10		T32	30		T33	527
valid_sources[0x6b]	57383	1			T31	15		T32	9		T33	459
valid_sources[0x6c]	52891	1			T31	12		T32	35		T33	443
valid_sources[0x6d]	53157	1			T31	21		T32	4		T33	369
valid_sources[0x6e]	60395	1			T31	8		T32	14		T33	393
valid_sources[0x6f]	54005	1			T31	15		T32	23		T33	610
valid_sources[0x70]	52174	1			T31	17		T32	3		T33	570
valid_sources[0x71]	58725	1			T31	22		T32	30		T33	513
valid_sources[0x72]	52055	1			T31	12		T33	596		T34	2
valid_sources[0x73]	59016	1			T31	9		T32	6		T33	439
valid_sources[0x74]	61708	1			T31	16		T32	25		T33	483
valid_sources[0x75]	60918	1			T31	16		T32	40		T33	514
valid_sources[0x76]	60877	1			T31	15		T33	568		T14	5
valid_sources[0x77]	58095	1			T31	9		T32	27		T33	507
valid_sources[0x78]	50445	1			T31	17		T32	18		T33	454
valid_sources[0x79]	53605	1			T31	19		T32	19		T33	415
valid_sources[0x7a]	87032	1			T31	14		T32	48		T33	528
valid_sources[0x7b]	64072	1			T31	15		T32	87		T33	598
valid_sources[0x7c]	58698	1			T31	15		T33	590		T34	3
valid_sources[0x7d]	59814	1			T31	20		T32	2		T33	731
valid_sources[0x7e]	62587	1			T31	11		T32	12		T33	409
valid_sources[0x7f]	63322	1			T31	13		T32	13		T33	573
valid_sources[0x80]	56780	1			T31	12		T32	51		T33	669

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3473559

1

T31

1555

T32

1923

T33

30201

values[0x0]

all_enables

biggest_size

4453712

1

T31

242

T32

300

T33

36044

values[0x1]

all_enables

biggest_size

4452506

1

T31

220

T32

292

T33

35739