Unified Coverage Report :: Module :: prim_filter_ctr

Module : prim_filter_ctr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_filter[0].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[1].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[2].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[3].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[4].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[5].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[6].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[7].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[8].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[9].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[10].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[11].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[12].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[13].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[14].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[15].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[16].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[17].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[18].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[19].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[20].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[21].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[22].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[23].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[24].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[25].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[26].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[27].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[28].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[29].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[30].u_filter	100.00	100.00	100.00			100.00
tb.dut.gen_filter[31].u_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_filter[0].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[1].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[2].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[3].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[4].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[5].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[6].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[7].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[8].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[9].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[10].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[11].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[12].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[13].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[14].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[15].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[16].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[17].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[18].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[19].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[20].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[21].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[22].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[23].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[24].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[25].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[26].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[27].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[28].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[29].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[30].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_filter[31].u_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_filter_ctr

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Module : prim_filter_ctr

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Module : prim_filter_ctr

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[0].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[1].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[2].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[3].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[4].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[5].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[6].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[7].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[8].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[9].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[10].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[11].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[12].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[13].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[14].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[15].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[16].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[17].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[18].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[19].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[20].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[21].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[22].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[23].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[24].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[25].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[26].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[27].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[28].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[29].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[30].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

Line Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	50	3	3	100.00
ALWAYS	58	4	4	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	79	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
50	1	1
51	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
			MISSING_ELSE
66	1	1
67	1	1
69	1	1
74	1	1
75	1	1
79	1	1

---

Cond Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (diff_ctr_d == thresh_i)
            ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 EXPRESSION ((filter_synced != filter_q) ? '0 : ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1))))
             -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION (filter_synced != filter_q)
                -------------1-------------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       75
 SUB-EXPRESSION ((diff_ctr_q >= thresh_i) ? thresh_i : ((diff_ctr_q + 1'b1)))
                 ------------1-----------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T33

 LINE       79
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T31,T32,T34

---

Branch Coverage for Instance : tb.dut.gen_filter[31].u_filter

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	75	3	3	100.00
TERNARY	79	2	2	100.00
IF	50	2	2	100.00
IF	58	3	3	100.00
IF	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_filter_ctr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((filter_synced != filter_q)) ? 
-2-:	75	((diff_ctr_q >= thresh_i)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	79	(enable_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T34
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	58	if ((!rst_ni))
-2-:	60	if (update_stored_value)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T31,T32,T33